CN109558946B - Recognition system based on memristor array - Google Patents
Recognition system based on memristor array Download PDFInfo
- Publication number
- CN109558946B CN109558946B CN201811267920.4A CN201811267920A CN109558946B CN 109558946 B CN109558946 B CN 109558946B CN 201811267920 A CN201811267920 A CN 201811267920A CN 109558946 B CN109558946 B CN 109558946B
- Authority
- CN
- China
- Prior art keywords
- module
- digital
- fpga
- memristor array
- analog conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Artificial Intelligence (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Image Analysis (AREA)
Abstract
The invention discloses a recognition system based on a memristor array, which comprises an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module and the memristor array, wherein the image acquisition module is used for acquiring images; the neural network module is connected with the image acquisition module, the neural network module is connected with the FPGA module through the communication module, the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively, and the memristor array is connected with the digital-to-analog conversion module. The memristor array circuit interface is built, limited input is provided for the memristor array circuit, and abundant research of scientific research personnel on the aspect of memristor technology is facilitated. And a large amount of electronic synapse operation can be replaced, and the energy of researchers and the research cost of research institutions are greatly saved.
Description
Technical Field
The invention relates to the technical field of neural networks, in particular to an identification system based on a memristor array, and particularly relates to a system constructed by upper computer software and a hardware circuit with an FPGA (field programmable gate array) and an embedded development board as cores.
Background
With the development of material technology, the memristor is used as a nonlinear resistor with a memory function, brings great changes to the structural system, principle and design theory of an electronic circuit, is a fourth passive basic circuit element following a resistor, a capacitor and an inductor, and provides potential possibility for further development and improvement of the memory and processing functions in the electronic technology. Although the memristor has been improved in terms of manufacturing process due to the limitation of biological neuroscience, the practical popularization of the memristor in terms of integrated circuits still has many scientific and technical problems to be solved due to the special biological characteristics of the memristor, and the significance of using the memristor as a single component is not great. But the difficulty of integrated use is very difficult, and the memory resistor has a very high threshold for scientific research work and practical application of the memory resistor.
In recent years, analog simulation of an equivalent circuit of a memristor array circuit is increasingly rising, the memristor is realized through the equivalent circuit, although the function of the memristor is simulated in use and theoretically developed, the practical application field does not have corresponding breakthrough application development, and meanwhile, in the aspect of practical application research, the research organization is often burdened by the high cost problem of memristor research.
Disclosure of Invention
The invention aims to: aiming at overcoming the defects in the prior art, the invention adopts a deep learning algorithm aiming at the special requirements of image recognition and a novel device memristor and ensuring that a platform is more intelligent and better practicability, accuracy and richness are obtained; because of the non-directivity of the signal of the memristor device integrated circuit, aiming at the recognition technology research of a specific memristor as a synapse, a research purpose can be realized by designing a simple circuit and adopting a limited input mode; different from the previous development project of the memristor identification technology, the method adopts a software and hardware platform mode to provide limited input for the memristor array circuit, and facilitates the richness research of scientific research personnel in the aspect of the memristor technology. And a large amount of electronic synapse operation can be replaced, and the energy of researchers and the research cost of research institutions are greatly saved.
The technical scheme is as follows:
a recognition system based on a memristor array comprises an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module and the memristor array; the neural network module is connected with the image acquisition module, the neural network module is connected with the FPGA module through the communication module, the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively, and the memristor array is connected with the digital-to-analog conversion module;
the image acquisition module acquires a target image and sends the acquired image to the neural network module;
the neural network module adopts an artificial neural network to identify the image acquired by the image acquisition module and sends the identified result to the FPGA module through the communication module; the scale of the neural network module depends on the number m of input variables and the number n of identification types;
the FPGA module decomposes the data sent by the neural network module into digital signals, transmits the digital signals to the digital-to-analog conversion module one by one, and provides a time sequence for the digital-to-analog conversion module; the FPGA module is connected with the microprocessor module to read, store and calculate data;
the digital-to-analog conversion module is designed into m paths of digital-to-analog converters according to the number of input variables; receiving data transmitted by the FPGA module according to the time sequence provided by the FPGA module, and outputting a corresponding analog signal to the memristor array;
the memristor array is an n-m array formed by connecting diodes and memristors in series and then expanding the diodes and the memristors in a cascading mode; the output end of the memristor array is connected with an operational amplifier, a key switch SW is arranged on a circuit connecting the memristor array and the operational amplifier, the memristor array is connected with a resistor Rx, and the Rx is grounded; the memristor array is connected with the digital-to-analog conversion module and receives an analog signal input by the digital-to-analog conversion module
And processes the input analog signal to output a signal of
Wherein i represents an input variable, i ═ 1,2, …, m; j denotes the identification type, j is 1,2, …, n; wijRepresenting the weights of the corresponding memristors in the memristor array,
the output signal
After the operation and the amplification, the data are sent to the microprocessor module;
the microprocessor module is respectively connected with the FPGA module and the FPGA moduleA memristor array connection for receiving signals processed by the memristor array
And processing the output result
And finally obtaining the recognized image type according to the output result.
The FPGA module processes the decomposed digital signals as follows: if the number is a positive number, sending the digital signal to the microprocessor for storage; if the number is a negative number, marking the signal in a mode of 8-bit tail residue 1 of one byte, and then sending the signal to a digital-to-analog conversion module; during sending, if the FPGA module detects 8-bit end remainder 1 of a digital byte, the digital is determined to be a negative number, at the moment, a pin GPIOX of the FPGA module is put high, the microprocessor module reads a signal of the pin GPIOX, and after the value of the digital-to-analog conversion module is read, the signal is marked to be a negative value; the microprocessor module is used for outputting the output signal
Perform an operation
And the Verf is the working reference voltage of the digital-to-analog conversion module.
The neural network module comprises an identification network module and an identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimension reduction module adopts a convolution and pooling mode in deep learning, adopts a mixed Gaussian distribution model background modeling method to extract a foreground, then carries out contour detection through a Canny operator, and finally carries out image identification through a convolution neural network.
The diode is a Schottky diode.
The diode adopts one of MSR0320, MBR0520, MBR120, MBRS1-40, MBRM110 or MBRS41-0LT 3G.
The image acquisition module adopts independent cameras of various different models or cameras of a computer.
The target image includes a gesture, a letter, and a number.
The FPGA module can adopt FPGA development boards of various models.
The microprocessor module checks whether the identification system operates normally; if the abnormality is detected, returning error information to the identification system through the communication module; the abnormity is that the microprocessor module and the program of the FPGA module run away or the detection data is staggered.
The communication module adopts an I2C, uart, Bluetooth or Nrf2401 wireless module mode according to actual needs.
Has the advantages that: in order to reduce the research threshold of the application field of the memristor and increase the expandability of the memristor, a memristor array circuit interface is built by the upper computer + FPGA + stm 32. Limited input is provided for the memristor array circuit, and the research on the aspect of memristor technology by scientific research personnel is facilitated. And a large amount of electronic synapse operation can be replaced, and the energy of researchers and the research cost of research institutions are greatly saved.
Drawings
FIG. 1 is a block diagram of the system of the present invention.
FIG. 2 is a GUI interface diagram of the present invention.
Fig. 3 is a connection structure diagram of the FPGA.
Fig. 4 is a connection structure diagram of stm 32.
Fig. 5 is a structure diagram of a digital-to-analog converter and memristor array connection.
FIG. 6 is a memristor array circuit connection diagram
FIG. 7 is a memristor array single bank composition schematic.
Fig. 8 is a schematic diagram of the entire hardware configuration.
Fig. 9(a) and 9(b) are equivalent reference diagrams of memristor array processing signals according to the specific embodiment of the present invention.
FIG. 10 is a flow chart of system execution.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
FIG. 1 is a block diagram of the system of the present invention. As shown in fig. 1, the recognition system based on the memristor array of the present invention includes an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module, and the memristor array. The neural network module is connected with the image acquisition module, the neural network module is connected with the FPGA module through the communication module, the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively, and the memristor array is connected with the digital-to-analog conversion module;
the image acquisition module is a camera and is used for acquiring a target image and sending the acquired image to the neural network module; the target image includes gestures, letters, numbers, and the like. The acquisition area of the image acquisition module refers to the range of the camera, and the target image can be acquired and calibrated according to the area. In the invention, the image acquisition module can adopt independent cameras with various different models or cameras carried by a computer.
In the invention, the image acquisition module can select the number of channels and select the threshold value according to the type of the object to be identified and the specific requirement. The threshold is specifically as follows: in order to solve (remove background) the influence caused by interference signals which are received by useful signals with similar frequencies and cannot be filtered by a system, edge pixels are filtered by adopting a weak gradient value, and edge pixels with high gradient values are reserved, and the method can be realized by selecting high and low thresholds. If the gradient value of the edge pixel is above the high threshold, marking it as a strong edge pixel; if the gradient value of the edge pixel is less than the high threshold and greater than the low threshold, marking it as a weak edge pixel; if the gradient value of the edge pixel is smaller than the low threshold value, the image capturing effect can be inhibited, and the best image capturing effect can be obtained.
The neural network module adopts an artificial neural network to identify the image acquired by the image acquisition module and sends the identified result to the FPGA module through the communication module; the scale of the neural network module depends on the number of input variables (m) and the number of recognition types (n) in order to verify and utilize the memristor as a neural synapse recognition function. The neural network module comprises an identification network module and an identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimensionality reduction module adopts a convolution and pooling mode in deep learning, adopts a mixed Gaussian distribution model background modeling method to extract a foreground, then carries out contour detection through a Canny operator, and finally carries out image identification through a convolution neural network; the identification dimensionality reduction module reduces parameters and calculated quantity while keeping main characteristics, prevents overfitting, improves the generalization capability of the model, effectively relieves the quantity of memristors and solves the problem of circuits, effectively improves the identification precision of pictures, and adopts a mode of increasing the depth and width of a network and reducing the parameters.
In the present invention, a GUI interface is provided, and referring to fig. 2, including:
s1, designing an object type selection button which can be clicked according to actual needs, and realizing the addition or replacement of the recognized object types;
s2, a channel selection area, designed with buttons for selecting the number of channels according to specific needs, where the number of channels is the type or number of target acquisitions such as target object images, gestures, motions, etc.
S3, a threshold selecting area, because of the uncertainty of the environmental condition of the collected image, a threshold selecting button is designed by adopting a threshold selecting mode of a slide bar, and the method can meet various places with complicated light.
And S4, an operation platform area is designed with an operation panel for operating the whole technology development platform, and the operation panel is used for operating the platform after the selection and determination of the front object identification type and the channel number, and comprises operation buttons for turning on a camera, extracting a foreground, identifying, automatically identifying, sleeping and exiting.
And S5, a result report area for reporting the program execution result and prompting the operation information for the user.
The FPGA module is connected with the digital-to-analog conversion module, decomposes the data sent by the neural network module into digital signals, transmits the digital signals to the digital-to-analog conversion module one by one, and provides a time sequence for the digital-to-analog conversion module; in order to distinguish the positive and negative of the number processed by the neural network module, the number is processed as follows: if the number is a negative number, marking the signal in a mode of 8-bit tail residue 1 of one byte, and then sending the signal to a digital-to-analog conversion module; during sending, if the FPGA module detects 8-bit end-to-end residue 1 of a digital byte, determining that the digital is a negative number, setting a certain pin GPIOX of the FPGA module high, reading a signal of the pin GPIOX by the microprocessor module, and marking the signal as a negative value after reading the value of the digital-to-analog conversion module; the FPGA module is connected with the microprocessor module to realize timely reading, storing and calculating of data;
in the invention, the FPGA module can adopt FPGA development boards of various models.
As shown in fig. 3 and 4, the digital-to-analog conversion module receives the digital signal transmitted by the FPGA module according to the timing provided by the FPGA module, and outputs an analog signal required by the specified characteristics. The digital-to-analog conversion modules can be cascaded to form a multi-path digital-to-analog converter according to actual requirements, and provide corresponding input signals for the memristor array in actual application.
In the present invention, as shown in fig. 5, the digital-to-analog conversion module adopts a 1 × m digital-to-analog conversion converter, and only provides a voltage input signal for one column of memristors in multiple rows at a time; the timing signal takes 4 (clock pin SCK), 5 (enable pin CS/LD) and 6 (data input Din) on the digital-to-analog conversion module as basic signal input parts and provides a working voltage signal for the multi-path digital-to-analog converter, so that the digital-to-analog converter can output signals required by specified characteristics.
The memristor array is synthesized by adopting various two-dimensional materials, is actually integrated by using devices with strong resistance to voltage change, comprises a plurality of memristor devices, and can process analog signals provided by a digital-to-analog converter;
the memristor array can be designed in a mode as shown in FIG. 6, and is expanded in a mode as shown in FIG. 7. The memristor array is formed by connecting m Schottky diodes with memristors in series and then expanding the m Schottky diodes in a cascading mode; the output end of the memristor array is connected with an operational amplifier; the Schottky diode is connected with the digital-to-analog conversion module, the digital-to-analog conversion module provides an input signal for the memristor array, current flowing through the memristor array is converted into voltage information, and the voltage information is sent to a microprocessor to be read after operational amplification;
in the invention, the performance of the Schottky series diodes adopted as the component diodes in the memristor array is the best, the Schottky series diodes comprise common diodes such as MSR0320, MBR0520, MBR120, MBRS1-40, MBRM110, MBRS41-0LT3G and the like, the forward conduction basically stays at about 0.2-0.3V, the forward conduction voltage of the MBRS410LT3G is the best in this time, and the MBRS410LT3G has the forward conduction voltage of 0.24V by combining with the figure 9(a) and the figure b), and meanwhile, when the reverse voltage is 1V, the minimum current value exists, and the minimum current value is finally matched with the data precision requirement of operation in a neural network.
The memristor array is shown as part B in fig. 6, and each package of the m memristors can rectify the current of the digital-to-analog conversion module by connecting a diode at one end. The diodes are connected to the signal paths provided by the multiple digital-to-analog conversion modules shown in diagram a of fig. 6.
And a key switch SW is arranged on a line connecting the memristor array and the operational amplifier, and the key switch SW adopts a self-locking switch for starting the normal work of the single-row memristor and eliminating the residual charge in the circuit in a pull-down mode.
The memristor array is connected with a resistor Rx, and the Rx is grounded; the Rx is selected from an adjustable precision resistor 3296 and is used for generating the weight W in the memristor array together with the memristor, and the adjusting effect can be improved by adjusting the Rx.
In the invention, the memristor array is an n-m memristor array formed by n rows of 1-m memristor arrays.
In the invention, if the array of the memristors needs to be expanded according to the scale of the neural network module, the corresponding 1 × M digital-to-analog conversion converter can be expanded into a 1 × p (p > M) multi-output mode by the way of cascading with other types of digital-to-analog converters or the digital-to-analog converter of the model.
FIG. 8 is an equivalent reference diagram of memristor array processing signals employed by a specific embodiment of the present disclosure. As shown in fig. 8, the memristor array adopted by the specific embodiment of the present invention is a memristor array of 4 × 8, the scale of the corresponding neural network module is that the number of input variables is 8, and the number of identification types is 4; when the memristor array works normally, after Rx is adjusted, the switch SW is pressed, and the input signal provided by the digital-to-analog conversion module
And obtaining an output signal of
Wherein i represents an input variable, i ═ 1,2, …, 8; j represents the identification type, j is 1,2, …, 4; wijRepresenting the weights of the corresponding memristors in the memristor array,
Rxis a resistor R in an operational amplifier circuitxResistance value of RMijIs the trained resistance of the memristor in the memristor array; then the operational amplifier outputs the signal
And amplifying output and sending the amplified output to the microprocessor module.
The microprocessor module is respectively connected with the FPGA module and the memristor array and receives the signals through the memristor arrayProcessed signal
And processing, marking the positive and negative of the memristor weight in the memristor array, and outputting the result
And finally, obtaining the identified image type according to the output result. The microprocessor reads the pin signal of the FPGA module to judge the positive and negative of the pin signal, and if the pin signal is positive, the processed signal is only needed to be stored; if the output signal is negative, the error caused by 1 in the signal is marked in a mode of distinguishing a byte 8-bit tail 1 introduced by positive and negative locks of the data processed by the neural network module before, and then the output signal is subjected to error detection
Perform an operation
Eliminating errors in the measurement process; and the Verf is the working reference voltage of the digital-to-analog conversion module.
The microprocessor module can also check whether the identification system normally operates, and if the abnormality is detected, error information is returned to the identification system through the communication module; and the abnormity is that the microprocessor module and the FPGA module run away or the data is detected to be staggered.
The communication module can adopt modes such as an I2C, uart, Bluetooth, nrf2401 wireless module and the like according to actual needs, and serial port communication is selected for stability of signal transmission.
The method comprises the following steps:
step 1: the image acquisition module acquires a target image and sends the acquired image to the neural network module;
step 2: the neural network module adopts an artificial neural network to identify the image acquired by the image acquisition module and sends the identified result to the FPGA module through the communication module; the neural network module comprises an identification network module and an identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimensionality reduction module adopts a convolution and pooling mode in deep learning, adopts a mixed Gaussian distribution model background modeling method to extract a foreground, then carries out contour detection through a Canny operator, and finally carries out image identification through a convolution neural network;
and step 3: the FPGA module decomposes the data sent by the neural network module into digital signals, transmits the digital signals to the digital-to-analog conversion module one by one, and provides a time sequence for the digital-to-analog conversion module; in order to distinguish the positive and negative of the number processed by the neural network module, the number is processed as follows: if the number is a negative number, marking the signal in a mode of 8-bit tail residue 1 of one byte, and then sending the signal to a digital-to-analog conversion module; during sending, if the FPGA module detects 8-bit end remainder 1 of a digital byte, the digital is determined to be a negative number, at the moment, a pin GPIOX of the FPGA module is put high, the microprocessor module reads a signal of the pin GPIOX, and after the value of the digital-to-analog conversion module is read, the signal is marked to be a negative value;
and 4, step 4: the digital-to-analog conversion module receives the digital signal transmitted by the FPGA module according to the time sequence provided by the FPGA module and outputs an analog signal with specified characteristic requirements;
and 5: the memristor array receives an input signal provided by the digital-to-analog conversion module
Obtain an output signal of
Then the output signal is output through an operational amplifier
Amplifying the output and sending the amplified output to the microprocessor module;
step 6: the microprocessor module is respectively connected with the FPGA module and the memristor array and receives signals processed by the memristor array
And processing, marking the positive and negative of the memristor weight in the memristor array, and outputting the result
And finally obtaining the recognized image type according to the output result.
The invention integrates a memristor material technology, a deep learning algorithm, a software driving technology, an image processing technology and an automatic control technology into an upper computer + FPGA + stm32 platform, and has the core of constructing and operating the memristor platform, so that the research threshold of the memristor as the application field of the electronic synapse is reduced, and through the expandability of the platform, more identification applications related to the memristor can be realized by using the platform, thereby having very important significance for effectively reducing the cost consumed in the technical research and development of the memristor identification applications.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (10)
1. An identification system based on a memristor array, characterized in that: the intelligent video camera comprises an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module and a memristor array; the neural network module is connected with the image acquisition module, the neural network module is connected with the FPGA module through the communication module, the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively, and the memristor array is connected with the digital-to-analog conversion module;
the image acquisition module acquires a target image and sends the acquired image to the neural network module;
the neural network module adopts an artificial neural network to identify the image acquired by the image acquisition module and sends the identified result to the FPGA module through the communication module; the scale of the neural network module depends on the number m of input variables and the number n of identification types;
the FPGA module decomposes the data sent by the neural network module into digital signals, transmits the digital signals to the digital-to-analog conversion module one by one, and provides a time sequence for the digital-to-analog conversion module; the FPGA module is connected with the microprocessor module to read, store and calculate data;
the digital-to-analog conversion module is designed into m paths of digital-to-analog converters according to the number of input variables; receiving data transmitted by the FPGA module according to the time sequence provided by the FPGA module, and outputting a corresponding analog signal to the memristor array;
the memristor array is an n-m array formed by connecting diodes and memristors in series and then expanding the diodes and the memristors in a cascading mode; the output end of the memristor array is connected with an operational amplifier, a key switch SW is arranged on a circuit connecting the memristor array and the operational amplifier, the memristor array is connected with a resistor Rx, and the Rx is grounded; the memristor array is connected with the digital-to-analog conversion module and receives an analog signal input by the digital-to-analog conversion module
And processes the input analog signal to output a signal of
Wherein i represents an input variable, i ═ 1,2, …, m; j denotes the identification type, j is 1,2, …, n; wijRepresenting the weights of corresponding memristors in the memristor array,
the output signal
After the operation and the amplification, the data are sent to the microprocessor module;
the microprocessor module is respectively connected with the FPGA module and the memristor array and receives signals processed by the memristor array
And processing the output result
And finally, obtaining the identified image type according to the output result.
2. The identification system of claim 1, wherein: the FPGA module processes the decomposed digital signals as follows: if the number is a positive number, sending the digital signal to the microprocessor module for storage; if the number is a negative number, marking the signal by adopting a mode of 8-bit tail residue 1 of one byte, and then sending the signal to a digital-to-analog conversion module; during sending, if the FPGA module detects 8-bit end remainder 1 of a digital byte, the digital is determined to be a negative number, at the moment, a pin GPIOX of the FPGA module is put high, the microprocessor module reads a signal of the pin GPIOX, and after the value of the digital-to-analog conversion module is read, the signal is marked to be a negative value; the microprocessor module is used for outputting the output signal
Perform an operation
And the Verf is the working reference voltage of the digital-to-analog conversion module.
3. The identification system of claim 1, wherein: the neural network module comprises an identification network module and an identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimension reduction module adopts a convolution and pooling mode in deep learning, adopts a mixed Gaussian distribution model background modeling method to extract a foreground, then carries out contour detection through a Canny operator, and finally carries out image identification through a convolution neural network.
4. The identification system of claim 1, wherein: the diode is a Schottky diode.
5. The identification system of claim 4, wherein: the diode adopts one of MSR0320, MBR0520, MBR120, MBRS1-40, MBRM110 or MBRS41-0LT 3G.
6. The identification system of claim 1, wherein: the image acquisition module adopts independent cameras of various different models or cameras of a computer.
7. The identification system of claim 1, wherein: the target image includes a gesture, a letter, and a number.
8. The identification system of claim 1, wherein: the FPGA module can adopt FPGA development boards of various models.
9. The identification system of claim 1, wherein: the microprocessor module checks whether the identification system operates normally; if the abnormality is detected, returning error information to the identification system through the communication module; the abnormity is that the microprocessor module and the program of the FPGA module run away or the detection data is staggered.
10. The identification system of claim 1, wherein: the communication module adopts an I2C, uart, Bluetooth or Nrf2401 wireless module mode according to actual needs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811267920.4A CN109558946B (en) | 2018-10-29 | 2018-10-29 | Recognition system based on memristor array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811267920.4A CN109558946B (en) | 2018-10-29 | 2018-10-29 | Recognition system based on memristor array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109558946A CN109558946A (en) | 2019-04-02 |
| CN109558946B true CN109558946B (en) | 2022-07-12 |
Family
ID=65865528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811267920.4A Active CN109558946B (en) | 2018-10-29 | 2018-10-29 | Recognition system based on memristor array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109558946B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111239548B (en) * | 2020-02-16 | 2022-01-28 | 常熟理工学院 | Circuit fault detection device based on fraction memristor neural network system |
| CN111460365B (en) * | 2020-03-10 | 2021-12-03 | 华中科技大学 | Equation set solver based on memristive linear neural network and operation method thereof |
| CN113178219B (en) * | 2021-04-08 | 2023-10-20 | 电子科技大学 | Memristor sense-memory integrated circuit structure applied to image recognition field |
| CN113285708B (en) * | 2021-05-31 | 2024-02-13 | 郑州轻工业大学 | Four-color guessing circuit based on memristor neural network |
| CN115775028B (en) * | 2021-09-06 | 2024-07-16 | 本源量子计算科技（合肥）股份有限公司 | Quantum circuit optimization method, quantum circuit optimization device, quantum circuit optimization medium and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103810497A (en) * | 2014-01-26 | 2014-05-21 | 华中科技大学 | Memristor based image identification system and method |
| CN105160401A (en) * | 2015-08-27 | 2015-12-16 | 电子科技大学 | WTA neural network based on memristor array and application thereof |
| CN105224986A (en) * | 2015-09-29 | 2016-01-06 | 清华大学 | Based on the deep neural network system of memory resistor |
-
2018
- 2018-10-29 CN CN201811267920.4A patent/CN109558946B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103810497A (en) * | 2014-01-26 | 2014-05-21 | 华中科技大学 | Memristor based image identification system and method |
| CN105160401A (en) * | 2015-08-27 | 2015-12-16 | 电子科技大学 | WTA neural network based on memristor array and application thereof |
| CN105224986A (en) * | 2015-09-29 | 2016-01-06 | 清华大学 | Based on the deep neural network system of memory resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109558946A (en) | 2019-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109558946B (en) | Recognition system based on memristor array | |
| CN105303198B (en) | A kind of remote sensing image semisupervised classification method learnt from fixed step size | |
| CN102422319B (en) | Image retrieval method and image registration method | |
| CN111523470A (en) | Feature fusion block, convolutional neural network, pedestrian re-identification method and related equipment | |
| CN103810497B (en) | Memristor based image identification system and method | |
| CN109858476B (en) | Tag expansion method and electronic equipment | |
| CN110232394A (en) | A kind of multi-scale image semantic segmentation method | |
| DE112016005746T5 (en) | Folding neural network | |
| DE112019000739T5 (en) | TIME SERIES ACQUISITION FOR ANALYZING AND CORRECTING A SYSTEM STATUS | |
| CN105551036A (en) | Training method and device for deep learning network | |
| CN107480178A (en) | A kind of pedestrian's recognition methods again compared based on image and video cross-module state | |
| CN115359353A (en) | Flower identification and classification method and device | |
| CN103077367A (en) | Label detection system and device and label detection method for label detection system | |
| CN116887063B (en) | Trusted image sensing chip based on nonlinear strong physical unclonable function circuit | |
| CN111222558A (en) | Image processing method and storage medium | |
| CN118154968A (en) | Identification error correction method and terminal for classifying dry garbage and wet garbage | |
| CN105447451A (en) | Method and device for retrieving object markers | |
| CN115800274B (en) | 5G distribution network feeder automation self-adaptation method, device and storage medium | |
| CN117269620A (en) | Design method of electronic skin sensing array data acquisition and sensing system | |
| CN112580739B (en) | Method and device for determining training sample set | |
| CN115457366A (en) | Chinese herbal medicine multi-label recognition model based on graph convolution neural network | |
| Wanjun et al. | Yoga action recognition based on STF-ResNet | |
| CN111353349B (en) | Human body key point detection method and device, electronic equipment and storage medium | |
| CN104880216A (en) | Method for sensor fault identification based on cross usage of different error correction codes | |
| CN207802163U (en) | Reading circuit and imaging system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |