CN109558946B - A recognition system based on memristor array - Google Patents

Abstract

The invention discloses a recognition system based on a memristor array, which comprises an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module and the memristor array, wherein the image acquisition module is used for acquiring images; the neural network module is connected with the image acquisition module, the neural network module is connected with the FPGA module through the communication module, the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively, and the memristor array is connected with the digital-to-analog conversion module. The memristor array circuit interface is built, limited input is provided for the memristor array circuit, and abundant research of scientific research personnel on the aspect of memristor technology is facilitated. And a large amount of electronic synapse operation can be replaced, and the energy of researchers and the research cost of research institutions are greatly saved.

Description

A recognition system based on memristor array

technical field

The invention relates to the technical field of neural networks, in particular, a recognition system based on a memristor array is designed, in particular a system constructed by upper computer software and a hardware circuit with an FPGA+embedded development board as the core.

Background technique

With the development of material technology, memristor, as a nonlinear resistor with memory function, has brought great changes in the structural system, principle and design theory of electronic circuits. It is the fourth type after resistance, capacitance and inductance. Passive basic circuit elements offer potential possibilities for the further development of storage and processing functions in electronics. Due to the limitation of biological neuroscience, although the memristor has been improved in the manufacturing process, its special biological characteristics, so there are still many scientific and technological problems to be solved in its practical popularization in integrated circuits. It does not make much sense to use the device as a component alone. However, it is very difficult to integrate and use, and it has a very high threshold for scientific research work and practical application of memristors.

In recent years, the simulation of the equivalent circuit of the memristor array circuit has become increasingly popular. The memristor is realized through the equivalent circuit. Although the function of the memristor is simulated in use, it has been expanded in theory. There is no corresponding breakthrough application development in the field of practical application. At the same time, in the field of practical application research, the high cost of memristor research often makes research institutions overwhelmed.

SUMMARY OF THE INVENTION

Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention is aimed at the special requirements of image recognition and new device memristors, in order to make the platform more intelligent and obtain better practicability, accuracy and richness, using Because of the non-directionality of the signal of the memristor integrated circuit, we can design a simple circuit and use a limited input method to achieve the research purpose for the specific memristor as a synapse identification technology research. ; Different from the previous projects of memristor identification technology development, this time the software + hardware platform is adopted to provide limited input for the memristor array circuit, which is convenient for researchers to enrich the memristor technology. Research. It can replace a large number of electronic synaptic operations, which greatly saves the energy of researchers and the research cost of research institutions.

Technical solutions:

A recognition system based on a memristor array, comprising an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module and a memristor array; the neural network module and the image The acquisition module is connected, the neural network module is connected with the FPGA module through the communication module, the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively, and the memristor array is connected with the the digital-to-analog conversion module is connected;

The image acquisition module collects the target image, and sends the acquired image to the neural network module;

The neural network module adopts an artificial neural network to recognize the images collected by the image acquisition module, and sends the result after the recognition to the FPGA module through the communication module; the scale of the neural network module depends on input variables The number of m and the number of identification types n;

The FPGA module decomposes the data sent by the neural network module into digital signals, and transmits them to the digital-to-analog conversion module one by one, while providing timing for the digital-to-analog conversion module; the FPGA module and the microprocessor The connection of the device module realizes the reading, storage and calculation of data;

The digital-to-analog conversion module is designed into m-way digital-to-analog converters according to the number of input variables; and receives the data transmitted by the FPGA module according to the timing provided by the FPGA module, and outputs corresponding analog signals to the memory. resistor array;

并对所输入的模拟信号进行处理，输出信号为

其中，i表示输入变量，i＝1,2,…,m；j表示识别类型，j＝1,2,…,n；W_ij表示忆阻器阵列中对应忆阻器的权重，

所述输出信号

经运放后，发送至所述微处理器模块；The memristor array is an n*m array formed by connecting a diode and a memristor in series, and then expanding in a cascade manner; the output end of the memristor array is connected with an operational amplifier, and the memristor A key switch SW is arranged on the line connecting the array to the operational amplifier, the memristor array is connected with a resistor Rx, and the Rx is grounded; the memristor array is connected to the digital-to-analog conversion module, and receives all The analog signal input by the digital-to-analog conversion module

And process the input analog signal, the output signal is

Among them, i represents the input variable, i=1,2,...,m; j represents the recognition type, j=1,2,...,n; W _ij represents the weight of the corresponding memristor in the memristor array,

the output signal

After the operational amplifier, it is sent to the microprocessor module;

并处理输出结果

最终根据输出结果得到识别的图像类型。The microprocessor module is respectively connected with the FPGA module and the memristor array, and receives the signal processed by the memristor array

and process the output

Finally, the recognized image type is obtained according to the output result.

进行运算

其中Verf为所述数模转换模块的工作参考电压。The FPGA module performs the following processing on the decomposed digital signal: if the number is a positive number, the digital signal is sent to the microprocessor for storage; if the number is a negative number, a byte with 8 bits at the end is used as the remainder. The signal is marked in the way of 1, and then sent to the digital-to-analog conversion module; when sending, if the FPGA module detects that there is 1 at the end of the 8-bit digital byte, then it is determined that the number is a negative number, and the FPGA module is A certain pin GPIOX of the module is set high, the microprocessor module reads the signal of the pin GPIOX, and after reading the value of the digital-to-analog conversion module, it is marked as a negative value; processor module on the output signal

perform operations

Wherein Verf is the working reference voltage of the digital-to-analog conversion module.

The neural network module includes an identification network module and an identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimension reduction module adopts the convolution in deep learning. And pooling method, using the mixed Gaussian distribution model background modeling method for foreground extraction, and then through the Canny operator for contour detection, and finally through the convolutional neural network for image recognition.

The diode is a Schottky diode.

The diode adopts one of MSR0320, MBR0520, MBR120, MBRS1-40, MBRM110 or MBRS41-0LT3G.

The image acquisition module adopts a variety of independent cameras of different models or cameras provided by the computer.

The target image includes gestures, letters and numbers.

The FPGA module can adopt various types of FPGA development boards.

The microprocessor module verifies whether the identification system operates normally; if an abnormality is detected, the error information is returned to the identification system through the communication module; the abnormality is that the microprocessor module is the same as the FPGA The program of the module runs away or the detection data is misplaced.

The communication module adopts I2C, UART, Bluetooth or Nrf2401 wireless module mode according to actual needs.

Beneficial effects: In order to lower the research threshold of the memristor in the application field and increase its scalability, a memristor array circuit interface is built through the upper computer + FPGA + stm32. Provides limited input for memristor array circuits to facilitate researchers' richness in memristor technology. It can replace a large number of electronic synaptic operations, which greatly saves the energy of researchers and the research cost of research institutions.

Description of drawings

FIG. 1 is a block diagram of the system structure of the present invention.

FIG. 2 is a GUI interface diagram of the present invention.

Fig. 3 is the connection structure diagram of FPGA.

Figure 4 is a connection structure diagram of stm32.

Figure 5 is a structural diagram of the connection between the digital-to-analog converter and the memristor array.

Figure 6 is a circuit connection diagram of a memristor array

FIG. 7 is a schematic diagram of the structure of a single row of a memristor array.

FIG. 8 is a schematic diagram of the overall structure of the hardware.

FIG. 9( a ) and FIG. 9( b ) are equivalent reference diagrams of a signal processed by a memristor array according to a specific embodiment of the present invention.

Figure 10 is a flow chart of system execution.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of the system structure of the present invention. As shown in FIG. 1 , the identification system based on the memristor array of the present invention includes an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module and a memristor array. The neural network module is connected with the image acquisition module, the neural network module is connected with the FPGA module through the communication module, and the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively connected, the memristor array is connected with the digital-to-analog conversion module;

The image acquisition module is a camera, which is used to collect target images and send the collected images to the neural network module; the target images include gestures, letters, numbers, and the like. The acquisition area of the image acquisition module refers to the range captured by the camera, and the target image can be acquired and calibrated according to this area. In the present invention, the image acquisition module can use a variety of independent cameras of different models or cameras built in a computer.

In the present invention, the image acquisition module can select the number of channels and select a threshold value according to the type of object to be identified and specific needs. The specific threshold is as follows: in order to solve (remove the background) the influence of the received interference signals with similar frequencies of useful signals that cannot be filtered out by the system, use weak gradient values to filter edge pixels, and retain edges with high gradient values. pixels, which can be achieved by choosing high and low thresholds. If the gradient value of the edge pixel is higher than the high threshold, it is marked as a strong edge pixel; if the gradient value of the edge pixel is less than the high threshold and greater than the low threshold, it is marked as a weak edge pixel; if the gradient value of the edge pixel is less than If the threshold is low, it will be suppressed, and then the best image acquisition effect can be obtained.

The neural network module adopts an artificial neural network to recognize the images collected by the image acquisition module, and sends the result after the recognition to the FPGA module through the communication module; the scale of the neural network module depends on input variables The number (m) and the number of recognition types (n) are used to verify and utilize the memristor as a synaptic recognition function. The neural network module includes an identification network module and an identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimension reduction module adopts the convolution in deep learning. And pooling method, using the mixed Gaussian distribution model background modeling method to extract the foreground, then use the Canny operator to perform contour detection, and finally use the convolutional neural network to perform image recognition; the recognition dimension reduction module retains the main features while at the same time Reduce the amount of parameters and calculation, prevent over-fitting, improve the generalization ability of the model, effectively alleviate the number of memristors and solve the problem of the circuit, and effectively improve the recognition accuracy of the picture. way of parameters.

In the present invention, a GUI interface is provided, referring to Fig. 2, including:

S1. The object type area is designed with object type selection buttons that can be clicked according to actual needs, which can realize the increase or replacement of the recognized object type;

S2. The channel selection area is designed with buttons that can select the number of channels according to specific needs. The number of channels in this area is the type or number of target acquisitions such as target object images, postures, and actions.

S3. Threshold value selection area, because of the uncertainty of the environmental conditions of the collected images, the threshold value selection method of the slider is used to design the threshold value selection button, which can meet a variety of places with complex lighting.

S4. The operation platform area is designed with an operation panel for operating the entire technology development platform, which is used to operate the platform after the object recognition type and the number of channels are selected and determined in the front, including opening the camera, foreground extraction, recognition, automatic Action buttons for identification, sleep and exit.

S5, the result report area, report the program execution result, and prompt the user for operation information.

The FPGA module is connected to the digital-to-analog conversion module, decomposes the data sent by the neural network module into digital signals, and transmits them to the digital-to-analog conversion module one by one, while providing timing for the digital-to-analog conversion module; In order to distinguish the positive and negative of the number processed by the neural network module, the number is processed as follows: if the number is negative, the signal is marked with 1 at the end of 8 bits of a byte, and then sent to the digital Analog conversion module; when sending, if the FPGA module detects that the 8-bit end of the digital byte is 1, then determine that the number is a negative number, and at this time a certain pin GPIOX of the FPGA module is set high, and the The microprocessor module reads the signal of the pin GPIOX, and after reading the value of the digital-to-analog conversion module, it is marked as a negative value; the FPGA module is connected to the microprocessor module to realize data Timely read, store and calculate;

In the present invention, the FPGA module can adopt various types of FPGA development boards.

As shown in Figure 3 and Figure 4, the digital-to-analog conversion module receives the digital signal transmitted by the FPGA module according to the timing sequence provided by the FPGA module, and outputs the analog signal required by the specified feature. The digital-to-analog conversion modules can be cascaded according to actual requirements to form a multi-channel digital-to-analog converter, and provide corresponding input signals for the practical memristor array.

In the present invention, as shown in FIG. 5 , the digital-to-analog conversion module adopts a 1*m digital-to-analog conversion converter, and only provides a voltage input signal for one column of memristors in multiple rows at a time; the time sequence signal is Take 4 (clock pin SCK), 5 (enable pin CS/LD) and 6 (data input Din) on the digital-to-analog conversion module as the basic signal input part, and provide the multi-channel digital-to-analog converter. The operating voltage signal, so that the digital-to-analog converter can output the signal required by the specified characteristic.

The memristor array is synthesized by using a variety of two-dimensional materials, but in practice, it is integrated with devices with strong resistance to voltage and resistance changes, including multiple memristor devices, and can be used for digital-to-analog converters. analog signal processing;

The memristor array can be designed as shown in FIG. 6 , and expanded as shown in FIG. 7 . The memristor array consists of m Schottky diodes connected in series with the memristor, and then expanded in a cascaded manner to form an n*m array; the output end of the memristor array is connected with an operational amplifier; The kit diode is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module provides an input signal for the memristor array, and converts the current flowing through the memristor array into voltage information. , sent to the microprocessor to read;

In the present invention, the component diodes used in the memristor array have the best performance of using Schottky series diodes, including commonly used diodes such as MSR0320, MBR0520, MBR120, MBRS1-40, MBRM110 and MBRS41-0LT3G , the forward conduction basically stays at about 0.2-0.3V. In this case, the forward conduction voltage of MBRS410LT3G is the best. Combined with Figure 9(a) and (b), it can be seen that the forward conduction voltage of MBRS410LT3G is 0.24V, At the same time, when the reverse voltage is 1V, there is a very small current value, which finally matches the data accuracy requirements of the operation in the neural network.

The memristor array is shown in part B in FIG. 6 , and each of the m memristor packages can be connected to a diode through one end to rectify the current of the digital-to-analog conversion module. The diode is connected to the signal channel provided by the multi-channel digital-to-analog conversion module shown in Figure A in FIG. 6 .

A key switch SW is provided on the line connecting the memristor array and the operational amplifier. The key switch SW is a self-locking switch, which is used to enable the normal operation of the single-row memristor, and use a pull-down method to eliminate the circuit residual charge in .

The memristor array is connected with a resistor Rx, and the Rx is grounded; the Rx selects an adjustable precision resistor 3296, which is used to generate the weight W in the memristor array together with the memristor, and can be adjusted by adjusting Rx improves regulation.

In the present invention, the memristor array is an n*m memristor array formed by n rows of 1*m memristor arrays.

In the present invention, if the array of memristors needs to be expanded according to the scale of the neural network module, the corresponding 1*m digital-to-analog converter can pass the same type of digital-to-analog converter or the digital-to-analog converter of this model. The cascaded mode of the converters is extended to a multi-output mode of 1*p(p>M).

并通过如图8所示的忆阻器阵列，得到输出信号为

其中，i表示输入变量，i＝1,2,…,8； j表示识别类型，j＝1,2,…,4；W_ij表示忆阻器阵列中对应忆阻器的权重，

R_x是运放电路中电阻R_x的阻值，R_Mij是忆阻器阵列中忆阻器的已训练好的阻值；之后运放将输出信号

放大输出，发送至所述微处理器模块。FIG. 8 is an equivalent reference diagram of a memristor array used in a specific embodiment of the present invention to process signals. As shown in FIG. 8 , the memristor array used in the specific embodiment of the present invention adopts a 4*8 memristor array, and the corresponding scale of the neural network module is that the number of input variables is 8, and the number of the recognition type is 8. The number is 4; when the memristor array is working normally, after adjusting Rx, the switch SW is pressed, and the input signal provided by the digital-to-analog conversion module

And through the memristor array shown in Figure 8, the output signal is obtained as

Among them, i represents the input variable, i=1,2,...,8; j represents the recognition type, j=1,2,...,4; W _ij represents the weight of the corresponding memristor in the memristor array,

Rx _is the resistance value of the resistor Rx in the op amp circuit, and R _{Mij is} the trained resistance value of the memristor in the memristor array; then the op amp will output the signal

The amplified output is sent to the microprocessor module.

并处理，标记所述忆阻器阵列中的忆阻器权重的正负，输出结果

最终根据输出结果得到识别的图像类型。所述微处理器读取所述FPGA模块的引脚信号来判断其正负，若为正，只需将处理的信号存储即可；若为负，为了消除之前区分所述神经网络模块处理后的数据的正负锁引入的一个字节8位末尾余1的方式对信号进行标记中1带来的误差，则对所述输出信号

进行运算

消除测量过程中的误差；其中Verf为所述数模转换模块的工作参考电压。The microprocessor module is respectively connected with the FPGA module and the memristor array, and receives the signal processed by the memristor array

And process, mark the positive and negative of the memristor weights in the memristor array, output the result

Finally, the recognized image type is obtained according to the output result. The microprocessor reads the pin signal of the FPGA module to judge whether it is positive or negative. If it is positive, it only needs to store the processed signal; if it is negative, in order to eliminate the previously processed neural network module The positive and negative lock of the data introduces the error caused by the 1 in the signal by marking the signal with the remaining 1 at the end of the 8-bit of a byte, then the output signal is

perform operations

Eliminate errors in the measurement process; where Verf is the working reference voltage of the digital-to-analog conversion module.

The microprocessor module can also verify whether the identification system operates normally, and if an abnormality is detected, the error information is returned to the identification system through the communication module; the abnormality is the microprocessor module. The program of the same FPGA module runs away or detects that the data is misplaced.

The communication module can adopt I2C, uart, bluetooth, nrf2401 wireless module and other methods according to actual needs. In the present invention, serial communication is selected for the stability of signal transmission.

The steps of the present invention are as follows:

Step 1: the image acquisition module collects the target image, and sends the acquired image to the neural network module;

Step 2: The neural network module uses an artificial neural network to recognize the images collected by the image acquisition module, and sends the recognized result to the FPGA module through the communication module; the neural network module includes a recognition network module and identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimension reduction module adopts the convolution and pooling methods in deep learning, and adopts mixed The Gaussian distribution model background modeling method is used to extract the foreground, and then use the Canny operator to perform contour detection, and finally use the convolutional neural network to perform image recognition;

Step 3: The FPGA module decomposes the data sent by the neural network module into digital signals, and transmits them to the digital-to-analog conversion module one by one, while providing timing for the digital-to-analog conversion module; in order to distinguish the neural network The positive or negative of the number processed by the module is processed as follows: if the number is a negative number, the signal is marked with 1 at the end of 8 bits of a byte, and then sent to the digital-to-analog conversion module; When the FPGA module detects that the 8-bit end of the digital byte is more than 1, then it is determined that the number is a negative number, and a certain pin GPIOX of the FPGA module is set high at this time, and the microprocessor module reads To the signal of the pin GPIOX, and after reading the value of the digital-to-analog conversion module, it is marked as a negative value;

Step 4: the digital-to-analog conversion module receives the digital signal transmitted by the FPGA module according to the timing sequence provided by the FPGA module, and outputs the analog signal required by the specified feature;

得到输出信号为

再通过运放将输出信号

放大输出，发送至所述微处理器模块；Step 5: the memristor array receives the input signal provided by the digital-to-analog conversion module

The output signal is obtained as

The output signal is then output by an op amp

Amplify the output and send it to the microprocessor module;

并处理，标记所述忆阻器阵列中的忆阻器权重的正负，输出结果

最终根据输出结果得到识别的图像类型。Step 6: The microprocessor module is respectively connected with the FPGA module and the memristor array, and receives the signal processed by the memristor array

And process, mark the positive and negative of the memristor weights in the memristor array, output the result

Finally, the recognized image type is obtained according to the output result.

In the present invention, the upper computer + FPGA + stm32 platform integrates the memristor material technology, deep learning algorithm, software driving technology, image processing technology and automatic control technology to form the platform, and the core lies in the structure and operation of the memristor platform , which lowers the research threshold of memristor as an electronic synapse. Through its scalability, more identification applications about memristors can be realized by using this platform, so as to effectively reduce the identification of memristors. The cost of such applications in technology research and development is of great significance.

The above is only the preferred embodiment of the present invention, it should be pointed out that: for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can also be made, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.

Claims (10)

1. a recognition system based on memristor array, is characterized in that: comprise image acquisition module, neural network module, communication module, FPGA module, microprocessor module, digital-to-analog conversion module and memristor array; The network module is connected with the image acquisition module, the neural network module is connected with the FPGA module through the communication module, and the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively, so the the memristor array is connected to the digital-to-analog conversion module; The image acquisition module collects the target image, and sends the acquired image to the neural network module; The neural network module adopts an artificial neural network to recognize the images collected by the image acquisition module, and sends the result after the recognition to the FPGA module through the communication module; the scale of the neural network module depends on input variables The number of m and the number of identification types n; The FPGA module decomposes the data sent by the neural network module into digital signals, and transmits them to the digital-to-analog conversion module one by one, while providing timing for the digital-to-analog conversion module; the FPGA module and the microprocessor The connection of the device module realizes the reading, storage and calculation of data; The digital-to-analog conversion module is designed into m-way digital-to-analog converters according to the number of input variables; and receives the data transmitted by the FPGA module according to the timing provided by the FPGA module, and outputs corresponding analog signals to the memristor array; The memristor array is an n*m array formed by connecting a diode and a memristor in series, and then expanding in a cascade manner; the output end of the memristor array is connected with an operational amplifier, and the memristor A key switch SW is arranged on the line connecting the array to the operational amplifier, the memristor array is connected with a resistor Rx, and the Rx is grounded; the memristor array is connected to the digital-to-analog conversion module, and receives all The analog signal input by the digital-to-analog conversion module

And process the input analog signal, the output signal is

Among them, i represents the input variable, i=1,2,...,m; j represents the recognition type, j=1,2,...,n; W _ij represents the weight of the corresponding memristor in the memristor array,

the output signal

After the operational amplifier, it is sent to the microprocessor module; The microprocessor module is respectively connected with the FPGA module and the memristor array, and receives the signal processed by the memristor array

and process the output

Finally, the recognized image type is obtained according to the output result. 2. The identification system according to claim 1 is characterized in that: the digital signal decomposed by the FPGA module is processed as follows: if the number is a positive number, the digital signal is sent to the microprocessor module Storage; if the number is a negative number, the signal is marked with 1 at the end of 8 bits of a byte, and then sent to the digital-to-analog conversion module; when sending, if the FPGA module detects 8 bits of digital bytes There is 1 at the end, then it is determined that the number is a negative number. At this time, a certain pin GPIOX of the FPGA module is set high, and the microprocessor module reads the signal of the pin GPIOX, and reads all the signals. After the value of the digital-to-analog conversion module, it is marked as a negative value; the microprocessor module has a negative impact on the output signal

perform operations

Wherein Verf is the working reference voltage of the digital-to-analog conversion module. 3. The identification system according to claim 1, is characterized in that: described neural network module comprises identification network module and identification dimension reduction module; Described identification network module is determined by setting different weight values and excitation function. Connection method; the identification and dimension reduction module adopts the convolution and pooling methods in deep learning, adopts the mixed Gaussian distribution model background modeling method to extract the foreground, and then uses the Canny operator to perform contour detection, and finally uses the convolutional neural network. Perform image recognition. 4. The identification system according to claim 1, wherein the diode is a Schottky diode. 5 . The identification system according to claim 4 , wherein the diode adopts one of MSR0320, MBR0520, MBR120, MBRS1-40, MBRM110 or MBRS41-OLT3G. 6 . 6 . The identification system according to claim 1 , wherein the image acquisition module adopts a plurality of independent cameras of different models or a camera built-in computer. 7 . 7. The recognition system according to claim 1, wherein the target image includes gestures, letters and numbers. 8 . The identification system according to claim 1 , wherein the FPGA module can adopt various types of FPGA development boards. 9 . 9. The identification system according to claim 1, characterized in that: the microprocessor module verifies whether the identification system operates normally; if an abnormality is detected, the error information is returned to the identification system through the communication module. The identification system is described; the abnormality is that the programs of the microprocessor module and the FPGA module run away or the detection data is misplaced. 10 . The identification system according to claim 1 , wherein the communication module adopts I2C, uart, Bluetooth or Nrf2401 wireless module mode according to actual needs. 11 .

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