CN109558946B - A recognition system based on memristor array - Google Patents
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Abstract
Description
技术领域technical field
本发明涉及神经网络技术领域,尤其设计了一种基于忆阻器阵列的识别系统,具体是一种由上位机软件和以FPGA+嵌入式开发板为核心的硬件电路构建的系统。The invention relates to the technical field of neural networks, in particular, a recognition system based on a memristor array is designed, in particular a system constructed by upper computer software and a hardware circuit with an FPGA+embedded development board as the core.
背景技术Background technique
随着材料技术的发展,忆阻器作为一种有记忆功能的非线性电阻,带来了电子电路的结构体系、原理、设计理论的巨大变革,是继电阻、电容、电感之后的第四种无源基本电路元件,为电子技术中存储和处理功能的进一步发展提高提供了潜在的可能性。由于生物神经科学方面限制,虽然忆阻器已经在制作工艺方面有所改进,但其特殊的生物特性,因而其在集成电路方面实用普及仍有许多的科学技术难题要解决,并且,将忆阻器单独作为一个元器件来使用的意义并不大。但集成使用起来难度十分不易,对科研工作和忆阻器实际应用有着极高的门槛。With the development of material technology, memristor, as a nonlinear resistor with memory function, has brought great changes in the structural system, principle and design theory of electronic circuits. It is the fourth type after resistance, capacitance and inductance. Passive basic circuit elements offer potential possibilities for the further development of storage and processing functions in electronics. Due to the limitation of biological neuroscience, although the memristor has been improved in the manufacturing process, its special biological characteristics, so there are still many scientific and technological problems to be solved in its practical popularization in integrated circuits. It does not make much sense to use the device as a component alone. However, it is very difficult to integrate and use, and it has a very high threshold for scientific research work and practical application of memristors.
近年来,对于忆阻器阵列电路的等效电路的模拟仿真日益兴起,通过等效电路来实现忆阻器,虽然在使用上模拟了忆阻器的功能,在理论上有所拓展,但在实际应用领域并未有相应的较为突破性的应用发展,与此同时在实际应用研究方面,面对忆阻器研究的高成本问题,往往要使得研究机构的不堪重负。In recent years, the simulation of the equivalent circuit of the memristor array circuit has become increasingly popular. The memristor is realized through the equivalent circuit. Although the function of the memristor is simulated in use, it has been expanded in theory. There is no corresponding breakthrough application development in the field of practical application. At the same time, in the field of practical application research, the high cost of memristor research often makes research institutions overwhelmed.
发明内容SUMMARY OF THE INVENTION
发明目的:为了克服现有技术中存在的不足,本发明针对图像识别和新型器件忆阻器的特殊要求,为了使得平台更具智能化,获得更好的实用性、准确度、丰富度,采用了深度学习的算法;因为忆阻器件集成电路的信号的不定向性,针对具体的忆阻器作为突触的识别技术研究,我们可通过设计简单电路,并采用有限输入的方式来实现研究目的;与以往忆阻器识别技术开发的项目不同的的是,本次采用了软件+硬件平台的方式,为忆阻器阵列电路提供有限的输入,方便科研人员在忆阻器技术方面的丰富性研究。并可代替大量的电子突触运算,极大的节省了研究人员的精力和研究机构的研究成本。Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention is aimed at the special requirements of image recognition and new device memristors, in order to make the platform more intelligent and obtain better practicability, accuracy and richness, using Because of the non-directionality of the signal of the memristor integrated circuit, we can design a simple circuit and use a limited input method to achieve the research purpose for the specific memristor as a synapse identification technology research. ; Different from the previous projects of memristor identification technology development, this time the software + hardware platform is adopted to provide limited input for the memristor array circuit, which is convenient for researchers to enrich the memristor technology. Research. It can replace a large number of electronic synaptic operations, which greatly saves the energy of researchers and the research cost of research institutions.
技术方案:Technical solutions:
一种基于忆阻器阵列的识别系统,包括图像采集模块、神经网络模块、通讯模块、FPGA模块、微处理器模块、数模转换模块以及忆阻器阵列;所述神经网络模块与所述图像采集模块连接,所述神经网络模块通过所述通讯模块与所述FPGA模块连接,所述 FPGA模块连接分别与所述微处理器模块和所述数模转换模块连接,所述忆阻器阵列与所述数模转换模块连接;A recognition system based on a memristor array, comprising an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module and a memristor array; the neural network module and the image The acquisition module is connected, the neural network module is connected with the FPGA module through the communication module, the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively, and the memristor array is connected with the the digital-to-analog conversion module is connected;
所述图像采集模块对目标图像进行采集,并将其采集得到的图像发送至所述神经网络模块;The image acquisition module collects the target image, and sends the acquired image to the neural network module;
所述神经网络模块采用人工神经网络对所述图像采集模块采集的图像进行识别,并将识别之后的结果通过所述通讯模块发送至所述FPGA模块;所述神经网络模块的规模取决于输入变量的个数m和识别类型的个数n;The neural network module adopts an artificial neural network to recognize the images collected by the image acquisition module, and sends the result after the recognition to the FPGA module through the communication module; the scale of the neural network module depends on input variables The number of m and the number of identification types n;
所述FPGA模块对所述神经网络模块发送过来的数据分解成数字信号,并将其逐一传送给所述数模转换模块,同时为数模转换模块提供时序;所述FPGA模块与所述微处理器模块连接,实现数据的读取、存储以及计算;The FPGA module decomposes the data sent by the neural network module into digital signals, and transmits them to the digital-to-analog conversion module one by one, while providing timing for the digital-to-analog conversion module; the FPGA module and the microprocessor The connection of the device module realizes the reading, storage and calculation of data;
所述数模转换模块根据输入变量的个数设计成m路数模转换器;并根据所述FPGA模块提供的时序接收所述FPGA模块传送过来的数据,输出对应的的模拟信号至所述忆阻器阵列;The digital-to-analog conversion module is designed into m-way digital-to-analog converters according to the number of input variables; and receives the data transmitted by the FPGA module according to the timing provided by the FPGA module, and outputs corresponding analog signals to the memory. resistor array;
所述忆阻器阵列为由二极管同忆阻器串联之后,再通过级联的方式扩展形成的n*m 阵列;所述忆阻器阵列的输出端连接有运放,在所述忆阻器阵列与所述运放连接的线路上设有按键开关SW,所述忆阻器阵列连接有电阻Rx,所述Rx接地;所述忆阻器阵列与所述数模转换模块连接,并接收所述数模转换模块输入的模拟信号并对所输入的模拟信号进行处理,输出信号为其中,i表示输入变量,i=1,2,…,m;j表示识别类型,j=1,2,…,n;Wij表示忆阻器阵列中对应忆阻器的权重,所述输出信号经运放后,发送至所述微处理器模块;The memristor array is an n*m array formed by connecting a diode and a memristor in series, and then expanding in a cascade manner; the output end of the memristor array is connected with an operational amplifier, and the memristor A key switch SW is arranged on the line connecting the array to the operational amplifier, the memristor array is connected with a resistor Rx, and the Rx is grounded; the memristor array is connected to the digital-to-analog conversion module, and receives all The analog signal input by the digital-to-analog conversion module And process the input analog signal, the output signal is Among them, i represents the input variable, i=1,2,...,m; j represents the recognition type, j=1,2,...,n; W ij represents the weight of the corresponding memristor in the memristor array, the output signal After the operational amplifier, it is sent to the microprocessor module;
所述微处理器模块分别与所述FPGA模块和所述忆阻器阵列连接,接收经所述忆阻器阵列处理过的信号并处理输出结果最终根据输出结果得到识别的图像类型。The microprocessor module is respectively connected with the FPGA module and the memristor array, and receives the signal processed by the memristor array and process the output Finally, the recognized image type is obtained according to the output result.
所述FPGA模块对其分解的数字信号作如下处理:如果所述数字是正数,将所述数字信号发送至所述微处理器存储;如果所述数字是负数,采用一个字节8位末尾余1的方式对信号进行标记,然后发送给数模转换模块;在发送的时候,所述FPGA模块如果检测到数字字节8位末尾余1,那么确定该数字为负数,此时将所述FPGA模块的某一引脚GPIOX置高,所述微处理器模块读取到所述引脚GPIOX的信号,并在读取到所述数模转换模块的值之后,标记为负值;所述微处理器模块对所述输出信号进行运算其中Verf为所述数模转换模块的工作参考电压。The FPGA module performs the following processing on the decomposed digital signal: if the number is a positive number, the digital signal is sent to the microprocessor for storage; if the number is a negative number, a byte with 8 bits at the end is used as the remainder. The signal is marked in the way of 1, and then sent to the digital-to-analog conversion module; when sending, if the FPGA module detects that there is 1 at the end of the 8-bit digital byte, then it is determined that the number is a negative number, and the FPGA module is A certain pin GPIOX of the module is set high, the microprocessor module reads the signal of the pin GPIOX, and after reading the value of the digital-to-analog conversion module, it is marked as a negative value; processor module on the output signal perform operations Wherein Verf is the working reference voltage of the digital-to-analog conversion module.
所述神经网络模块包括识别网络模块和识别降维模块;所述识别网络模块通过设定不同的权重值和激励函数来确定网络的连接方式;所述识别降维模块采用深度学习中的卷积和池化的方式,采用混合高斯分布模型背景建模方法进行前景提取,再通过Canny 算子进行轮廓检测,最后通过卷积神经网络进行图像识别。The neural network module includes an identification network module and an identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimension reduction module adopts the convolution in deep learning. And pooling method, using the mixed Gaussian distribution model background modeling method for foreground extraction, and then through the Canny operator for contour detection, and finally through the convolutional neural network for image recognition.
所述二极管采用肖基特二极管。The diode is a Schottky diode.
所述二极管采用MSR0320、MBR0520、MBR120、MBRS1-40、MBRM110或 MBRS41-0LT3G其中一种。The diode adopts one of MSR0320, MBR0520, MBR120, MBRS1-40, MBRM110 or MBRS41-0LT3G.
所述图像采集模块采用多种不同型号的独立摄像头或者电脑自带的摄像头。The image acquisition module adopts a variety of independent cameras of different models or cameras provided by the computer.
所述目标图像包括手势、字母以及数字。The target image includes gestures, letters and numbers.
所述FPGA模块可采用多种型号的FPGA开发板。The FPGA module can adopt various types of FPGA development boards.
所述微处理器模块校验所述识别系统是否正常运行;若检测到异常之后,则将出错信息通过所述通讯模块返回到所述识别系统;所述异常为微处理器模块同所述FPGA模块的程序跑飞或检测数据发生错位。The microprocessor module verifies whether the identification system operates normally; if an abnormality is detected, the error information is returned to the identification system through the communication module; the abnormality is that the microprocessor module is the same as the FPGA The program of the module runs away or the detection data is misplaced.
所述通讯模块根据实际需要采用I2C、uart、蓝牙或Nrf2401无线模块方式。The communication module adopts I2C, UART, Bluetooth or Nrf2401 wireless module mode according to actual needs.
有益效果:为了使得忆阻器的应用领域研究门槛降低,增添其可扩展性,通过以上位机+FPGA+stm32搭建了一种忆阻器阵列电路接口。为忆阻器阵列电路提供有限的输入,方便科研人员在忆阻器技术方面的丰富性研究。并可代替大量的电子突触运算,极大的节省了研究人员的精力和研究机构的研究成本。Beneficial effects: In order to lower the research threshold of the memristor in the application field and increase its scalability, a memristor array circuit interface is built through the upper computer + FPGA + stm32. Provides limited input for memristor array circuits to facilitate researchers' richness in memristor technology. It can replace a large number of electronic synaptic operations, which greatly saves the energy of researchers and the research cost of research institutions.
附图说明Description of drawings
图1为本发明系统结构框图。FIG. 1 is a block diagram of the system structure of the present invention.
图2为本发明的GUI界面图。FIG. 2 is a GUI interface diagram of the present invention.
图3为FPGA的连接结构图。Fig. 3 is the connection structure diagram of FPGA.
图4为stm32的连接结构图。Figure 4 is a connection structure diagram of stm32.
图5为数模转换器与忆阻器阵列连接结构图。Figure 5 is a structural diagram of the connection between the digital-to-analog converter and the memristor array.
图6为忆阻器阵列电路连接图Figure 6 is a circuit connection diagram of a memristor array
图7为忆阻器阵列单排构成示意图。FIG. 7 is a schematic diagram of the structure of a single row of a memristor array.
图8为硬件整体构成示意图。FIG. 8 is a schematic diagram of the overall structure of the hardware.
图9(a)、图9(b)为本发明具体实施例的忆阻器阵列处理信号的等效参考图。FIG. 9( a ) and FIG. 9( b ) are equivalent reference diagrams of a signal processed by a memristor array according to a specific embodiment of the present invention.
图10为系统执行流程图。Figure 10 is a flow chart of system execution.
具体实施方式Detailed ways
下面结合附图对本发明作更进一步的说明。The present invention will be further described below in conjunction with the accompanying drawings.
图1为本发明系统结构框图。如图1所示,本发明基于忆阻器阵列的识别系统包括图像采集模块、神经网络模块、通讯模块、FPGA模块、微处理器模块、数模转换模块以及忆阻器阵列。所述神经网络模块与所述图像采集模块连接,所述神经网络模块通过所述通讯模块与所述FPGA模块连接,所述FPGA模块连接分别与所述微处理器模块和所述数模转换模块连接,所述忆阻器阵列与所述数模转换模块连接;FIG. 1 is a block diagram of the system structure of the present invention. As shown in FIG. 1 , the identification system based on the memristor array of the present invention includes an image acquisition module, a neural network module, a communication module, an FPGA module, a microprocessor module, a digital-to-analog conversion module and a memristor array. The neural network module is connected with the image acquisition module, the neural network module is connected with the FPGA module through the communication module, and the FPGA module is connected with the microprocessor module and the digital-to-analog conversion module respectively connected, the memristor array is connected with the digital-to-analog conversion module;
所述图像采集模块为摄像头,用于对目标图像进行采集,并将其采集得到的图像发送至所述神经网络模块;所述目标图像包括手势、字母以及数字等。所述图像采集模块的采集区域是参考所述摄像头所摄像的范围,可根据此区域对目标图像采集校准。在本发明中,所述图像采集模块可以采用多种不同型号的独立摄像头或者电脑自带的摄像头。The image acquisition module is a camera, which is used to collect target images and send the collected images to the neural network module; the target images include gestures, letters, numbers, and the like. The acquisition area of the image acquisition module refers to the range captured by the camera, and the target image can be acquired and calibrated according to this area. In the present invention, the image acquisition module can use a variety of independent cameras of different models or cameras built in a computer.
在本发明中,所述图像采集模块可以根据选择需识别的物体类型、依据具体的需要情况来对通道的数目选择以及选择阈值。所述阈值具体如下:为了解决(去除背景)接收到的有用信号频率相近的、系统无法滤除的干扰信号所带来的影响,采用弱梯度值过滤边缘像素,并保留具有高梯度值的边缘像素,可以通过选择高低阈值来实现。如果边缘像素的梯度值高于高阈值,则将其标记为强边缘像素;如果边缘像素的梯度值小于高阈值并且大于低阈值,则将其标记为弱边缘像素;如果边缘像素的梯度值小于低阈值,则会被抑制,进而能够获得最佳取像效果。In the present invention, the image acquisition module can select the number of channels and select a threshold value according to the type of object to be identified and specific needs. The specific threshold is as follows: in order to solve (remove the background) the influence of the received interference signals with similar frequencies of useful signals that cannot be filtered out by the system, use weak gradient values to filter edge pixels, and retain edges with high gradient values. pixels, which can be achieved by choosing high and low thresholds. If the gradient value of the edge pixel is higher than the high threshold, it is marked as a strong edge pixel; if the gradient value of the edge pixel is less than the high threshold and greater than the low threshold, it is marked as a weak edge pixel; if the gradient value of the edge pixel is less than If the threshold is low, it will be suppressed, and then the best image acquisition effect can be obtained.
所述神经网络模块采用人工神经网络对所述图像采集模块采集的图像进行识别,并将识别之后的结果通过所述通讯模块发送至所述FPGA模块;所述神经网络模块的规模取决于输入变量的个数(m)和识别类型的个数(n),目的是对忆阻器充当神经突触识别功能进行验证和利用。所述神经网络模块包括识别网络模块和识别降维模块;所述识别网络模块通过设定不同的权重值和激励函数来确定网络的连接方式;所述识别降维模块采用深度学习中的卷积和池化的方式,采用混合高斯分布模型背景建模方法进行前景提取,再通过Canny算子进行轮廓检测,最后通过卷积神经网络进行图像识别;所述识别降维模块在保留主要的特征同时减少参数和计算量,防止过拟合,提高模型泛化能力,有效的缓解忆阻器的数量和解决电路的问题,并且有效的提升图片的识别精度,采用了增加网络深度和宽度的同时减少参数的方式。The neural network module adopts an artificial neural network to recognize the images collected by the image acquisition module, and sends the result after the recognition to the FPGA module through the communication module; the scale of the neural network module depends on input variables The number (m) and the number of recognition types (n) are used to verify and utilize the memristor as a synaptic recognition function. The neural network module includes an identification network module and an identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimension reduction module adopts the convolution in deep learning. And pooling method, using the mixed Gaussian distribution model background modeling method to extract the foreground, then use the Canny operator to perform contour detection, and finally use the convolutional neural network to perform image recognition; the recognition dimension reduction module retains the main features while at the same time Reduce the amount of parameters and calculation, prevent over-fitting, improve the generalization ability of the model, effectively alleviate the number of memristors and solve the problem of the circuit, and effectively improve the recognition accuracy of the picture. way of parameters.
在本发明中,设置了GUI界面,参考图2,包括:In the present invention, a GUI interface is provided, referring to Fig. 2, including:
S1、物体类型区域,设计有可根据实际需要点击的物体类型选择按钮,可实现识别物体类型的增加或者更换;S1. The object type area is designed with object type selection buttons that can be clicked according to actual needs, which can realize the increase or replacement of the recognized object type;
S2、通道选择区域,设计有可依据具体的需要情况来对通道的数目选择按钮,这里面通道的数目即目标物体图像、姿势、动作等目标采集的类型或者数目。S2. The channel selection area is designed with buttons that can select the number of channels according to specific needs. The number of channels in this area is the type or number of target acquisitions such as target object images, postures, and actions.
S3、阈值选择区域,因为采集图像的环境情况的不确定性,采用了滑条的阈值选定方式设计了阈值选定按钮,能够满足多种光线复杂的场所。S3. Threshold value selection area, because of the uncertainty of the environmental conditions of the collected images, the threshold value selection method of the slider is used to design the threshold value selection button, which can meet a variety of places with complex lighting.
S4、操作平台区域,设计有对于整个技术开发平台进行操作的操作面板,用于在前面的物体识别类型、通道数目选择确定之后,对该平台进行操作,包括打开相机、前景提取、识别、自动识别、休眠及退出的操作按钮。S4. The operation platform area is designed with an operation panel for operating the entire technology development platform, which is used to operate the platform after the object recognition type and the number of channels are selected and determined in the front, including opening the camera, foreground extraction, recognition, automatic Action buttons for identification, sleep and exit.
S5、结果报告区域,将程序执行结果报告出来,并对使用者进行操作信息提示。S5, the result report area, report the program execution result, and prompt the user for operation information.
所述FPGA模块与所述数模转换模块相连,对所述神经网络模块发送过来的数据分解成数字信号,并将其逐一传送给所述数模转换模块,同时为数模转换模块提供时序;为了区分所述神经网络模块处理后的数字的正负,对所述数字作如下处理:如果所述数字是负数,采用一个字节8位末尾余1的方式对信号进行标记,然后发送给数模转换模块;在发送的时候,所述FPGA模块如果检测到数字字节8位末尾余1,那么确定该数字为负数,此时将所述FPGA模块的某一引脚GPIOX置高,所述微处理器模块读取到所述引脚GPIOX的信号,并在读取到所述数模转换模块的值之后,标记为负值;所述 FPGA模块与所述微处理器模块连接,实现数据的及时读取、存储以及计算;The FPGA module is connected to the digital-to-analog conversion module, decomposes the data sent by the neural network module into digital signals, and transmits them to the digital-to-analog conversion module one by one, while providing timing for the digital-to-analog conversion module; In order to distinguish the positive and negative of the number processed by the neural network module, the number is processed as follows: if the number is negative, the signal is marked with 1 at the end of 8 bits of a byte, and then sent to the digital Analog conversion module; when sending, if the FPGA module detects that the 8-bit end of the digital byte is 1, then determine that the number is a negative number, and at this time a certain pin GPIOX of the FPGA module is set high, and the The microprocessor module reads the signal of the pin GPIOX, and after reading the value of the digital-to-analog conversion module, it is marked as a negative value; the FPGA module is connected to the microprocessor module to realize data Timely read, store and calculate;
在本发明中,所述FPGA模块可采用多种型号的FPGA开发板。In the present invention, the FPGA module can adopt various types of FPGA development boards.
如图3、图4所示,所述数模转换模块根据所述FPGA模块提供的时序接收所述 FPGA模块传送过来的数字信号,输出指定特征要求的模拟信号。所述数模转换模块可根据实际需求进行级联形成多路数模转换器,为实际应用的忆阻器阵列提供相应的输入信号。As shown in Figure 3 and Figure 4, the digital-to-analog conversion module receives the digital signal transmitted by the FPGA module according to the timing sequence provided by the FPGA module, and outputs the analog signal required by the specified feature. The digital-to-analog conversion modules can be cascaded according to actual requirements to form a multi-channel digital-to-analog converter, and provide corresponding input signals for the practical memristor array.
在本发明中,如图5所示,所述数模转换模块采用1*m的数模转换转换器,一次只为多排中的一列忆阻器提供电压输入信号;所述的时序信号是以所述数模转换模块上的 4(时钟引脚SCK)、5(使能引脚CS/LD)和6(数据输入Din)为基本的信号输入部分,并为多路数模转换器提供工作电压信号,从而使得数模转换器能够输出指定特征要求的信号。In the present invention, as shown in FIG. 5 , the digital-to-analog conversion module adopts a 1*m digital-to-analog conversion converter, and only provides a voltage input signal for one column of memristors in multiple rows at a time; the time sequence signal is Take 4 (clock pin SCK), 5 (enable pin CS/LD) and 6 (data input Din) on the digital-to-analog conversion module as the basic signal input part, and provide the multi-channel digital-to-analog converter. The operating voltage signal, so that the digital-to-analog converter can output the signal required by the specified characteristic.
所述忆阻器阵列采用多种二维材料进行合成,但在实际中使用抗电压阻值变化特性强的器件进行集成,包含有多个忆阻器件,并能够对数模转换器提供来的模拟信号进行处理;The memristor array is synthesized by using a variety of two-dimensional materials, but in practice, it is integrated with devices with strong resistance to voltage and resistance changes, including multiple memristor devices, and can be used for digital-to-analog converters. analog signal processing;
所述忆阻器阵列可采用如图6的方式进行设计,图7方式进行扩展。所述忆阻器阵列由m个肖基特二极管同忆阻器串联之后,再通过级联的方式扩展形成n*m阵列;所述忆阻器阵列的输出端连接有运放;所述肖基特二极管与所述数模转换模块连接,由所述数模转换模块为所述忆阻器阵列提供输入信号,将流过所述忆阻器阵列的电流转化为电压信息,经运放后,发送至微处理器读取;The memristor array can be designed as shown in FIG. 6 , and expanded as shown in FIG. 7 . The memristor array consists of m Schottky diodes connected in series with the memristor, and then expanded in a cascaded manner to form an n*m array; the output end of the memristor array is connected with an operational amplifier; The kit diode is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module provides an input signal for the memristor array, and converts the current flowing through the memristor array into voltage information. , sent to the microprocessor to read;
在本发明中,所述忆阻器阵列中采用的所述元器件二极管采用肖基特系列的二极管的性能最佳,包括MSR0320、MBR0520、MBR120、MBRS1-40、MBRM110及 MBRS41-0LT3G等常用二极管,正向导通基本都停留在0.2—0.3V左右,在本次中选用 MBRS410LT3G正向导通电压最佳,结合图9(a)、(b)可以看出,MBRS410LT3G 正向导通电压为0.24V,与此同时反向电压为1V时,才存在有极小的电流值,最终与神经网络中运算的数据精度要求所匹配。In the present invention, the component diodes used in the memristor array have the best performance of using Schottky series diodes, including commonly used diodes such as MSR0320, MBR0520, MBR120, MBRS1-40, MBRM110 and MBRS41-0LT3G , the forward conduction basically stays at about 0.2-0.3V. In this case, the forward conduction voltage of MBRS410LT3G is the best. Combined with Figure 9(a) and (b), it can be seen that the forward conduction voltage of MBRS410LT3G is 0.24V, At the same time, when the reverse voltage is 1V, there is a very small current value, which finally matches the data accuracy requirements of the operation in the neural network.
所述忆阻器阵列如图6中B部分所示,所述m个忆阻器的封装中每一个可通过一端连接二极管,对所述数模转换模块的电流进行整流。所述二极管连接至位于图6中A 图所示的多路数模转换模块提供的信号道上。The memristor array is shown in part B in FIG. 6 , and each of the m memristor packages can be connected to a diode through one end to rectify the current of the digital-to-analog conversion module. The diode is connected to the signal channel provided by the multi-channel digital-to-analog conversion module shown in Figure A in FIG. 6 .
在所述忆阻器阵列与所述运放连接的线路上设有按键开关SW,所述按键开关SW选用自锁开关,用于开启单排忆阻器的正常工作,使用下拉的方式消除电路中的残余电荷量。A key switch SW is provided on the line connecting the memristor array and the operational amplifier. The key switch SW is a self-locking switch, which is used to enable the normal operation of the single-row memristor, and use a pull-down method to eliminate the circuit residual charge in .
所述忆阻器阵列连接有电阻Rx,所述Rx接地;所述Rx选用可调精密电阻器3296,用于和忆阻器共同产生所述忆阻器阵列中的权重W,并可通过调节Rx改善调节效果。The memristor array is connected with a resistor Rx, and the Rx is grounded; the Rx selects an adjustable precision resistor 3296, which is used to generate the weight W in the memristor array together with the memristor, and can be adjusted by adjusting Rx improves regulation.
在本发明中,所述忆阻器阵列为n排1*m的忆阻器阵列形成的n*m忆阻器阵列。In the present invention, the memristor array is an n*m memristor array formed by n rows of 1*m memristor arrays.
在本发明中,若根据所述神经网络模块的规模需要扩充忆阻器的阵列,对应的1*m的数模转换转换器,可通过同其他型号的数模转换器或者本型号的数模转换器级联的方式扩充为1*p(p>M)的多路输出模式。In the present invention, if the array of memristors needs to be expanded according to the scale of the neural network module, the corresponding 1*m digital-to-analog converter can pass the same type of digital-to-analog converter or the digital-to-analog converter of this model. The cascaded mode of the converters is extended to a multi-output mode of 1*p(p>M).
图8为本发明具体实施例采用的忆阻器阵列处理信号的等效参考图。如图8所示,本发明具体实施例采用的忆阻器阵列采用的是4*8的忆阻器阵列,对应的所述神经网络模块的规模为输入变量的个数为8,识别类型的个数为4;所述忆阻器阵列正常工作时,调节Rx后,开关SW按下,由所述数模转换模块提供的输入信号并通过如图8所示的忆阻器阵列,得到输出信号为其中,i表示输入变量,i=1,2,…,8; j表示识别类型,j=1,2,…,4;Wij表示忆阻器阵列中对应忆阻器的权重, Rx是运放电路中电阻Rx的阻值,RMij是忆阻器阵列中忆阻器的已训练好的阻值;之后运放将输出信号放大输出,发送至所述微处理器模块。FIG. 8 is an equivalent reference diagram of a memristor array used in a specific embodiment of the present invention to process signals. As shown in FIG. 8 , the memristor array used in the specific embodiment of the present invention adopts a 4*8 memristor array, and the corresponding scale of the neural network module is that the number of input variables is 8, and the number of the recognition type is 8. The number is 4; when the memristor array is working normally, after adjusting Rx, the switch SW is pressed, and the input signal provided by the digital-to-analog conversion module And through the memristor array shown in Figure 8, the output signal is obtained as Among them, i represents the input variable, i=1,2,...,8; j represents the recognition type, j=1,2,...,4; W ij represents the weight of the corresponding memristor in the memristor array, Rx is the resistance value of the resistor Rx in the op amp circuit, and R Mij is the trained resistance value of the memristor in the memristor array; then the op amp will output the signal The amplified output is sent to the microprocessor module.
所述微处理器模块分别与所述FPGA模块和所述忆阻器阵列连接,接收经所述忆阻器阵列处理过的信号并处理,标记所述忆阻器阵列中的忆阻器权重的正负,输出结果最终根据输出结果得到识别的图像类型。所述微处理器读取所述FPGA模块的引脚信号来判断其正负,若为正,只需将处理的信号存储即可;若为负,为了消除之前区分所述神经网络模块处理后的数据的正负锁引入的一个字节8位末尾余1的方式对信号进行标记中1带来的误差,则对所述输出信号进行运算消除测量过程中的误差;其中Verf为所述数模转换模块的工作参考电压。The microprocessor module is respectively connected with the FPGA module and the memristor array, and receives the signal processed by the memristor array And process, mark the positive and negative of the memristor weights in the memristor array, output the result Finally, the recognized image type is obtained according to the output result. The microprocessor reads the pin signal of the FPGA module to judge whether it is positive or negative. If it is positive, it only needs to store the processed signal; if it is negative, in order to eliminate the previously processed neural network module The positive and negative lock of the data introduces the error caused by the 1 in the signal by marking the signal with the remaining 1 at the end of the 8-bit of a byte, then the output signal is perform operations Eliminate errors in the measurement process; where Verf is the working reference voltage of the digital-to-analog conversion module.
所述微处理器模块还可以校验所述识别系统是否正常运行,若检测到异常之后,则将出错信息通过所述通讯模块返回到所述识别系统;所述异常为所述微处理器模块同所述FPGA模块的程序跑飞或检测到数据发生错位等。The microprocessor module can also verify whether the identification system operates normally, and if an abnormality is detected, the error information is returned to the identification system through the communication module; the abnormality is the microprocessor module. The program of the same FPGA module runs away or detects that the data is misplaced.
所述通讯模块可根据实际需要采用I2C、uart、蓝牙、nrf2401无线模块等方式,在本发明中为了信号传输的稳定性,选用了串口通信。The communication module can adopt I2C, uart, bluetooth, nrf2401 wireless module and other methods according to actual needs. In the present invention, serial communication is selected for the stability of signal transmission.
本发明的步骤如下:The steps of the present invention are as follows:
步骤1:所述图像采集模块对目标图像进行采集,并将其采集得到的图像发送至所述神经网络模块;Step 1: the image acquisition module collects the target image, and sends the acquired image to the neural network module;
步骤2:所述神经网络模块采用人工神经网络对所述图像采集模块采集的图像进行识别,并将识别之后的结果通过所述通讯模块发送至所述FPGA模块;所述神经网络模块包括识别网络模块和识别降维模块;所述识别网络模块通过设定不同的权重值和激励函数来确定网络的连接方式;所述识别降维模块采用深度学习中的卷积和池化的方式,采用混合高斯分布模型背景建模方法进行前景提取,再通过Canny算子进行轮廓检测,最后通过卷积神经网络进行图像识别;Step 2: The neural network module uses an artificial neural network to recognize the images collected by the image acquisition module, and sends the recognized result to the FPGA module through the communication module; the neural network module includes a recognition network module and identification dimension reduction module; the identification network module determines the connection mode of the network by setting different weight values and excitation functions; the identification dimension reduction module adopts the convolution and pooling methods in deep learning, and adopts mixed The Gaussian distribution model background modeling method is used to extract the foreground, and then use the Canny operator to perform contour detection, and finally use the convolutional neural network to perform image recognition;
步骤3:所述FPGA模块对所述神经网络模块发送过来的数据分解成数字信号,并将其逐一传送给所述数模转换模块,同时为数模转换模块提供时序;为了区分所述神经网络模块处理后的数字的正负,对所述数字作如下处理:如果所述数字是负数,采用一个字节8位末尾余1的方式对信号进行标记,然后发送给数模转换模块;在发送的时候,所述FPGA模块如果检测到数字字节8位末尾余1,那么确定该数字为负数,此时将所述FPGA模块的某一引脚GPIOX置高,所述微处理器模块读取到所述引脚GPIOX的信号,并在读取到所述数模转换模块的值之后,标记为负值;Step 3: The FPGA module decomposes the data sent by the neural network module into digital signals, and transmits them to the digital-to-analog conversion module one by one, while providing timing for the digital-to-analog conversion module; in order to distinguish the neural network The positive or negative of the number processed by the module is processed as follows: if the number is a negative number, the signal is marked with 1 at the end of 8 bits of a byte, and then sent to the digital-to-analog conversion module; When the FPGA module detects that the 8-bit end of the digital byte is more than 1, then it is determined that the number is a negative number, and a certain pin GPIOX of the FPGA module is set high at this time, and the microprocessor module reads To the signal of the pin GPIOX, and after reading the value of the digital-to-analog conversion module, it is marked as a negative value;
步骤4:所述数模转换模块根据所述FPGA模块提供的时序接收所述FPGA模块传送过来的数字信号,输出指定特征要求的模拟信号;Step 4: the digital-to-analog conversion module receives the digital signal transmitted by the FPGA module according to the timing sequence provided by the FPGA module, and outputs the analog signal required by the specified feature;
步骤5:所述忆阻器阵列接收所述数模转换模块提供的输入信号得到输出信号为再通过运放将输出信号放大输出,发送至所述微处理器模块;Step 5: the memristor array receives the input signal provided by the digital-to-analog conversion module The output signal is obtained as The output signal is then output by an op amp Amplify the output and send it to the microprocessor module;
步骤6:所述微处理器模块分别与所述FPGA模块和所述忆阻器阵列连接,接收经所述忆阻器阵列处理过的信号并处理,标记所述忆阻器阵列中的忆阻器权重的正负,输出结果最终根据输出结果得到识别的图像类型。Step 6: The microprocessor module is respectively connected with the FPGA module and the memristor array, and receives the signal processed by the memristor array And process, mark the positive and negative of the memristor weights in the memristor array, output the result Finally, the recognized image type is obtained according to the output result.
本发明以上位机+FPGA+stm32平台,融合了忆阻器材料技术、深度学习算法、软件驱动技术、图像处理技术和自动控制技术构件了该平台,核心在于对忆阻器平台的构架和操作,使得忆阻器作为电子突触的应用领域研究门槛降低,通过其可扩展性,使得更多的关于忆阻器的识别类应用可利用该平台来实现,从而对有效地降低忆阻器识别类应用在技术研发时所耗费的成本具有十分重要的意义。In the present invention, the upper computer + FPGA + stm32 platform integrates the memristor material technology, deep learning algorithm, software driving technology, image processing technology and automatic control technology to form the platform, and the core lies in the structure and operation of the memristor platform , which lowers the research threshold of memristor as an electronic synapse. Through its scalability, more identification applications about memristors can be realized by using this platform, so as to effectively reduce the identification of memristors. The cost of such applications in technology research and development is of great significance.
以上所述仅是本发明的优选实施方式,应当指出:对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。The above is only the preferred embodiment of the present invention, it should be pointed out that: for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can also be made, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.
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