CN109547044A - Non- CORBA waveform components loaded circuit - Google Patents
Non- CORBA waveform components loaded circuit Download PDFInfo
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- CN109547044A CN109547044A CN201811263202.XA CN201811263202A CN109547044A CN 109547044 A CN109547044 A CN 109547044A CN 201811263202 A CN201811263202 A CN 201811263202A CN 109547044 A CN109547044 A CN 109547044A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
A kind of non-CORBA waveform components loaded circuit disclosed by the invention, being intended to provide one kind can be improved SCA system loads speed, reduce the loaded circuit of reconstitution time, the technical scheme is that: LocalBus bus reader, which is read, carrys out the load information that bootstrap loading Agent logic equipment passes to loading interface driving, the FLASH block that CPLD loading interface is chosen with the road the K FLASH block selector configured is the currently active piece, the non-CORBA waveform components being stored in the currently active piece are provided to M piece DSP and N piece FPGA, start the non-CORBA waveform components before M piece DSP and N piece FPGA loaded in parallel in active block by the road the K reseting signal generator that configures；By the road the K stress state register of load information storage to CPLD, by reading the load information of the road K stress state register in CPLD, acquisition loading result is passed to load Agent logic equipment.
Description
Technical field
The present invention relates to wireless communication field software and radio techniques, and in particular to a kind of software communications architecture it is non-
CORBA (Common Object Request Broker Architecture), Common Object Request Broker Architecture) wave
Shape component loaded circuit and method.
Background technique
Software radio is the important technology of the current communications field, software communications architecture (SCA, Software
Communications Architecture) provide a kind of software frame practiced for soft software radio platforms.
The purpose of SCA is to realize wireless communication apparatus hardware modularity, and software has portable, reusability and interoperability.SCA
Core concept be that a kind of standardized software systems are designed using Object--oriented method, by by different software waveforms
Component, which is loaded into general hardware platform, realizes different functions, needs replacing the update of radio station only wherein
Software waveform can realize.The reusability of software not only shortens the development cycle of radio station, also to a certain extent
Reduce development cost.The load of waveform components is that different software waveform components are loaded into general hardware platform, is
One of most important support technology of the core concept of SCA.
For SCA, be suitable for the naming convention of processor below: general processor GPP represents the processing for supporting CORBA
Device (can be the DSP for supporting CORBA)；Digital signal processor DSP represents the processor for supporting C language, but does not support
CORBA；Field programmable gate array chip FPGA represents the processor for supporting HDL, does not also support CORBA equally.Based on SCA's
In software radio, is provided with internal communication using CORBA middleware between GPP processor, led between GPP and processing unit
Courier realizes example with MHAL.Waveform is achieved independently of terrace part, and design is standardized with realization based on SCA, has good open
Putting property.GPP side waveform component mainly realizes Network layer function, and DSP, FPGA side waveform component realize physical layer and data link layer
Function realizes waveform load based on waveform components loading technique.GPP side waveform component is CORBA waveform components, by GPP hardware
The load method of logical device is loaded.DSP, FPGA side waveform component are non-CORBA waveform components, by DSP hardware or
FPGA hardware can the load method of load logic equipment loaded.DSP/FPGA processor program load be divided into actively load and
Passive load.Actively load is the loading mode for reading data from principal and subordinate's designated port after processor electrification reset and executing.Root
It is parallel bus and universal serial bus according to port, actively load can be divided into parallel active load and serial actively load again.It is parallel main
Dynamic load is the loading mode for reading data from principal and subordinate's parallel port after processor electrification reset and executing, and serial actively load is
The loading mode for reading data from principal and subordinate's parallel port after processor electrification reset and executing.Passive load is replied by cable on processor
Suspended state is in behind position, load controller, which passes through the passive load port input data of processor and starts processor, executes journey
The mode of sequence.Various loading modes respectively have superiority and inferiority.Parallel active loading mode loading velocity is most fast, but processor and memory
Between line it is more.Serial active loaded circuit is simple, but loading velocity is slower.Passive load is more flexible, but needs
It wants special processor to serve as load controller, and often difference is huge for the passive load port of different processor, realizes complicated
It spends higher.With the development of technology, different types of DSP/FPGA processor all has a variety of loading modes, current all
DSP/FPGA processor all has parallel FLASH active loading interface, from Master-slave parallel FLASH after resetting for processor hardware
Middle loading procedure.
Currently, non-CORBA waveform components loading procedure is substantially all the load passively loaded using DSP/FPGA processor
Process.Operation can load logic equipment and loading interface driver on GPP.Can load logic equipment connect by bus to load
Mouth sends loading command and data.Loading interface is responsible for receiving loading command and data, to can load target devices (DSP/
FPGA it) is loaded.There is the following disadvantage in existing some schemes:
One, waveform components are after being read by GPP, then by bus transfer to that can load target devices, by passively loading mould
Formula, which is realized, loads the waveform components that can load target devices, and transmission process needs subpackage to carry out, and process is complicated, is easy error,
And speed is slow, passive loading mode is also slow loading mode in addition, so that entire loading procedure is complicated and load is fast
Degree is slower, is not able to satisfy certain system requirements for needing to be reconfigured quickly.
The two, mode does not support loaded in parallel, and multiple target devices that load can only be loaded serially, when whole system loads
Between be each accumulation for loading the target devices load time, when can be loaded in system target devices it is more when, when system loads
Between it is too slow.
Summary of the invention
The purpose of the present invention is for shortcoming existing for prior art software communications architecture, providing one kind can
Raising can individually load target devices and entire SCA system loads speed, reduce the non-CORBA waveform components load of reconstitution time
Circuit, further object of the present invention are to provide a kind of non-CORBA waveform components loading method based on foregoing circuit.
To achieve the above objectives, a kind of non-CORBA waveform components loaded circuit provided by the invention, comprising: deploy and add
Carry Agent logic equipment, loading interface drives and supports the general processor GPP of CORBA waveform components, deploys loading interface
Complex programmable logic device (CPLD), the parallel NORFLASH memory chip of K=M+N piece, be configured to active loaded in parallel mould
The N piece on-site programmable gate array FPGA and M piece digital signal processor DSP of formula, wherein the loading interface of CPLD contains
LocalBus bus reader, the road K FLASH block selector, the road K reseting signal generator and the road K stress state register, it is special
Sign is: non-CORBA waveform components are stored in local FLASH, and by realizing multiple waveform components to local FLASH piecemeal
Storage；LocalBus bus reader, which is read, carrys out the load letter that bootstrap loading Agent logic equipment passes to loading interface driving
Breath, it is the currently active piece, the currently active piece that CPLD loading interface, which passes through the FLASH block that the road the K FLASH block selector configured is chosen,
The non-CORBA waveform components being stored in the currently active piece are provided to M piece DSP and N piece FPGA, letter is resetted by the road K configured
Non- CORBA waveform components before number generator starting M piece DSP and N piece FPGA active loaded in parallel in active block；M piece DSP and N
Piece FPGA uses active loaded in parallel mode, by load information storage into the road the K stress state register of CPLD, loading interface
It is driven through the load information that LocalBus bus reader reads the road K stress state register in CPLD, obtains M piece DSP and N
The loading result of piece FPGA passes to load Agent logic equipment.
A kind of non-CORBA waveform components loading method based on foregoing circuit, comprising the following steps:
A, the core frame being deployed on GPP calls the load method for the load Agent logic equipment being deployed on GPP, initiates to add
Current-carrying journey；
B, the Open function for the load Agent logic equipment calls loading interface driving being deployed on GPP is sent to loading interface
Open signal checks stress state pin DONE/PROG by the loading interface being deployed on CPLD, returns to stress state and posts
Storage value, loading interface driving return to Open result according to stress state register value
C, load Agent logic equipment will include the corresponding FLASH block selector number of device to be loaded and corresponding FLASH block number
Load information driven by loading interface and via LocalBus bus be sent to loading interface, loading interface passes through LocalBus
Bus reader reads load information and FLASH block number is arranged to reference numeral FLASH block selector, then by setting information
Load Agent logic equipment is returned to via loading interface driving, decides whether to continue subsequent load process；
If D, continuing to load, Agent logic equipment is driven to send to loading interface via LocalBus by loading interface and be loaded
The value of corresponding reseting signal generator is set as 1 by LocalBus bus reader by order, loading interface, and reset signal occurs
After the value 1 that device is set as, reseting signal generator will by export discrete line traffic control Digital Signal Processing DSP HRST pin or
The PROG pin of FPGA starts DSP FPGA bootstrap loading process, and stress state register is by loading result via loading interface
Driving returns to load Agent logic equipment, if load failure, load Agent logic equipment will retransmit loading command；
E, the Colse function of load Agent logic equipment calls loading interface driving terminates load process.
The present invention has the following beneficial effects: compared with the prior art
It is high to load success rate.The present invention is stored in local FLASH using non-CORBA waveform components and can load in target devices, and
By realizing the storage of multiple waveform components to local FLASH piecemeal, by FLASH block selector, reseting signal generator and
The realization of stress state register can load target devices active loaded in parallel waveform components, read sets of waveforms compared to traditional GPP
Part is simultaneously transmitted to the passive loading method of waveform components that can load target devices by bus, reduces the biography of waveform components complexity
Defeated process improves waveform components loading velocity and load success rate.
Loading efficiency is high.The present invention is stored in local FLASH using non-CORBA waveform components and can load in target devices,
And the storage by realizing multiple waveform components to local FLASH piecemeal, by the FLASH block selector of multidiameter delay, reset
Signal generator and stress state register realize multiple loaded in parallel for loading target devices, overcome prior art K piece
Target devices, which can be loaded, serially to be loaded, system loads time too slow defect, system loads time-consuming be only it is existing serial plus
The 1/K of load mode, whole system load time substantially shorten.
Versatility is good.The present invention is that current all DSP/FPGA processors all have load mould using parallel actively load
Formula has fine versatility.
Detailed description of the invention
Further illustrate technical solution of the present invention with reference to the accompanying drawing, but the content protected of the present invention be not limited to
It is lower described.
Fig. 1 is non-CORBA waveform components loaded circuit schematic diagram of the invention.
Fig. 2 is the load flow chart of Fig. 1.
Specific embodiment
Refering to fig. 1.In the embodiment described below, a kind of non-CORBA waveform components loaded circuit, including deploy and add
Carry Agent logic equipment, loading interface drives and supports the general processor GPP of CORBA waveform components, deploys loading interface
Complex programmable logic device (CPLD), the parallel NORFLASH memory chips of K=M+N, be configured to active loaded in parallel mould
The N piece on-site programmable gate array FPGA and M piece digital signal processor DSP of formula, wherein the loading interface of CPLD contains
LocalBus bus reader, the road K FLASH block selector, the road K reseting signal generator and the road K stress state register, it is special
Sign is: non-CORBA waveform components are stored in local FLASH, and by realizing multiple waveform components to local FLASH piecemeal
Storage；LocalBus bus reader reads and carrys out the load letter that bootstrap loading Agent logic equipment passes to loading interface driving
Breath, it is the currently active piece, the currently active piece that CPLD loading interface, which passes through the FLASH block that the road the K FLASH block selector configured is chosen,
The non-CORBA waveform components being stored in the currently active piece are provided to M piece DSP and N piece FPGA, and the road K by configuring resets
Signal generator starts the non-CORBA waveform components before M piece DSP and N piece FPGA active loaded in parallel in active block；M piece DSP and
N piece FPGA uses active loaded in parallel mode, and by load information storage into the road the K stress state register of CPLD, load is connect
Mouth is driven through the load information that LocalBus bus reader reads the road K stress state register in CPLD, obtains M piece DSP
With the loading result of N piece FPGA, load Agent logic equipment is passed to.
GPP is connect by LocalBus bus with CPLD.CPLD input terminal is LocalBus bus reader and K (K=M+
N) root inputs discrete lines, wherein M root input discrete lines are connect with the GPIO pin of M piece DSP, and N root inputs discrete lines and N piece
The DONE pin of FPGA connects；CPLD output end exports discrete lines by M root and connect with the HRST pin of M piece DSP, passes through N root
Output discrete lines are connect with the PROG pin of N piece FPGA, export n ground of discrete lines and K piece FLASH high by K group (every group of n root)
The connection of location pin.
M piece in K piece FLASH chip corresponds to external memory interface EMIF connection M piece DSP by asynchronous parallel interface,
N piece therein corresponds to loaded in parallel interface BPI connection N piece FPGA by asynchronous parallel interface.
After LocalBus bus reader receives the calling-on signal of GPP, the FLASH block number of FLASH block selector is set,
Or after receiving the calling-on signal of GPP, the value of reseting signal generator is set as 1；FLASH block selector passes through n root address
The low and high level that FLASH high n bit address line is contoured to correspond to by control line, using the corresponding FLASH chip chosen as currently having
Block is imitated, it, will by n root address after FLASH block selector receives the block number of LocalBus bus reader setting
The low and high level that FLASH high n bit address line is contoured to correspond to；Or after receiving the calling-on signal of GPP, reseting signal generator
By exporting discrete lines, the PROG pin starting DSP FPGA bootstrap loading process of the HRST pin of DSP perhaps FPGA is controlled；
Stress state register receives LocalBus bus reader and reads signal, by the GPIO pin of DSP or with FPGA's
DONE pin level state is converted into stress state, reads for LocalBus bus reader and sends GPP to.
Refering to Fig. 2.The non-CORBA waveform components loading method of software communications architecture provided in this embodiment, including with
Lower step:
S1: the core frame being deployed on GPP calls the load method for the load Agent logic equipment being deployed on GPP, initiates
Load process；
S2: the Open function of the load Agent logic equipment calls loading interface driving on GPP, the load on CPLD are deployed in
Interface sends Open signal；After loading interface on CPLD receives Open signal, stress state pin DONE/PROG is checked,
Stress state pin DONE/PROG return inspection result is stored to stress state register, according to stress state register
To return Open result；Loading interface driving returns to " Open " whether successful result to loading Agent logic according to Open result
Equipment；
S3: load Agent logic equipment be arranged/load information is written, will include the corresponding FLASH block selector of device to be loaded
The load information of number and corresponding FLASH block number drives the load being sent on CPLD via LocalBus by loading interface
Interface, the loading interface on CPLD read load information by LocalBus bus reader and reference numeral FLASH block are arranged
Selector chooses the corresponding FLASH block of block number, returns to load information to loading interface and drives, and load Agent logic equipment query/
It reads load information and decides whether to continue subsequent load process, if skipping to S5 driving Colse function without load, terminating
Load process.
S4: the function that load Agent logic equipment calls loading interface driving provides sends loading command, and loading command is logical
It crosses loading interface and drives the loading interface being transmitted on CPLD via LocalBus, control corresponding reseting signal generator and generate reset
Signal, corresponding load target devices, which execute, to be loaded and returns to stress state to stress state register；Loading interface on CPLD
Stress state to loading interface is returned to drive；It loads Agent logic equipment and reads stress state information, if stress state is not just
Really, S4 is jumped to, loading interface retransmits loading command and goes to S5 after stress state is correct.
S5: the Colse function of load Agent logic equipment calls loading interface driving terminates load process.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
Under the premise of the principle of the invention, several improvements and modifications can also be made, these improvements and modifications are also considered as protection of the invention
Within the scope of.The content being not described in detail in this specification belongs to the prior art well known to professional and technical personnel in the field.
Claims (10)
1. a kind of non-CORBA waveform components loaded circuit, comprising: deploy load Agent logic equipment, loading interface driving simultaneously
Support the general processor GPP of CORBA waveform components, the complex programmable logic device (CPLD) for deploying loading interface, K=M+
The parallel NOR FLASH memory chip of N piece, the N piece on-site programmable gate array FPGA and M for being configured to active loaded in parallel mode
Piece digital signal processor DSP, wherein the loading interface of CPLD contains LocalBus bus reader, the choosing of the road K FLASH block
Select device, the road K reseting signal generator and the road K stress state register, it is characterised in that: non-CORBA waveform components are stored in this
In ground FLASH, and the storage by realizing multiple waveform components to local FLASH piecemeal；LocalBus bus reader is read
Carry out the load information that bootstrap loading Agent logic equipment passes to loading interface driving, CPLD loading interface passes through the road K configured
The FLASH block that FLASH block selector is chosen is the currently active piece, and the currently active piece is stored in M piece DSP and N piece FPGA offer
Non- CORBA waveform components in the currently active piece start M piece DSP and N piece FPGA by the road the K reseting signal generator configured
Non- CORBA waveform components before active loaded in parallel in active block；M piece DSP and N piece FPGA uses active loaded in parallel mode,
By load information storage into the road the K stress state register of CPLD, loading interface is driven through LocalBus bus reader
The load information of the road K stress state register in CPLD is read, the loading result of M piece DSP and N piece FPGA are obtained, passes to and adds
Carry Agent logic equipment.
2. non-CORBA waveform components loaded circuit as described in claim 1, it is characterised in that: GPP passes through LocalBus bus
It is connect with CPLD.
3. non-CORBA waveform components loaded circuit as described in claim 1, it is characterised in that: CPLD input terminal is
LocalBus bus reader and K=M+N root input discrete lines, wherein M root inputs discrete lines and the GPIO pin of M piece DSP connects
It connects, N root input discrete lines are connect with the DONE pin of N piece FPGA, and output end exports the HRST of discrete lines and M piece DSP by M root
Pin connection, exports discrete lines by N root and connect with the PROG pin of N piece FPGA, exports discrete lines and K piece by every group of n root
The connection of FLASH high n bit address pin.
4. non-CORBA waveform components loaded circuit as described in claim 1, it is characterised in that: the M piece in K piece FLASH chip
External memory interface EMIF connection M piece DSP is corresponded to by asynchronous parallel interface, N piece therein passes through asynchronous parallel interface pair
Answer loaded in parallel interface BPI connection N piece FPGA.
5. non-CORBA waveform components loaded circuit as described in claim 1, it is characterised in that: LocalBus bus reader
After the calling-on signal for receiving GPP, the FLASH block number of FLASH block selector is set, or after receiving the calling-on signal of GPP,
The value of reseting signal generator is set as 1.
6. non-CORBA waveform components loaded circuit as described in claim 1, it is characterised in that: FLASH block selector passes through n
The low and high level that FLASH high n bit address line is contoured to correspond to by root address, using the corresponding FLASH chip chosen as
The currently active piece.
7. non-CORBA waveform components loaded circuit as claimed in claim 5, it is characterised in that: FLASH block selector receives
After the block number of LocalBus bus reader setting, FLASH high n bit address line is contoured to correspond to by n root address
Low and high level；Or after receiving the calling-on signal of GPP, reseting signal generator controls DSP's by output discrete lines
HRST pin perhaps FPGA PROG pin start DSP FPGA bootstrap loading process；Stress state register receives
LocalBus bus reader reads signal, is converted by the GPIO pin of DSP or with the DONE pin level state of FPGA
Stress state reads for LocalBus bus reader and sends GPP to.
8. a kind of non-CORBA waveform components loading method based on foregoing circuit, comprising the following steps: the core being deployed on GPP
Heart frame calls the load method for the load Agent logic equipment being deployed on GPP, initiates load process；It is deployed in GPP simultaneously
On load Agent logic equipment calls loading interface driving Open function to loading interface send Open signal, pass through deployment
Loading interface on CPLD checks stress state pin DONE/PROG, returns to stress state register value, and loading interface drives
It is dynamic that Open result is returned to according to stress state register value；Loading Agent logic equipment will be corresponding comprising device to be loaded
The load information of FLASH block selector number and corresponding FLASH block number is driven by loading interface to be sent out via LocalBus bus
It send to loading interface, loading interface reads load information by LocalBus bus reader and FLASH block number is arranged to right
Should number FLASH block selector, then by setting information via loading interface driving return to load Agent logic equipment, determine
Whether subsequent load process is continued；When continuing load, Agent logic equipment is by loading interface driving via LocalBus to adding
It carries interface and sends loading command, the value of corresponding reseting signal generator is set as by loading interface by LocalBus bus reader
1, after the value 1 that reseting signal generator is set as, reseting signal generator will pass through the discrete line traffic control Digital Signal Processing DSP of output
HRST pin perhaps FPGA PROG pin start DSP FPGA bootstrap loading process, stress state register will load knot
Fruit returns to load Agent logic equipment via loading interface driving, if load failure, load Agent logic equipment will again
Send loading command；The Colse function of Agent logic equipment calls loading interface driving is loaded, load process is terminated.
9. non-CORBA waveform components loading method as claimed in claim 8, it is characterised in that: load Agent logic equipment is set
Set/load information is written, the load of FLASH block number will be numbered and corresponded to comprising the corresponding FLASH block selector of device to be loaded
Information is driven by loading interface and is sent to the loading interface on CPLD via LocalBus, and the loading interface on CPLD passes through
LocalBus bus reader, which reads load information and reference numeral FLASH block selector is arranged, chooses the corresponding FLASH of block number
Block returns to load information to loading interface and drives, loads Agent logic equipment query/reading load information and decide whether to continue
Subsequent load process terminates load process if driving Colse function without load.
10. non-CORBA waveform components loading method as claimed in claim 9, it is characterised in that: load Agent logic equipment tune
Loading command is sent with the function that loading interface driving provides, loading command is driven by loading interface and is transmitted to via LocalBus
Loading interface on CPLD controls corresponding reseting signal generator and generates reset signal, and corresponding load target devices execute load
And stress state is returned to stress state register；Loading interface on CPLD returns to stress state to loading interface and drives；Add
It carries Agent logic equipment and reads stress state information, if stress state is incorrect, loading interface retransmits loading command, directly
To stress state it is correct after, go to load Agent logic equipment calls loading interface driving Colse function, terminate load stream
Journey.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811263202.XA CN109547044A (en) | 2018-10-28 | 2018-10-28 | Non- CORBA waveform components loaded circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811263202.XA CN109547044A (en) | 2018-10-28 | 2018-10-28 | Non- CORBA waveform components loaded circuit |
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| CN109547044A true CN109547044A (en) | 2019-03-29 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112148384A (en) * | 2020-09-27 | 2020-12-29 | 中国民用航空飞行学院 | SCA waveform component loading method and device, readable medium and electronic equipment |
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| CN105388982A (en) * | 2015-11-16 | 2016-03-09 | 中国电子科技集团公司第十研究所 | Multiprocessor power-on reset circuit |
| CN107885517A (en) * | 2017-10-25 | 2018-04-06 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Embedded system handles device program loaded circuit |
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| CN103365691A (en) * | 2013-07-12 | 2013-10-23 | 中国人民解放军总参谋部第六十三研究所 | Distributed-storage-based SCA component loading device and loading method |
| CN105388982A (en) * | 2015-11-16 | 2016-03-09 | 中国电子科技集团公司第十研究所 | Multiprocessor power-on reset circuit |
| CN107885517A (en) * | 2017-10-25 | 2018-04-06 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Embedded system handles device program loaded circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112148384A (en) * | 2020-09-27 | 2020-12-29 | 中国民用航空飞行学院 | SCA waveform component loading method and device, readable medium and electronic equipment |
| CN112148384B (en) * | 2020-09-27 | 2023-04-18 | 中国民用航空飞行学院 | SCA waveform component loading method and device, readable medium and electronic equipment |
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