CN109546278B - Three-dimensional coupler based on through silicon via and preparation method thereof - Google Patents

Three-dimensional coupler based on through silicon via and preparation method thereof Download PDF

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CN109546278B
CN109546278B CN201811246791.0A CN201811246791A CN109546278B CN 109546278 B CN109546278 B CN 109546278B CN 201811246791 A CN201811246791 A CN 201811246791A CN 109546278 B CN109546278 B CN 109546278B
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layer
signal interconnection
column
dielectric layer
vapor deposition
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CN109546278A (en
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卢启军
朱樟明
杨银堂
李跃进
丁瑞雪
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/12—Coupling devices having more than two ports
    • H01P5/16—Conjugate devices, i.e. devices having at least one port decoupled from one other port
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00—Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type

Abstract

The invention discloses a three-dimensional coupler based on a through silicon via and a preparation method thereof, which relate to the field of three-dimensional integrated circuits, and mainly adopt a through silicon via three-dimensional integration technology and a multi-branch structure, and combine with a reactive ion corrosion technology, an electrochemical deposition, a plasma enhanced chemical vapor deposition, a chemical vapor deposition method and other process methods, thereby effectively reducing the length of an interconnection line and the area of a chip, improving the data transmission bandwidth and the integration level, realizing the purposes of simultaneously improving the performance of the integrated circuit, reducing the power consumption, reducing the weight and the volume, and solving the defects of the prior art that the occupied area of the chip is large, the adjustable space of indexes such as the coupling level, the directionality and the like is small, and particularly the isolation level is difficult to improve and the integration requirement is difficult to meet.

Description

Three-dimensional coupler based on through silicon via and preparation method thereof
Technical Field
The invention belongs to the field of three-dimensional integrated circuits, and particularly relates to a three-dimensional coupler based on a through silicon via and a preparation method thereof.
Background
The three-dimensional integration technology distributes the functional modules of the circuit system on different chips (which can be chips with different functions and different processes), and forms a three-dimensional stack by low-temperature bonding. In a three-dimensional Integrated Circuit (3-D IC), electrical connection between upper and lower modules is realized Through Silicon Vias (TSVs), which have a decisive role in the performance of the entire system. The 3-D IC has the advantages of greatly reducing the overall interconnection length, improving the data transmission bandwidth, reducing the chip area, improving the integration level and realizing the heterogeneous integration of the chip, and can realize the purposes of simultaneously improving the performance of an integrated circuit, reducing the power consumption and reducing the weight and the volume.
The microwave coupler is one of the most basic passive devices in a microwave wireless communication system, realizes the distribution of input and output power and phases in an electromagnetic coupling mode, and is mainly applied to modules such as a mixer, a balanced amplifier, a feed network of an antenna array and the like and microwave testing. The 3-D IC vertically stacks the multi-layer modules, and the wireless electromagnetic coupling communication, microwave signal power distribution and microwave signal phase distribution between the upper layer module and the lower layer module need to introduce more couplers, so that the application of the couplers in the 3-D IC is more extensive. The traditional planar microwave coupler not only occupies huge chip area, but also has small adjustable space for indexes such as coupling degree, directionality and the like, and particularly, the isolation degree is difficult to improve. In addition, the discrete three-dimensional microwave coupler based on the low-temperature co-fired ceramic process is difficult to meet the requirement of integration. By utilizing the vertical interconnection characteristic of the TSV, most of the coupler can be realized by using the vertical TSV, the chip area occupied by the coupler can be greatly reduced, the indexes such as the coupling degree and the isolation degree can be effectively improved, and the coupler is particularly compatible with a 3-D IC process. In addition, the multi-section coupler is easier to realize by using the TSV technology, which is particularly important for a high-performance broadband microwave coupler.
Disclosure of Invention
Aiming at the defects in the prior art, the embodiment of the invention provides a three-dimensional coupler based on a through silicon via and a preparation method thereof.
In a first aspect, an embodiment of the present invention provides a three-dimensional coupler based on a through silicon via, including a top-layer top ground layer, a top-layer top signal line, a top-layer top dielectric layer, a top-layer ground pillar, a top-layer top signal interconnection pillar, a top-layer bottom ground layer, a top-layer bottom signal interconnection pillar, a top-layer bottom shielding layer, an upper-layer silicon substrate, an upper-layer first dielectric layer, an upper-layer shielding layer, an upper-layer second dielectric layer, an upper-layer signal interconnection pillar, a middle-layer top first dielectric layer, a middle-layer top shielding layer, a middle-layer top first signal interconnection pillar, a middle-layer top ground layer, a middle-layer top second dielectric layer, a middle-layer top second signal interconnection pillar, a middle-layer top ground pillar, a middle-layer ground pillar, a middle-layer signal interconnection line, a middle-layer bottom ground pillar, Middle-level bottom second dielectric layer, middle level bottom ground plane, middle level bottom first dielectric layer, middle level bottom shielding layer, middle level bottom first signal interconnection post, lower floor's silicon substrate, lower floor's first dielectric layer, lower floor's shielding layer, lower floor's second dielectric layer, lower floor's signal interconnection post, bottom top dielectric layer, bottom top shielding layer, bottom top signal interconnection post, bottom top ground plane, bottom dielectric layer, bottom ground post, bottom signal interconnection post, bottom ground plane, bottom signal line:
the three-dimensional coupler based on the silicon through hole sequentially comprises a top-layer top grounding layer, a top-layer top dielectric layer, a top-layer bottom grounding layer, a top-layer bottom dielectric layer, an upper-layer silicon substrate, a middle-layer top first dielectric layer, a middle-layer top grounding layer, a middle-layer top second dielectric layer, a middle-layer middle dielectric layer, a middle-layer bottom second dielectric layer, a middle-layer bottom grounding layer, a middle-layer bottom first dielectric layer, a lower-layer silicon substrate, a bottom-layer top dielectric layer, a bottom-layer top grounding layer, a bottom-layer bottom dielectric;
the top signal line of the top layer comprises six branches which are symmetrical front to back and left to right, and the distance between the top signal line of the top layer and the ground layer of the top layer is equal everywhere;
the top-layer top dielectric layer is provided with four top-layer grounding columns which are symmetrical front and back and left and right and two top-layer top signal interconnection columns which are symmetrical left and right;
the ground layer at the bottom of the top layer is provided with two through holes which are bilaterally symmetrical, and a top-layer top dielectric layer and a top-layer top signal interconnection column pass through the through holes;
the top layer bottom medium layer is provided with two top layer bottom shielding layers which are bilaterally symmetrical and distributed in an annular through groove, and a top layer bottom signal interconnection column is arranged on the inner side of each top layer bottom shielding layer;
the upper silicon substrate is provided with two upper shielding layers which are bilaterally symmetrical and distributed in an annular through groove, an upper signal interconnection column is arranged on the inner side of each upper shielding layer, an upper first dielectric layer is arranged between each upper shielding layer and the upper silicon substrate, and an upper second dielectric layer is arranged between each upper shielding layer and the corresponding upper signal interconnection column;
the first medium layer at the top of the middle layer is provided with two middle layer top shielding layers which are bilaterally symmetrical and distributed in an annular through groove, and a first signal interconnection column at the top of the middle layer is arranged on the inner side of each middle layer top shielding layer;
the grounding layer at the top of the middle layer is provided with two through holes which are bilaterally symmetrical, and a second dielectric layer at the top of the middle layer and a second signal interconnection column at the top of the middle layer pass through the through holes;
the second medium layer on the top of the middle layer is provided with four middle layer top grounding columns which are symmetrical front and back and left and right and two middle layer top second signal interconnection columns which are symmetrical left and right;
the middle medium layer of the middle layer is provided with four middle ground posts which are symmetrical front and back and left and right and two middle signal interconnection wires which are symmetrical left and right;
the second medium layer at the bottom of the middle layer is provided with four middle layer bottom grounding columns which are symmetrical front and back and left and right and two middle layer bottom second signal interconnection columns which are symmetrical left and right;
the grounding layer at the bottom of the middle layer is provided with two through holes which are bilaterally symmetrical, and a second dielectric layer at the bottom of the middle layer and a second signal interconnection column at the bottom of the middle layer pass through the through holes;
the first medium layer at the bottom of the middle layer is provided with two middle layer bottom shielding layers which are bilaterally symmetrical and distributed in an annular through groove, and a first signal interconnection column at the bottom of the middle layer is arranged on the inner side of each middle layer bottom shielding layer;
the lower silicon substrate is provided with two lower shielding layers which are bilaterally symmetrical and distributed in an annular through groove, the inner side of each lower shielding layer is provided with a lower signal interconnection column, a lower first dielectric layer is arranged between the lower shielding layer and the lower silicon substrate, and a lower second dielectric layer is arranged between the lower shielding layer and the lower signal interconnection column;
the bottom layer top dielectric layer is provided with two bottom layer top shielding layers which are bilaterally symmetrical and distributed in an annular through groove, and a bottom layer top signal interconnection column is arranged on the inner side of each bottom layer top shielding layer;
the ground layer at the top of the bottom layer is provided with two through holes which are bilaterally symmetrical, and a bottom dielectric layer at the bottom of the bottom layer and a signal interconnection column at the bottom of the bottom layer pass through the through holes;
the bottom medium layer is provided with four bottom grounding posts which are symmetrical front and back and left and right and two bottom signal interconnection posts which are symmetrical left and right;
the bottom signal line comprises six branches which are symmetrical front and back and left and right, and the distance between the bottom signal line and the bottom grounding layer is equal everywhere;
the top layer top signal line, the top layer top signal interconnection column, the top layer bottom signal interconnection column, the upper layer signal interconnection column, the middle layer top first signal interconnection column, the middle layer top second signal interconnection column, the middle layer signal interconnection line, the middle layer bottom second signal interconnection column, the middle layer bottom first signal interconnection column, the lower layer signal interconnection column, the bottom layer top signal interconnection column, the bottom layer bottom signal interconnection column and the bottom layer bottom signal line are sequentially connected;
the top layer top grounding layer, the top layer grounding column, the top layer bottom grounding layer, the top layer bottom shielding layer, the upper layer shielding layer, the middle layer top grounding column, the middle layer middle grounding column, the middle layer bottom grounding layer, the middle layer bottom shielding layer, the lower layer shielding layer, the bottom layer top grounding layer, the bottom layer grounding column and the bottom layer bottom grounding layer are sequentially connected;
the top bottom dielectric layer, the upper first dielectric layer and the middle top first dielectric layer are sequentially connected;
the first medium layer at the bottom of the middle layer, the first medium layer at the lower layer and the medium layer at the top of the bottom layer are sequentially connected.
Furthermore, the top bottom ground plane through hole, the top bottom shielding layer, the upper shielding layer, the middle top ground plane through hole, the middle bottom shielding layer, the lower shielding layer, the bottom top shielding layer, and the bottom top ground plane through hole are arranged on the same straight line in the center.
Further, the centers of the top layer top signal interconnection column, the top layer bottom signal interconnection column, the upper layer signal interconnection column, the middle layer top first signal interconnection column, the middle layer top second signal interconnection column, the middle layer bottom first signal interconnection column, the lower layer signal interconnection column, the bottom layer top signal interconnection column and the bottom layer bottom signal interconnection column are located on the same straight line.
Furthermore, the upper part and the lower part of the three-dimensional coupler based on the through silicon via are symmetrical with respect to the middle medium layer of the middle layer.
Furthermore, the top layer top signal line, the top layer top ground layer, the top layer bottom ground layer, the middle layer top ground layer, the middle layer signal interconnection line, the middle layer bottom ground layer, the bottom layer top ground layer, the bottom layer bottom signal line and the bottom layer bottom ground layer are made of copper materials.
Further, the top layer grounding column, the top layer top signal interconnection column, the top layer bottom shielding layer, the upper layer signal interconnection column, the middle layer top shielding layer, the middle layer top first signal interconnection column, the middle layer top second signal interconnection column, the middle layer top grounding column, the middle layer middle grounding column, the middle layer bottom second signal interconnection column, the middle layer bottom first signal interconnection column, the middle layer bottom grounding column, the middle layer bottom shielding layer, the lower layer signal interconnection column, the bottom layer top shielding layer, the bottom layer top signal interconnection column, the bottom layer bottom signal interconnection column, and the bottom layer grounding column are made of copper, tungsten or polysilicon.
Further, the top-layer top dielectric layer, the top-layer bottom dielectric layer, the upper-layer first dielectric layer, the middle-layer top second dielectric layer, the middle-layer middle dielectric layer, the middle-layer bottom second dielectric layer, the middle-layer bottom first dielectric layer, the lower-layer first dielectric layer, the bottom-layer top dielectric layer, and the bottom-layer bottom dielectric layer are made of silicon dioxide or silicon nitride materials.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a three-dimensional coupler based on a through silicon via, including the following steps:
(1) etching an annular blind groove on the lower silicon substrate by using a reactive ion etching technology;
(2) preparing a lower first dielectric layer on the inner surface of the annular blind groove by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
(3) preparing a lower shielding layer on the surface of the lower first dielectric layer by an electrochemical deposition or chemical vapor deposition method and carrying out chemical mechanical polishing on the lower shielding layer;
(4) etching a cylindrical blind hole in the center of the silicon substrate on the inner side of the lower shielding layer by using a reactive ion etching technology;
(5) preparing a dielectric layer on the inner surface of the cylindrical blind hole by using a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(6) preparing a lower signal interconnection column on the surface of the dielectric layer by electrochemical deposition or chemical vapor deposition and carrying out chemical mechanical polishing on the lower signal interconnection column;
(7) etching the lower first dielectric layer, the lower silicon substrate and the dielectric layer by using a reactive ion etching technology to form an annular blind groove in a region between the lower signal interconnection column and the lower shielding layer;
(8) preparing a lower second dielectric layer on the inner surface of the annular blind groove through a vacuum-assisted spin coating process and carrying out chemical mechanical polishing on the lower second dielectric layer;
(9) preparing a bottom layer top dielectric layer on the chemical mechanical polishing surface by a chemical vapor deposition method;
(10) etching an annular blind groove and a cylindrical blind hole on the bottom layer top dielectric layer by using a reactive ion etching technology until the lower shielding layer and the lower signal interconnection column are completely exposed;
(11) preparing a bottom layer top shielding layer and a bottom layer top signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the bottom layer top shielding layer and the bottom layer top signal interconnection column;
(12) preparing a bottom layer top grounding layer containing a through hole on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
(13) preparing a bottom dielectric layer on the surface of the grounding layer on the top of the bottom layer by using a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(14) etching a cylindrical blind hole on the surface of the bottom dielectric layer by using a reactive ion etching technology until the bottom top grounding layer and the bottom top signal interconnection column are completely exposed;
(15) preparing a bottom layer grounding column and a bottom layer bottom signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the bottom layer grounding column and the bottom layer bottom signal interconnection column;
(16) preparing a bottom signal line and a bottom grounding layer on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
(17) turning over the silicon substrate, and thinning the silicon substrate through rough grinding and fine grinding on the back surface of the silicon substrate until the lower shielding layer and the lower signal interconnection column are exposed;
(18) removing a damaged layer on the surface layer on the thinned surface of the back surface of the silicon substrate by dry etching or wet etching;
(19) preparing a first medium layer at the bottom of the middle layer on the surface of the silicon substrate with the surface damage layer removed by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(20) etching an annular blind groove and a cylindrical blind hole on the surface of the first dielectric layer at the bottom of the middle layer by using a reactive ion corrosion technology at the same time until the lower shielding layer and the lower signal interconnection column are completely exposed;
(21) preparing an intermediate layer bottom shielding layer and an intermediate layer bottom first signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer bottom shielding layer and the intermediate layer bottom first signal interconnection column;
(22) preparing a middle-layer bottom grounding layer containing a through hole on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
(23) preparing a second medium layer at the bottom of the middle layer on the surface of the grounding layer at the bottom of the middle layer by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(24) etching a cylindrical blind hole on the surface of the second dielectric layer at the bottom of the middle layer by using a reactive ion etching technology until the grounding layer at the bottom of the middle layer and the first signal interconnection column at the bottom of the middle layer are completely exposed;
(25) preparing an intermediate layer bottom grounding column and an intermediate layer bottom second signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method and carrying out chemical mechanical polishing on the intermediate layer bottom grounding column and the intermediate layer bottom second signal interconnection column;
(26) preparing a middle medium layer on the chemical mechanical polishing surface by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(27) etching a cylindrical blind hole and a rectangular blind groove on the surface of the medium layer in the middle of the middle layer by using a reactive ion etching technology until the grounding column at the bottom of the middle layer and the second signal interconnection column at the bottom of the middle layer are completely exposed;
(28) preparing a middle grounding column and a middle signal interconnection line of the middle layer on the inner surfaces of the cylindrical blind hole and the rectangular blind groove by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the middle grounding column and the middle signal interconnection line of the middle layer to form a first chemical mechanical polishing surface;
(29) etching an annular blind groove on the upper silicon substrate by using a reactive ion etching technology;
(30) preparing an upper first dielectric layer on the inner surface of the annular blind groove by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
(31) preparing an upper shielding layer on the surface of the upper first dielectric layer by electrochemical deposition or chemical vapor deposition and carrying out chemical mechanical polishing on the upper shielding layer;
(32) etching a cylindrical blind hole in the center of the silicon substrate on the inner side of the upper shielding layer by using a reactive ion etching technology;
(33) preparing a dielectric layer on the inner surface of the cylindrical blind hole by using a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(34) preparing an upper signal interconnection column on the surface of the dielectric layer by electrochemical deposition or chemical vapor deposition and carrying out chemical mechanical polishing on the upper signal interconnection column;
(35) etching off an upper first dielectric layer, an upper silicon substrate and the dielectric layer by using a reactive ion etching technology in a region between the upper signal interconnection column and the upper shielding layer to form an annular blind groove;
(36) preparing an upper second dielectric layer on the inner surface of the annular blind groove by a vacuum-assisted spin coating process and carrying out chemical mechanical polishing on the upper second dielectric layer;
(37) preparing a top bottom dielectric layer on the chemically mechanical polished surface by a chemical vapor deposition method;
(38) etching an annular blind groove and a cylindrical blind hole on the top bottom dielectric layer by utilizing a reactive ion etching technology until the upper shielding layer and the upper signal interconnection column are completely exposed;
(39) preparing a top bottom shielding layer and a top bottom signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the top bottom shielding layer and the top bottom signal interconnection column;
(40) preparing a top bottom grounding layer containing a through hole on the chemical mechanical polishing surface by electrochemical deposition or chemical vapor deposition;
(41) preparing a top dielectric layer on the surface of the ground layer at the bottom of the top layer through plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
(42) etching a cylindrical blind hole on the surface of the top dielectric layer by using a reactive ion etching technology until the top bottom grounding layer and the top bottom signal interconnection column are completely exposed;
(43) preparing a top layer grounding column and a top layer top signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the top layer grounding column and the top layer top signal interconnection column;
(44) preparing a top signal line and a top ground layer on the chemical mechanical polishing surface by electrochemical deposition or chemical vapor deposition;
(45) turning over the silicon substrate, and thinning the silicon substrate through rough grinding and fine grinding on the back surface of the silicon substrate until the upper shielding layer and the upper signal interconnection column are exposed;
(46) removing a damaged layer on the surface layer on the thinned surface of the back surface of the silicon substrate by dry etching or wet etching;
(47) preparing a first dielectric layer on the top of the middle layer on the surface of the silicon substrate with the surface damage layer removed by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(48) etching an annular blind groove and a cylindrical blind hole on the first medium layer on the top of the middle layer by using a reactive ion corrosion technology until the upper shielding layer and the upper signal interconnection column are completely exposed;
(49) preparing an intermediate layer top shielding layer and an intermediate layer top first signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer top shielding layer and the intermediate layer top first signal interconnection column;
(50) preparing a middle layer top grounding layer containing a through hole on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
(51) preparing a second dielectric layer on the top of the middle layer on the surface of the grounding layer on the top of the middle layer by using a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(52) etching a cylindrical blind hole on the surface of the second dielectric layer on the top of the middle layer by using a reactive ion etching technology until the grounding layer on the top of the middle layer and the first signal interconnection column on the top of the middle layer are completely exposed;
(53) preparing an intermediate layer top grounding column and an intermediate layer top second signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer top grounding column and the intermediate layer top second signal interconnection column to form a second chemical mechanical polishing surface;
(54) and bonding the first chemical mechanical polishing surface and the second chemical mechanical polishing surface in a face-to-face mode through a dielectric bonding method and a metal bonding method.
The through-silicon-via three-dimensional coupler and the preparation method thereof provided by the embodiment of the invention have the following beneficial effects:
(1) the invention is based on the through silicon via technology, and is easy to realize three-dimensional integration;
(2) the invention adopts three-dimensional and multi-branch knots, is compact and occupies small area;
(3) the invention separates the signal line and the silicon substrate by the grounding layer and the shielding layer, and the transmission loss is small;
(4) the vertical signal line part of the invention belongs to the sealing, has little influence on the electromagnetic characteristics of other silicon through holes around, can simplify the electromagnetic isolation design, and improves the utilization rate of the chip area and the overall performance of the three-dimensional integrated circuit.
Drawings
FIG. 1a is a side view of a three-dimensional through-silicon-via based coupler according to an embodiment of the present invention;
FIG. 1b is a top view of a three-dimensional through-silicon-via based coupler according to an embodiment of the present invention;
FIGS. 2a to 26a are schematic process flow diagrams of a method for manufacturing a three-dimensional through silicon via-based coupler according to an embodiment of the present invention;
fig. 2b to 26b are schematic process flow diagrams of a method for manufacturing a three-dimensional coupler based on a through silicon via according to an embodiment of the present invention.
Description of reference numerals:
101-top bottom dielectric layer 102-top bottom shield layer
103-top bottom signal interconnect stud 104-top bottom ground plane
105-top dielectric layer 106-top signal interconnect pillar
107-top ground stud 108-top ground plane
109-top signal line 201-upper silicon substrate
202-upper first dielectric layer 203-upper shielding layer
204-upper signal interconnect stud 205-upper second dielectric layer
301-interlayer top first dielectric layer 302-interlayer top shield
303-middle layer top first signal interconnect stud 304-middle layer top ground plane
305-middle layer top second dielectric layer 306-middle layer top second signal interconnect pillar
307-middle layer top ground stud 308-middle layer middle dielectric layer
309-middle ground pillar 310-middle signal interconnect
311-middle layer bottom first dielectric layer 312-middle layer bottom shield layer
313-middle layer bottom first signal interconnect pillar 314-middle layer bottom ground plane
315-middle layer bottom second dielectric layer 316-middle layer bottom second signal interconnect pillar
317-middle layer bottom ground stud 401-lower silicon substrate
402-lower first dielectric layer 403-lower shield layer
404-lower signal interconnect stud 405-lower second dielectric layer
501 bottom top dielectric layer 502 bottom top shield layer
503-bottom layer top signal interconnect stud 504-bottom layer top ground plane
505-bottom dielectric layer 506-bottom signal interconnect pillar
507-bottom ground stud 508-bottom ground plane
509-bottom layer bottom signal line
Detailed Description
As shown in fig. 1, a three-dimensional coupler based on through-silicon-via according to an embodiment of the present invention includes a top ground layer 108, a top signal line 109, a top dielectric layer 105, a top ground pillar 107, a top signal interconnect pillar 106, a top bottom ground layer 104, a top bottom dielectric layer 101, a top signal interconnect pillar 103, a top bottom shielding layer 102, an upper silicon substrate 201, an upper first dielectric layer 202, an upper shielding layer 203, an upper second dielectric layer 205, an upper signal interconnect pillar 204, a middle top first dielectric layer 301, a middle top shielding layer 302, a middle top first signal interconnect pillar 303, a middle top ground layer 304, a middle top second dielectric layer 305, a middle top second signal interconnect pillar 306, a middle top ground pillar 307, a middle dielectric layer 308, a middle ground pillar 309, and a middle ground pillar, Middle layer signal interconnection line 310, middle layer bottom grounding column 317, middle layer bottom second signal interconnection column 316, middle layer bottom second dielectric layer 315, middle layer bottom grounding layer 314, middle layer bottom first dielectric layer 311, middle layer bottom shielding layer 312, middle layer bottom first signal interconnection column 313, lower layer silicon substrate 401, lower layer first dielectric layer 402, lower layer shielding layer 403, lower layer second dielectric layer 405, lower layer signal interconnection column 404, bottom layer top dielectric layer 501, bottom layer top shielding layer 502, bottom layer top signal interconnection column 503, bottom layer top grounding layer 504, bottom layer bottom dielectric layer 505, bottom layer grounding column 507, bottom layer bottom signal interconnection column 506, bottom layer bottom grounding layer 508, bottom layer bottom signal line 509;
the three-dimensional coupler is sequentially provided with a top-layer top grounding layer 108, a top-layer top dielectric layer 105, a top-layer bottom grounding layer 104, a top-layer bottom dielectric layer 101, an upper-layer silicon substrate 201, a middle-layer top first dielectric layer 301, a middle-layer top grounding layer 304, a middle-layer top second dielectric layer 305, a middle-layer middle dielectric layer 308, a middle-layer bottom second dielectric layer 315, a middle-layer bottom grounding layer 314, a middle-layer bottom first dielectric layer 311, a lower-layer silicon substrate 401, a bottom-layer top dielectric layer 501, a bottom-layer top grounding layer 504, a bottom-layer bottom dielectric layer 505;
the top signal line 109 comprises six branches which are symmetrical front to back and left to right, and the distance between the top signal line 109 and the top ground layer 108 is equal everywhere;
the top dielectric layer 105 is provided with four top grounding posts 107 which are symmetrical front and back and left and right and two top signal interconnection posts 106 which are symmetrical left and right;
the top bottom ground layer 104 is provided with two through holes which are bilaterally symmetrical, and a top dielectric layer 105 and a top signal interconnection column 106 pass through the through holes;
the top bottom dielectric layer 101 is provided with two top bottom shielding layers 102 which are bilaterally symmetrical and distributed in an annular through groove, and a top bottom signal interconnection column 103 is arranged on the inner side of each top bottom shielding layer 102;
the upper silicon substrate 201 is provided with two upper shielding layers 203 which are bilaterally symmetrical and distributed in an annular through groove, the inner side of each upper shielding layer 203 is provided with an upper signal interconnection column 204, an upper first dielectric layer 202 is arranged between the upper shielding layer 203 and the upper silicon substrate 201, and an upper second dielectric layer 205 is arranged between the upper shielding layer 203 and the upper signal interconnection column 204;
the middle layer top first dielectric layer 301 is provided with two middle layer top shielding layers 302 which are bilaterally symmetrical and distributed in an annular through groove, and a middle layer top first signal interconnection column 303 is arranged on the inner side of each middle layer top shielding layer 302;
the middle layer top ground layer 304 is provided with two through holes which are bilaterally symmetrical, and a middle layer top second dielectric layer 305 and a middle layer top second signal interconnection column 306 pass through the through holes;
the middle layer top second medium layer 305 is provided with four middle layer top grounding posts 307 which are symmetrical front and back and left and right and two middle layer top second signal interconnection posts 306 which are symmetrical left and right;
the middle layer middle dielectric layer 308 is provided with four middle layer middle grounding posts 309 which are symmetrical front and back and left and right and two middle layer signal interconnecting wires 310 which are symmetrical left and right;
the middle layer bottom second dielectric layer 315 is provided with four middle layer bottom grounding posts 317 which are symmetrical front and back and left and right and two middle layer bottom second signal interconnection posts 316 which are symmetrical left and right;
the middle-layer bottom ground layer 314 is provided with two through holes which are bilaterally symmetrical, and a middle-layer bottom second dielectric layer 315 and a middle-layer bottom second signal interconnection column 316 pass through the through holes;
the first middle layer bottom 311 is provided with two middle layer bottom shielding layers 312 which are bilaterally symmetrical and distributed in an annular through groove, and a middle layer bottom first signal interconnection column 313 is arranged on the inner side of each middle layer bottom shielding layer 312;
the lower silicon substrate 401 is provided with two lower shielding layers 403 which are bilaterally symmetrical and distributed in an annular through groove, the inner side of each lower shielding layer 403 is provided with a lower signal interconnection column 404, a lower first dielectric layer 402 is arranged between the lower shielding layer 403 and the lower silicon substrate 401, and a lower second dielectric layer 405 is arranged between the lower shielding layer 403 and the lower signal interconnection column 404;
the bottom-layer top dielectric layer 501 is provided with two bottom-layer top shielding layers 502 which are bilaterally symmetrical and distributed in an annular through groove, and a bottom-layer top signal interconnection column 503 is arranged on the inner side of each bottom-layer top shielding layer 502;
the bottom top ground layer 504 is provided with two through holes which are bilaterally symmetrical, and a bottom dielectric layer 505 and a bottom signal interconnection column 506 pass through the through holes;
the bottom layer bottom dielectric layer 505 is provided with four bottom layer grounding posts 507 which are symmetrical front and back and left and right and two bottom layer signal interconnection posts 506 which are symmetrical left and right;
the bottom signal line 509 comprises six branches which are symmetrical front and back and left and right, and the distance between the bottom signal line 509 and the bottom ground layer 508 is equal everywhere;
the top-layer top signal line 109, the top-layer top signal interconnection column 106, the top-layer bottom signal interconnection column 103, the upper-layer signal interconnection column 204, the middle-layer top first signal interconnection column 303, the middle-layer top second signal interconnection column 306, the middle-layer signal interconnection line 310, the middle-layer bottom second signal interconnection column 316, the middle-layer bottom first signal interconnection column 313, the lower-layer signal interconnection column 404, the bottom-layer top signal interconnection column 503, the bottom-layer bottom signal interconnection column 506, and the bottom-layer bottom signal line 509 are sequentially connected;
the top ground layer 108, the top ground post 107, the top bottom ground layer 104, the top bottom shielding layer 102, the upper shielding layer 203, the middle top shielding layer 302, the middle top ground layer 304, the middle top ground post 307, the middle ground post 309, the middle bottom ground post 317, the middle bottom ground layer 314, the middle bottom shielding layer 312, the lower shielding layer 403, the bottom top shielding layer 502, the bottom top ground layer 504, the bottom ground post 507, and the top bottom ground layer 508 are sequentially connected;
the top bottom dielectric layer 101, the upper first dielectric layer 202 and the middle top first dielectric layer 301 are sequentially connected;
the middle bottom first dielectric layer 311, the lower first dielectric layer 402, and the bottom top dielectric layer 501 are shown connected in sequence.
The top bottom ground plane via, the top bottom shield 102, the upper shield 203, the middle top shield 302, the middle top ground plane via, the middle bottom shield 312, the lower shield 403, the bottom top shield 502, and the bottom top ground plane via are aligned with one another.
The centers of the top-layer top signal interconnection column 106, the top-layer bottom signal interconnection column 103, the upper-layer signal interconnection column 204, the middle-layer top first signal interconnection column 303, the middle-layer top second signal interconnection column 306, the middle-layer bottom second signal interconnection column 316, the middle-layer bottom first signal interconnection column 313, the lower-layer signal interconnection column 404, the bottom-layer top signal interconnection column 503 and the bottom-layer bottom signal interconnection column 506 are located on the same straight line.
The three-dimensional coupler is vertically symmetric about the middle interlevel dielectric layer 308.
Optionally, the top layer top signal line 109, the top layer top ground layer 108, the top layer bottom ground layer 104, the middle layer top ground layer 304, the middle layer signal interconnection line 310, the middle layer bottom ground layer 314, the bottom layer top ground layer 504, the bottom layer bottom signal line 509, and the bottom layer bottom ground layer 508 are made of copper or tungsten.
Optionally, the top ground stud 107, the top signal interconnect stud 106, the top signal interconnect stud 103, the top shield layer 102, the top shield layer 203, the top signal interconnect stud 204, the middle shield layer 302, the middle first signal interconnect stud 303, the middle second signal interconnect stud 306, the middle top ground stud 307, the middle ground stud 309, the middle second signal interconnect stud 316, the middle first signal interconnect stud 313, the middle bottom ground stud 317, the middle bottom shield layer 312, the lower shield layer 403, the lower signal interconnect stud 404, the bottom top shield layer 502, the bottom top signal interconnect stud 503, the bottom signal interconnect stud 506, and the bottom ground stud 507 are made of copper, tungsten, or polysilicon.
Optionally, the top dielectric layer 105, the top bottom dielectric layer 101, the upper first dielectric layer 202, the middle top first dielectric layer 301, the middle top second dielectric layer 305, the middle dielectric layer 308, the middle bottom second dielectric layer 315, the middle bottom first dielectric layer 311, the lower first dielectric layer 402, the bottom top dielectric layer 501, and the bottom dielectric layer 505 adopt silicon dioxide or silicon nitride materials.
According to the three-dimensional coupler based on the through silicon via, provided by the embodiment of the invention, through adopting a through silicon via three-dimensional integration technology and multiple branches, the length of an interconnection line and the area of a chip are effectively reduced, the data transmission bandwidth and the integration level are improved, and the purposes of simultaneously improving the performance of an integrated circuit, reducing the power consumption and reducing the weight and the volume are realized.
The embodiment of the invention provides a preparation method of a three-dimensional coupler based on a through silicon via, which comprises the following steps:
step1, etching an annular blind groove on the lower silicon substrate by using a reactive ion etching technology;
step2, preparing a lower first dielectric layer on the inner surface of the annular blind groove by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
step3, preparing a lower shielding layer on the surface of the lower first dielectric layer by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the lower shielding layer;
step4, etching a cylindrical blind hole in the center of the silicon substrate on the inner side of the lower shielding layer by using a reactive ion etching technology;
step5, preparing a dielectric layer on the inner surface of the cylindrical blind hole by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
step6, preparing a lower signal interconnection column on the surface of the dielectric layer by electrochemical deposition or chemical vapor deposition, and carrying out chemical mechanical polishing on the lower signal interconnection column;
step7, etching the lower first dielectric layer, the lower silicon substrate and the dielectric layer to form an annular blind groove in the area between the lower signal interconnection column and the lower shielding layer by using a reactive ion etching technology;
step8, preparing a lower layer second dielectric layer on the inner surface of the annular blind groove through a vacuum-assisted spin coating process and carrying out chemical mechanical polishing on the lower layer second dielectric layer;
step9, preparing a bottom layer top dielectric layer on the chemical mechanical polishing surface by a chemical vapor deposition method;
step10, etching an annular blind groove and a cylindrical blind hole on the bottom layer top dielectric layer by using a reactive ion etching technology at the same time until the lower shielding layer and the lower signal interconnection column are completely exposed;
step11, preparing a bottom layer top shielding layer and a bottom layer top signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole through an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the bottom layer top shielding layer and the bottom layer top signal interconnection column;
step12, preparing a bottom top grounding layer containing a through hole on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
step13, preparing a bottom dielectric layer on the surface of the bottom grounding layer by using a plasma enhanced chemical vapor deposition or a sub-atmospheric pressure chemical vapor deposition method;
step14, etching a cylindrical blind hole on the surface of the bottom dielectric layer of the bottom layer by using a reactive ion etching technology until the bottom layer top grounding layer and the bottom layer top signal interconnection column are completely exposed;
step15, preparing a bottom layer grounding column and a bottom layer bottom signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the bottom layer grounding column and the bottom layer bottom signal interconnection column;
step16, preparing a bottom layer bottom signal wire and a bottom layer bottom grounding layer on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
step17, turning the silicon substrate over, and thinning the silicon substrate through coarse grinding and fine grinding on the back surface of the silicon substrate until the lower shielding layer and the lower signal interconnection column are exposed;
step18, removing a damage layer on the surface layer on the thinned surface of the back surface of the silicon substrate through dry etching or wet etching;
step19, preparing a first dielectric layer at the bottom of the middle layer on the surface of the silicon substrate with the surface damage layer removed by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
step20, etching an annular blind groove and a cylindrical blind hole on the surface of the first dielectric layer at the bottom of the middle layer by using a reactive ion etching technology at the same time until the lower shielding layer and the lower signal interconnection column are completely exposed;
step21, preparing an intermediate layer bottom shielding layer and an intermediate layer bottom first signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole through an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer bottom shielding layer and the intermediate layer bottom first signal interconnection column;
step22, preparing an intermediate bottom grounding layer containing a through hole on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
step23, preparing a second medium layer at the bottom of the middle layer on the surface of the grounding layer at the bottom of the middle layer by a plasma enhanced chemical vapor deposition or a sub-atmospheric pressure chemical vapor deposition method;
step24, etching a cylindrical blind hole on the surface of the second dielectric layer at the bottom of the middle layer by using a reactive ion etching technology until the grounding layer at the bottom of the middle layer and the first signal interconnection column at the bottom of the middle layer are completely exposed;
step25, preparing an intermediate layer bottom grounding column and an intermediate layer bottom second signal interconnection column on the inner surface of the cylindrical blind hole by electrochemical deposition or chemical vapor deposition, and carrying out chemical mechanical polishing on the intermediate layer bottom grounding column and the intermediate layer bottom second signal interconnection column;
step26, preparing a middle medium layer of the middle layer on the chemical mechanical polishing surface by a plasma enhanced chemical vapor deposition or a sub-atmospheric pressure chemical vapor deposition method;
step27, etching cylindrical blind holes and rectangular blind grooves on the surface of the middle medium layer of the middle layer by using a reactive ion etching technology until the grounding column at the bottom of the middle layer and the second signal interconnection column at the bottom of the middle layer are completely exposed;
step28, preparing an intermediate layer middle grounding column and an intermediate layer signal interconnection line on the inner surfaces of the cylindrical blind hole and the rectangular blind groove by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer middle grounding column and the intermediate layer signal interconnection line to form a first chemical mechanical polishing surface;
step29, etching an annular blind groove on the upper silicon substrate by using a reactive ion etching technology;
step30, preparing an upper first dielectric layer on the inner surface of the annular blind groove by using a plasma enhanced chemical vapor deposition or a sub-atmospheric pressure chemical vapor deposition method;
step31, preparing an upper shielding layer on the surface of the upper first dielectric layer by electrochemical deposition or chemical vapor deposition and carrying out chemical mechanical polishing on the upper shielding layer;
step32, etching a cylindrical blind hole in the center of the silicon substrate on the inner side of the upper shielding layer by using a reactive ion etching technology;
step33, preparing a dielectric layer on the inner surface of the cylindrical blind hole by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
step34, preparing an upper signal interconnection column on the surface of the dielectric layer by electrochemical deposition or chemical vapor deposition and carrying out chemical mechanical polishing on the upper signal interconnection column;
step35, etching the upper first dielectric layer, the upper silicon substrate and the dielectric layer to form an annular blind groove in the area between the upper signal interconnection column and the upper shielding layer by using a reactive ion etching technology;
step36, preparing an upper second dielectric layer on the inner surface of the annular blind groove through a vacuum-assisted spin coating process and carrying out chemical mechanical polishing on the upper second dielectric layer;
step37, preparing a top-layer bottom dielectric layer on the chemical mechanical polishing surface through chemical vapor deposition;
step38, etching an annular blind groove and a cylindrical blind hole on the top-layer bottom dielectric layer by using a reactive ion etching technology at the same time until the upper-layer shielding layer and the upper-layer signal interconnection column are completely exposed;
step39, preparing a top layer bottom shielding layer and a top layer bottom signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole through an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the top layer bottom shielding layer and the top layer bottom signal interconnection column;
step40, preparing a top bottom grounding layer containing a through hole on the chemical mechanical polishing surface by electrochemical deposition or chemical vapor deposition;
step41, preparing a top dielectric layer on the surface of the bottom grounding layer of the top layer by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
step42, etching a cylindrical blind hole on the surface of the top dielectric layer of the top layer by using a reactive ion etching technology until the top bottom grounding layer and the top bottom signal interconnection column are completely exposed;
step43, preparing a top layer grounding column and a top layer top signal interconnection column on the inner surface of the cylindrical blind hole through an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the top layer grounding column and the top layer top signal interconnection column;
step44, preparing a top signal line and a top grounding layer on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
step45, turning the silicon substrate over, and thinning the silicon substrate through coarse grinding and fine grinding on the back surface of the silicon substrate until the upper shielding layer and the upper signal interconnection column are exposed;
step46, removing a damage layer on the surface layer on the thinned surface of the back surface of the silicon substrate through dry etching or wet etching;
step47, preparing a first dielectric layer on the top of the middle layer on the surface of the silicon substrate with the surface damage layer removed by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
step48, etching an annular blind groove and a cylindrical blind hole on the first dielectric layer on the top of the middle layer by using a reactive ion etching technology at the same time until the upper shielding layer and the upper signal interconnection column are completely exposed;
step49, preparing an intermediate layer top shielding layer and an intermediate layer top first signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole through an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer top shielding layer and the intermediate layer top first signal interconnection column;
step50, preparing an intermediate top grounding layer containing a through hole on the chemical mechanical polishing surface by electrochemical deposition or chemical vapor deposition;
step51, preparing a second dielectric layer on the top of the middle layer on the surface of the grounding layer on the top of the middle layer by using a plasma enhanced chemical vapor deposition or a sub-atmospheric pressure chemical vapor deposition method;
step52, etching a cylindrical blind hole on the surface of the second dielectric layer on the top of the middle layer by using a reactive ion etching technology until the grounding layer on the top of the middle layer and the first signal interconnection column on the top of the middle layer are completely exposed;
step53, preparing an intermediate layer top grounding column and an intermediate layer top second signal interconnection column on the inner surface of the cylindrical blind hole through an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer top grounding column and the intermediate layer top second signal interconnection column to form a second chemical mechanical polishing surface;
and Step54, bonding the first chemical mechanical polishing surface and the second chemical mechanical polishing surface in a face-to-face mode through a dielectric bonding method and a metal bonding method.
According to the through-silicon-via three-dimensional coupler and the preparation method provided by the embodiment of the invention, by adopting a reactive ion corrosion technology, electrochemical deposition, plasma enhanced chemical vapor deposition and a chemical vapor deposition method, the length of an interconnection line and the area of a chip are effectively reduced, the data transmission bandwidth and the integration level are improved, and the purposes of simultaneously improving the performance of an integrated circuit, reducing the power consumption and reducing the weight and the volume are realized.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
It should be noted that the above-mentioned embodiments do not limit the present invention in any way, and all technical solutions obtained by using equivalent alternatives or equivalent variations fall within the protection scope of the present invention.

Claims (8)

1. A through-silicon-via based three-dimensional coupler, comprising:
top-layer top ground plane, top-layer top signal line, top-layer top dielectric layer, top-layer ground column, top-layer top signal interconnection column, top-layer bottom ground plane, top-layer bottom dielectric layer, top-layer bottom signal interconnection column, top-layer bottom shielding layer, upper silicon substrate, upper first dielectric layer, upper shielding layer, upper second dielectric layer, upper signal interconnection column, middle-layer top first dielectric layer, middle-layer top shielding layer, middle-layer top first signal interconnection column, middle-layer top ground plane, middle-layer top second dielectric layer, middle-layer top second signal interconnection column, middle-layer top ground column, middle-layer middle dielectric layer, middle-layer signal interconnection line, middle-layer bottom ground column, middle-layer bottom second signal interconnection column, middle-layer bottom second dielectric layer, middle-layer bottom ground plane, middle-layer bottom first dielectric layer bottom, The device comprises a middle layer bottom shielding layer, a middle layer bottom first signal interconnection column, a lower layer silicon substrate, a lower layer first dielectric layer, a lower layer shielding layer, a lower layer second dielectric layer, a lower layer signal interconnection column, a bottom layer top dielectric layer, a bottom layer top shielding layer, a bottom layer top signal interconnection column, a bottom layer top grounding layer, a bottom layer bottom dielectric layer, a bottom layer grounding column, a bottom layer bottom signal interconnection column, a bottom layer bottom grounding layer and a bottom layer bottom signal line;
the three-dimensional coupler is sequentially provided with a top-layer top grounding layer, a top-layer top dielectric layer, a top-layer bottom grounding layer, a top-layer bottom dielectric layer, an upper-layer silicon substrate, a middle-layer top first dielectric layer, a middle-layer top grounding layer, a middle-layer top second dielectric layer, a middle-layer middle dielectric layer, a middle-layer bottom second dielectric layer, a middle-layer bottom grounding layer, a middle-layer bottom first dielectric layer, a lower-layer silicon substrate, a bottom-layer top dielectric layer, a bottom-layer top grounding layer, a bottom-layer bottom dielectric layer;
the top signal line of the top layer comprises six branches which are symmetrical front to back and left to right, and the distance between the top signal line of the top layer and the ground layer of the top layer is equal everywhere;
the top-layer top dielectric layer is provided with four top-layer grounding columns which are symmetrical front and back and left and right and two top-layer top signal interconnection columns which are symmetrical left and right;
the ground layer at the bottom of the top layer is provided with two through holes which are bilaterally symmetrical, and a top-layer top dielectric layer and a top-layer top signal interconnection column pass through the through holes;
the top layer bottom medium layer is provided with two top layer bottom shielding layers which are bilaterally symmetrical and distributed in an annular through groove, and a top layer bottom signal interconnection column is arranged on the inner side of each top layer bottom shielding layer;
the upper silicon substrate is provided with two upper shielding layers which are bilaterally symmetrical and distributed in an annular through groove, the inner side of each upper shielding layer is provided with an upper signal interconnection column, an upper first dielectric layer is arranged between the upper shielding layer and the upper silicon substrate, and an upper second dielectric layer is arranged between the upper shielding layer and the upper signal interconnection column;
the first medium layer at the top of the middle layer is provided with two middle layer top shielding layers which are bilaterally symmetrical and distributed in an annular through groove, and a first signal interconnection column at the top of the middle layer is arranged on the inner side of each middle layer top shielding layer;
the grounding layer at the top of the middle layer is provided with two through holes which are bilaterally symmetrical, and a second dielectric layer at the top of the middle layer and a second signal interconnection column at the top of the middle layer pass through the through holes;
the second medium layer on the top of the middle layer is provided with four middle layer top grounding columns which are symmetrical front and back and left and right and two middle layer top second signal interconnection columns which are symmetrical left and right;
the middle medium layer of the middle layer is provided with four middle ground posts which are symmetrical front and back and left and right and two middle signal interconnection wires which are symmetrical left and right;
the second medium layer at the bottom of the middle layer is provided with four middle layer bottom grounding columns which are symmetrical front and back and left and right and two middle layer bottom second signal interconnection columns which are symmetrical left and right;
the grounding layer at the bottom of the middle layer is provided with two through holes which are bilaterally symmetrical, and a second dielectric layer at the bottom of the middle layer and a second signal interconnection column at the bottom of the middle layer pass through the through holes;
the first medium layer at the bottom of the middle layer is provided with two middle layer bottom shielding layers which are bilaterally symmetrical and distributed in an annular through groove, and a first signal interconnection column at the bottom of the middle layer is arranged on the inner side of each middle layer bottom shielding layer;
the lower silicon substrate is provided with two lower shielding layers which are bilaterally symmetrical and distributed in an annular through groove, the inner side of each lower shielding layer is provided with a lower signal interconnection column, a lower first dielectric layer is arranged between the lower shielding layer and the lower silicon substrate, and a lower second dielectric layer is arranged between the lower shielding layer and the lower signal interconnection column;
the bottom layer top dielectric layer is provided with two bottom layer top shielding layers which are bilaterally symmetrical and distributed in an annular through groove, and a bottom layer top signal interconnection column is arranged on the inner side of each bottom layer top shielding layer;
the ground layer at the top of the bottom layer is provided with two through holes which are bilaterally symmetrical, and a bottom dielectric layer at the bottom of the bottom layer and a signal interconnection column at the bottom of the bottom layer pass through the through holes;
the bottom medium layer is provided with four bottom grounding posts which are symmetrical front and back and left and right and two bottom signal interconnection posts which are symmetrical left and right;
the bottom signal line comprises six branches which are symmetrical front and back and left and right, and the distance between the bottom signal line and the bottom grounding layer is equal everywhere;
the top-layer top signal line, the top-layer top signal interconnection column, the top-layer bottom signal interconnection column, the upper-layer signal interconnection column, the middle-layer top first signal interconnection column, the middle-layer top second signal interconnection column, the middle-layer signal interconnection line, the middle-layer bottom second signal interconnection column, the middle-layer bottom first signal interconnection column, the lower-layer signal interconnection column, the bottom-layer top signal interconnection column, the bottom-layer bottom signal interconnection column, and the bottom-layer bottom signal line are sequentially connected;
the top-layer top ground layer, the top-layer ground post, the top-layer bottom ground layer, the top-layer bottom shielding layer, the upper-layer shielding layer, the middle-layer top ground post, the middle-layer middle ground post, the middle-layer bottom ground layer, the middle-layer bottom shielding layer, the lower-layer shielding layer, the bottom-layer top ground layer, the bottom-layer ground post, and the bottom-layer bottom ground layer are sequentially connected;
the top bottom dielectric layer, the upper first dielectric layer and the middle top first dielectric layer are sequentially connected;
the first medium layer at the bottom of the middle layer, the first medium layer at the lower layer and the medium layer at the top of the bottom layer are sequentially connected.
2. The three-dimensional coupler of claim 1, wherein the top bottom ground plane via, the top bottom shield, the upper shield, the intermediate top ground plane via, the intermediate bottom shield, the lower shield, the bottom top shield, and the bottom top ground plane via are centered on a same line.
3. The three-dimensional coupler of claim 1, wherein the top layer top signal interconnect pillar, the top layer bottom signal interconnect pillar, the upper layer signal interconnect pillar, the middle layer top first signal interconnect pillar, the middle layer top second signal interconnect pillar, the middle layer bottom first signal interconnect pillar, the lower layer signal interconnect pillar, the bottom layer top signal interconnect pillar, and the bottom layer bottom signal interconnect pillar are centered on a same straight line.
4. The three-dimensional coupler of claim 1, wherein the three-dimensional coupler is vertically symmetric about the interlevel dielectric layer.
5. The three-dimensional coupler of claim 1, wherein the top layer top signal lines, the top layer top ground layer, the top layer bottom ground layer, the middle layer top ground layer, the middle layer signal interconnect lines, the middle layer bottom ground layer, the bottom layer top ground layer, the bottom layer bottom signal lines, and the bottom layer bottom ground layer are made of copper material.
6. The three-dimensional coupler of claim 1, wherein the top ground stud, the top signal interconnect stud, the top bottom shield, the upper signal interconnect stud, the middle top shield layer, the middle top first signal interconnect stud, the middle top second signal interconnect stud, the middle top ground stud, the middle ground stud, the middle bottom second signal interconnect stud, the middle bottom first signal interconnect stud, the middle bottom ground stud, the middle bottom shield, the lower signal interconnect stud, the bottom top shield, the bottom top signal interconnect stud, the bottom signal interconnect stud, and the bottom ground stud are made of copper, Tungsten or polysilicon material.
7. The three-dimensional coupler of claim 1, wherein the top dielectric layer, the top bottom dielectric layer, the top first dielectric layer, the middle top second dielectric layer, the middle dielectric layer, the middle bottom second dielectric layer, the middle bottom first dielectric layer, the bottom top dielectric layer, and the bottom dielectric layer are made of silicon dioxide or silicon nitride.
8. The method for preparing the through-silicon-via-based three-dimensional coupler according to claim 1, comprising the steps of:
(1) etching an annular blind groove on the lower silicon substrate by using a reactive ion etching technology;
(2) preparing a lower first dielectric layer on the inner surface of the annular blind groove by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
(3) preparing a lower shielding layer on the surface of the lower first dielectric layer by an electrochemical deposition or chemical vapor deposition method and carrying out chemical mechanical polishing on the lower shielding layer;
(4) etching a cylindrical blind hole in the center of the silicon substrate on the inner side of the lower shielding layer by using a reactive ion etching technology;
(5) preparing a dielectric layer on the inner surface of the cylindrical blind hole by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
(6) preparing a lower signal interconnection column on the surface of the dielectric layer by electrochemical deposition or chemical vapor deposition and carrying out chemical mechanical polishing on the lower signal interconnection column;
(7) etching the lower first dielectric layer, the lower silicon substrate and the dielectric layer by using a reactive ion etching technology to form an annular blind groove in a region between the lower signal interconnection column and the lower shielding layer;
(8) preparing a lower second dielectric layer on the inner surface of the annular blind groove through a vacuum-assisted spin coating process and carrying out chemical mechanical polishing on the lower second dielectric layer;
(9) preparing a bottom layer top dielectric layer on the chemical mechanical polishing surface by a chemical vapor deposition method;
(10) etching an annular blind groove and a cylindrical blind hole on the bottom layer top dielectric layer by using a reactive ion etching technology until the lower shielding layer and the lower signal interconnection column are completely exposed;
(11) preparing a bottom layer top shielding layer and a bottom layer top signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the bottom layer top shielding layer and the bottom layer top signal interconnection column;
(12) preparing a bottom layer top grounding layer containing a through hole on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
(13) preparing a bottom dielectric layer on the surface of the grounding layer on the top of the bottom layer by using a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(14) etching a cylindrical blind hole on the surface of the bottom dielectric layer by using a reactive ion etching technology until the bottom top grounding layer and the bottom top signal interconnection column are completely exposed;
(15) preparing a bottom layer grounding column and a bottom layer bottom signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the bottom layer grounding column and the bottom layer bottom signal interconnection column;
(16) preparing a bottom signal line and a bottom grounding layer on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
(17) turning over the silicon substrate, and thinning the silicon substrate through rough grinding and fine grinding on the back surface of the silicon substrate until the lower shielding layer and the lower signal interconnection column are exposed;
(18) removing a damaged layer on the surface layer on the thinned surface of the back surface of the silicon substrate by dry etching or wet etching;
(19) preparing a first medium layer at the bottom of the middle layer on the surface of the silicon substrate with the damaged layer of the surface layer removed by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(20) etching an annular blind groove and a cylindrical blind hole on the surface of the first dielectric layer at the bottom of the middle layer by using a reactive ion corrosion technology at the same time until the lower shielding layer and the lower signal interconnection column are completely exposed;
(21) preparing an intermediate layer bottom shielding layer and an intermediate layer bottom first signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer bottom shielding layer and the intermediate layer bottom first signal interconnection column;
(22) preparing a middle-layer bottom grounding layer containing a through hole on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
(23) preparing a second medium layer at the bottom of the middle layer on the surface of the grounding layer at the bottom of the middle layer by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(24) etching a cylindrical blind hole on the surface of the second dielectric layer at the bottom of the middle layer by using a reactive ion etching technology until the grounding layer at the bottom of the middle layer and the first signal interconnection column at the bottom of the middle layer are completely exposed;
(25) preparing an intermediate layer bottom grounding column and an intermediate layer bottom second signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method and carrying out chemical mechanical polishing on the intermediate layer bottom grounding column and the intermediate layer bottom second signal interconnection column;
(26) preparing a middle medium layer on the chemical mechanical polishing surface by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(27) etching a cylindrical blind hole and a rectangular blind groove on the surface of the medium layer in the middle of the middle layer by using a reactive ion etching technology until the grounding column at the bottom of the middle layer and the second signal interconnection column at the bottom of the middle layer are completely exposed;
(28) preparing a middle grounding column and a middle signal interconnection line of the middle layer on the inner surfaces of the cylindrical blind hole and the rectangular blind groove by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the middle grounding column and the middle signal interconnection line of the middle layer to form a first chemical mechanical polishing surface;
(29) etching an annular blind groove on the upper silicon substrate by using a reactive ion etching technology;
(30) preparing an upper first dielectric layer on the inner surface of the annular blind groove by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
(31) preparing an upper shielding layer on the surface of the upper first dielectric layer by electrochemical deposition or chemical vapor deposition and carrying out chemical mechanical polishing on the upper shielding layer;
(32) etching a cylindrical blind hole in the center of the silicon substrate on the inner side of the upper shielding layer by using a reactive ion etching technology;
(33) preparing a dielectric layer on the inner surface of the cylindrical blind hole by plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
(34) preparing an upper signal interconnection column on the surface of the dielectric layer by electrochemical deposition or chemical vapor deposition and carrying out chemical mechanical polishing on the upper signal interconnection column;
(35) etching off an upper first dielectric layer, an upper silicon substrate and the dielectric layer by using a reactive ion etching technology in a region between the upper signal interconnection column and the upper shielding layer to form an annular blind groove;
(36) preparing an upper second dielectric layer on the inner surface of the annular blind groove by a vacuum-assisted spin coating process and carrying out chemical mechanical polishing on the upper second dielectric layer;
(37) preparing a top bottom dielectric layer on the chemically-mechanically polished surface by chemical vapor deposition;
(38) etching an annular blind groove and a cylindrical blind hole on the top bottom dielectric layer by utilizing a reactive ion etching technology until the upper shielding layer and the upper signal interconnection column are completely exposed;
(39) preparing a top bottom shielding layer and a top bottom signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the top bottom shielding layer and the top bottom signal interconnection column;
(40) preparing a top bottom grounding layer containing a through hole on the chemical mechanical polishing surface by electrochemical deposition or chemical vapor deposition;
(41) preparing a top dielectric layer on the surface of the ground layer at the bottom of the top layer through plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition;
(42) etching a cylindrical blind hole on the surface of the top dielectric layer by using a reactive ion etching technology until the top bottom grounding layer and the top bottom signal interconnection column are completely exposed;
(43) preparing a top layer grounding column and a top layer top signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the top layer grounding column and the top layer top signal interconnection column;
(44) preparing a top signal line and a top ground layer on the chemical mechanical polishing surface by electrochemical deposition or chemical vapor deposition;
(45) turning over the silicon substrate, and thinning the silicon substrate through rough grinding and fine grinding on the back surface of the silicon substrate until the upper shielding layer and the upper signal interconnection column are exposed;
(46) removing a damaged layer on the surface layer on the thinned surface of the back surface of the silicon substrate by dry etching or wet etching;
(47) preparing a first dielectric layer on the top of the middle layer on the surface of the silicon substrate with the damaged layer of the surface layer removed by a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(48) etching an annular blind groove and a cylindrical blind hole on the first medium layer on the top of the middle layer by using a reactive ion corrosion technology until the upper shielding layer and the upper signal interconnection column are completely exposed;
(49) preparing an intermediate layer top shielding layer and an intermediate layer top first signal interconnection column on the inner surfaces of the annular blind groove and the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer top shielding layer and the intermediate layer top first signal interconnection column;
(50) preparing a middle layer top grounding layer containing a through hole on the chemical mechanical polishing surface by an electrochemical deposition or chemical vapor deposition method;
(51) preparing a second dielectric layer on the top of the middle layer on the surface of the grounding layer on the top of the middle layer by using a plasma enhanced chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition method;
(52) etching a cylindrical blind hole on the surface of the second dielectric layer on the top of the middle layer by using a reactive ion etching technology until the grounding layer on the top of the middle layer and the first signal interconnection column on the top of the middle layer are completely exposed;
(53) preparing an intermediate layer top grounding column and an intermediate layer top second signal interconnection column on the inner surface of the cylindrical blind hole by an electrochemical deposition or chemical vapor deposition method, and carrying out chemical mechanical polishing on the intermediate layer top grounding column and the intermediate layer top second signal interconnection column to form a second chemical mechanical polishing surface;
(54) and bonding the first chemical mechanical polishing surface and the second chemical mechanical polishing surface in a face-to-face mode through a dielectric bonding method and a metal bonding method.
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