CN109542801A - Write operation configuration method, storage control and storage equipment based on QLC nand flash memory - Google Patents
Write operation configuration method, storage control and storage equipment based on QLC nand flash memory Download PDFInfo
- Publication number
- CN109542801A CN109542801A CN201811301413.8A CN201811301413A CN109542801A CN 109542801 A CN109542801 A CN 109542801A CN 201811301413 A CN201811301413 A CN 201811301413A CN 109542801 A CN109542801 A CN 109542801A
- Authority
- CN
- China
- Prior art keywords
- data
- page
- bit
- write operation
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0669—Configuration or reconfiguration with decentralised address assignment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
Abstract
Write operation configuration method based on QLC nand flash memory, comprising steps of 16 voltage ranges of QLC NAND storage unit are characterized using 4 bits, each bit is characterized as a page address, and making QLC NAND tool, there are four page address；Binary coding mapping is carried out to voltage range each in 16 voltage ranges using coding rule, according to binary coding mapping relations by promoting storage voltage to specific voltage range, a variety of different QLC NAND write operations mapped based on four page address are realized；A variety of QLC NAND write operations are configured, matched QLC NAND write operation is selected according to different data storage requirements.The present invention is according to the characteristics of storage control and QLC nand flash memory write operation characteristic, a kind of method that can effectively improve the service performance of QLC NAND chip in storage equipment by configuring different write operation modes in storage control is provided, and then realizes the storage equipment of optimum data write performance.
Description
Technical field
The present invention relates to technical field of memory, and in particular to write operation configuration method, storage based on QLC nand flash memory
Controller and storage equipment.
Background technique
As 3D QLC flash memory technology develops, the 3D structure of multiple-layer stacked is become not with the advantage of its high capacity, low cost
Carry out the hot spot of application and research.QLC NAND refers to that every storage unit can store the nand flash memory of 4bit data, and 3D design refers to
The chip design of three-dimensional stacked multilayer is realized in silicon wafer vertical direction.However, 16 of the characterize data value due to QLC NAND
A voltage range span reduces, and the gap of each data storage voltage range reduces and the manufacturing process complexity of QLC increases etc.
Reason makes up to certain storage voltage after four data bit that each QLC storage unit is stored need multiple write operation
Domain, so that practical four bit data could be characterized, along with may be because of multiple write operation between consecutive storage unit when it is mutual
Interference, so that the data identification complexity that every QLC storage unit is stored increases, the serious QLC NAND chip that affects is being deposited
Store up the use in equipment.
Usual way is to try to read data error correction algorithm using more complicated ECC, related in optimization firmware (Firmware)
The algorithm etc. of data is read, guarantee is written to the service performance of the correctness of the data of QLC flash memory after reading with storage equipment.
Summary of the invention
In view of the deficiencies of the prior art or Improvement requirement, the present invention store the storage equipment of flash memory to use QLC NAND
(such as SSD hard disk) design proposes a variety of different write operations of configuration, it is intended that passing through the storage control in storage equipment
Configuration setting, used 3D QLC NAND is subjected to attribute configuration and realizes different write operations, to change QLC
The write operation number and order of nand flash memory improve the performance of the storing data of QLC NAND chip.
According in a first aspect, write operation configuration, the application provide one kind in the storage control in storage equipment to realize
Write operation configuration method based on QLC nand flash memory, comprising steps of
16 voltage ranges of the QLC NAND storage unit are characterized using 4 bits, each bit characterization
For a page address, making the QLC NAND tool, there are four page address；
Binary coding mapping is carried out to voltage range each in 16 voltage ranges using coding rule, according to binary system
Coding mapping relationship is realized more based on mapping four page address by promoting storage voltage to specific voltage range
The different QLC NAND write operation of kind；
A variety of QLC NAND write operations are configured, matched QLC can be selected according to different data storage requirements
NAND write operation realizes that the write-in to data in QLC NAND not same page stores.
In a kind of embodiment, four page address of the QLC NAND are respectively adopted page 0, page 1, page 2 and page 3 and indicate, institute
Bit 0, bit 1, bit 2 and bit 3, which is respectively adopted, in 4 bit datas for stating the single storage unit storage of QLC NAND indicates,
When the QLC NAND write operation carries out writing data storage, storage voltage is promoted to described 16 to QLC NAND storage unit
One of voltage range completes the storage of 4 bit datas.
In a kind of embodiment, the QLC NAND write operation includes following eight seed type:
Write operation one: 0 data of bit are first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit, then
2 data of bit are written to page 2,3 data of bit are finally written to page 3；
Write operation two: 0 data of bit are first written to 0 address of page in data writing operation, then simultaneously by 1 data of bit and bit 2
Data are written to page 2 and page 3, and 3 data of bit are finally written to page 3；
Write operation three: 0 data of bit are first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit, then
2 data of bit and 3 data of bit are written to page 2 and page 3 simultaneously；
Write operation four: 0 data of bit are first written to 0 address of page in data writing operation, then by 1 data of bit, 2 data of bit and
3 data of bit are written to page 1, page 2 and page 3 simultaneously；
Write operation five: first page 0 and page 1 is written simultaneously in 0 data of bit and 1 data of bit by data writing operation, will then be compared
Special 2 data are written to page 2, and 3 data of bit are finally written to page 3；
Write operation six: first page 0 and page 1 is written simultaneously in 0 data of bit and 1 data of bit by data writing operation, will then be compared
Special 2 data and 3 data of bit are written to page 2 and page 3 simultaneously；
Write operation seven: first page 0, page 1 is written in 0 data of bit, 1 data of bit and 2 data of bit by data writing operation simultaneously
With page 2,3 data of bit are then written to page 3；
Write operation eight: 0 data of bit, 1 data of bit, 2 data of bit and 3 data of bit are written data writing operation simultaneously
Page 0, page 1, page 2 and page 3.
It further include the QLC NAND write operation of each type being arranged corresponding write operation configuration in a kind of embodiment
Position makes firmware input different write operation configuration bits to call corresponding QLC NAND write operation, to realize according to different demands
Write-in storage to data in QLC NAND not same page.
According to second aspect, the application provides a kind of storage control based on QLC nand flash memory, the QLC NAND
16 voltage ranges of storage unit are characterized using 4 bits, each bit is characterized as a page address, the QLC
NAND tool is there are four page address, and for four page address configuration, there are many different QLC NAND in the storage control
Write operation, and a variety of QLC NAND write operation flexibly configurables, make the storage control according to different data storage requirements
Matched QLC NAND write operation is selected, to realize that the no write de-lay to data in QLC NAND not same page stores.
In a kind of embodiment, binary coding mapping ruler corresponding to each voltage range in 16 voltage ranges
Only has bit difference for the binary coding in neighboring voltage section, to reduce corrupt data possibility.
In a kind of embodiment, according to the coding mapping rule by the data of the need storage in the multiple pages of Rapid Combination,
To characterize the voltage of 16 voltage ranges, a variety of QLC NAND write operations are obtained.
In a kind of embodiment, four page address of the QLC NAND are respectively set to page 0, page 1, page 2 and page 3, described
Bit 0, bit 1, bit 2 and bit 3, which is respectively adopted, in the 4bit data of the single storage unit storage of QLC NAND indicates, described
When QLC NAND write operation carries out writing data storage, storage voltage is promoted to 16 voltages to QLC NAND storage unit
The storage of 4bit data is completed in one of section.
In a kind of embodiment, the write operation of the QLC includes following eight seed type:
Write operation one: 0 data of bit can be first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit,
Then 2 data of bit are written to page 2,3 data of bit is finally written to page 3；
Write operation two: 0 data of bit can be first written to 0 address of page in data writing operation, then simultaneously by 1 data of bit and ratio
Special 2 data are written to page 2 and page 3, and 3 data of bit are finally written to page 3；
Write operation three: 0 data of bit can be first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit,
Then 2 data of bit and 3 data of bit are written to page 2 and page 3 simultaneously；
Write operation four: 0 data of bit can be first written to 0 address of page in data writing operation, then 1 data of bit, bit 2 are counted
It is written to page 1, page 2 and page 3 simultaneously according to 3 data of bit；
Write operation five: first page 0 and page 1 can be written simultaneously in 0 data of bit and 1 data of bit by data writing operation, then
2 data of bit are written to page 2,3 data of bit are finally written to page 3；
Write operation six: first page 0 and page 1 can be written simultaneously in 0 data of bit and 1 data of bit by data writing operation, then
2 data of bit and 3 data of bit are written to page 2 and page 3 simultaneously；
Write operation seven: data writing operation can first by 0 data of bit, 1 data of bit and 2 data of bit simultaneously be written page 0,
3 data of bit are then written to page 3 by page 1 and page 2；
Write operation eight: 0 data of bit, 1 data of bit, 2 data of bit and 3 data of bit are written data writing operation simultaneously
Page 0, page 1, page 2 and page 3.
In a kind of embodiment, design has configurable TRIM register, the TRIM register in the storage control
In at least one of described QLC NAND write operation configured with eight seed types write operation.
In a kind of embodiment, configured with described in eight seed types of the write operation one to write operation eight in the TRIM register
QLC NAND write operation, and a variety of QLC NAND write operations are correspondingly configured with different write operation configuration bits, make described deposit
The firmware for storing up controller inputs different write operation configuration bits by different demands and calls corresponding QLC NAND write operation, to realize
Write-in storage to data in QLC NAND not same page.
In a kind of embodiment, the write operation configuration bit of the TRIM register is characterized using 3bit.
According to the third aspect, the application also provides a kind of storage equipment, including memory device and above-mentioned storage control,
It may be configured with a variety of different QLC NAND write operations in the storage control, make the storage control according to different numbers
Matched QLC NAND write operation is selected to carry out different QLC NAND write operations to the memory device according to storage demand.
According to above-described embodiment write operation configuration method, for QLC NAND type flash chip the characteristics of, depositing
It stores up configuration in controller and realizes a variety of write operations；The data writing operation of storage equipment is realized using different configurations, thus solid
It is flexibly used in part design.The present invention according to the characteristics of storage control and the research of QLC nand flash memory write operation characteristic and
Engineering demand, providing one kind can effectively be mentioned by configuring different write operation modes in storage control
The method of the service performance of QLC NAND chip in height storage equipment, and then realize and meet the most suitable of the storage system demand and write
Efficiency, the storage equipment of optimum data write performance.By realizing that be can configure is directed to QLC in storage equipment in the present invention
The different write operations of NAND, can be according to the write-in functions of the QLC NAND different information realization data dispatched from the factory, so as to have
Improve QLC NAND chip storage performance in effect ground.
Detailed description of the invention
Fig. 1 is QLC NAND write operation configuration flow figure；
Fig. 2 is QLC NAND voltage distribution graph；
Fig. 3 is the different write operation schematic diagrames of QLC NAND；
Wherein, Fig. 3 (a) illustrates write operation one: being sequentially written in data to page0-1-2-3；
Fig. 3 (b) illustrates write operation two: being sequentially written in data to page0-1-2/3；
Fig. 3 (c) illustrates write operation three: being sequentially written in data to page0-1/2-3；
Fig. 3 (d) illustrates write operation four: being sequentially written in data to page0-1/2/3；
Fig. 3 (e) illustrates write operation five: being sequentially written in data to page0/1-2-3；
Fig. 3 (f) illustrates write operation six: being sequentially written in data to page0/1-2/3；
Fig. 3 (g) illustrates write operation seven: being sequentially written in data to page0/1/2-3；
Fig. 3 (h) illustrates write operation eight: while writing data to page0/1/2/3；
Fig. 4 is write operation configuration schematic diagram in the controller of QLC NAND；
Fig. 5 is storage equipment principle block diagram；
Fig. 6 is the application schematic diagram of Fig. 5.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.
Storage equipment based on QLC nand flash memory refers to the storage control that QLC NAND is used by designing, and integrates 3D
QLC NAND chip realizes the read-write of data.To achieve the above object, it is more to propose the configuration realization in storage control for this example
The basic conception of kind write operation.
Embodiment one:
This example provides a kind of write operation configuration method based on QLC nand flash memory, realized in storage control it is a variety of not
Same QLC NAND write operation, flow chart is as shown in Figure 1, specifically comprise the following steps.
S1: 16 voltage ranges of QLC NAND storage unit are characterized using 4 bits, each bit is characterized as
One page address, making QLC NAND tool, there are four page address.
Specifically, for QLC NAND storage unit, since its voltage characteristic co-exists in 16 voltage ranges, QLC NAND
Voltage distribution graph can convert 4 bits (bit) for this 16 voltage ranges to characterize as shown in Fig. 2, therefore, each bit
Position can regard a page address as, then there are 4 page address for QLC NAND cell, can be set to page 0 (page 0), page respectively
1 (page 1), page 2 (page 2) and page 3 (page 3), correspondingly, 4 bits that the single storage unit of QLC NAND stores
Data are respectively adopted bit 0, bit 1, bit 2 and bit 3 and indicate, when QLC NAND write operation carries out writing data storage, to QLC
NAND storage unit promotes storage voltage one of to 16 voltage ranges, completes the storage of 4 bit datas.
The conventional write operation of QLC NAND is only one kind at present, and 0 data of bit first write operation as sequentially: are written to page
0 address, then page 1 is written into 1 data of bit, 2 data of bit are then written to page 2,3 data of bit are finally written to page 3.
The basic conception for a variety of write operations that this example proposes is exactly to break this single write operation sequence, is configured a variety of
QLC NAND write operation improves the storage of QLC NAND chip to change the write operation number and order of QLC nand flash memory
The performance of data, specific operation process are step S2 and step S3.
S2: binary coding mapping is carried out to voltage range each in 16 voltage ranges using coding rule, according to two
By promoting storage voltage to specific voltage range, realization is mapped a variety of scale coding mapping relations based on four page address
Different QLC NAND write operations.
Since each voltage range is characterized using 4bit in 16 voltage ranges, in order to make any two neighboring voltage area
Between binary code there was only that a bit is different, the coding rule of this example is using Gray code rule respectively to 16 voltages
Each voltage range carries out binary coding mapping in section, is arrived according to binary coding mapping relations by promoting storage voltage
A certain specific voltage range in 16 voltage ranges, and then obtain QLC NAND corresponding to the specific voltage range and write behaviour
Make, a variety of different QLC NAND write operations based on the mapping of four page address are realized with this.
Specifically, this example is using Gray code rule by promoting storage voltage a certain specific electricity into 16 voltage ranges
Between pressure area, generated QLC NAND write operation includes following eight seed type:
Write operation one: 0 data of bit are first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit, then
2 data of bit are written to page 2,3 data of bit are finally written to page 3；Shown in the process of write operation one such as Fig. 3 (a).
Write operation two: 0 data of bit are first written to 0 address of page in data writing operation, then simultaneously by 1 data of bit and bit 2
Data are written to page 2 and page 3, and 3 data of bit are finally written to page 3；Shown in the process of write operation two such as Fig. 3 (b).
Write operation three: 0 data of bit are first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit, then
2 data of bit and 3 data of bit are written to page 2 and page 3 simultaneously.
Write operation four: 0 data of bit are first written to 0 address of page in data writing operation, then by 1 data of bit, 2 data of bit and
3 data of bit are written to page 1, page 2 and page 3 simultaneously.
Write operation five: first page 0 and page 1 is written simultaneously in 0 data of bit and 1 data of bit by data writing operation, will then be compared
Special 2 data are written to page 2, and 3 data of bit are finally written to page 3.
Write operation six: first page 0 and page 1 is written simultaneously in 0 data of bit and 1 data of bit by data writing operation, will then be compared
Special 2 data and 3 data of bit are written to page 2 and page 3 simultaneously；Shown in the process of write operation six such as Fig. 3 (f).
Write operation seven: first page 0, page 1 is written in 0 data of bit, 1 data of bit and 2 data of bit by data writing operation simultaneously
With page 2,3 data of bit are then written to page 3；Shown in the process of write operation seven such as Fig. 3 (g).
Write operation eight: 0 data of bit, 1 data of bit, 2 data of bit and 3 data of bit are written data writing operation simultaneously
Page 0, page 1, page 2 and page 3；Shown in the process of write operation eight such as Fig. 3 (h).
S3: configuring a variety of QLC NAND write operations, can be selected according to different data storage requirements matched
QLC NAND write operation realizes that the write-in to data in QLC NAND not same page stores.
Further, in this example, corresponding write operation configuration bit is arranged to the QLC NAND write operation of each type, makes to deposit
The firmware of storage controller inputs different write operation configuration bits according to different data storage requirements and by interface protocol, to adjust
With corresponding QLC NAND write operation, the write-in of data in QLC NAND not same page is stored with realization.Such as, interface protocol can be with
PCIe or SATA or UFS agreement etc., for 8 kinds of different write operations for adapting to above-mentioned QLC NAND, it is corresponding configured with 8 kinds not
With write operation configuration bit, the corresponding 8 kinds of difference write operations for being associated with above-mentioned QLC of this 8 kinds different write operation configuration bits, wherein write
Operative configuration position is characterized using 3 bits (3bits).
This example provides the different write operation configuration methods of QLC nand flash memory, to carry out attribute according to 3D QLC NAND
Configuration is to realize different write operations, to change the write operation number and order of QLC nand flash memory.
Embodiment two:
Based on embodiment one, this example provides a kind of storage control based on QLC nand flash memory, in the storage control
Configured with QLC NAND difference write operation.
16 voltage ranges of QLC NAND storage unit are characterized using 4 bits, each bit is characterized as one
Page address makes page address there are four QLC NAND tools, and four page address configurations are directed in storage control, and there are many different QLC
NAND write operation, and, a variety of QLC NAND write operation flexibly configurables make storage control according to different data storage requirements
Matched QLC NAND write operation is selected, to realize that the no write de-lay to data in QLC NAND not same page stores.
Wherein, binary coding mapping ruler corresponding to each voltage range is neighboring voltage area in 16 voltage ranges
Between binary coding only have a bit difference, with reduce corrupt data may, if Gray code rule, reflected according to coding
Rule is penetrated by the data of the need storage in the multiple pages of Rapid Combination, so that the voltage of 16 voltage ranges of characterization, obtains a variety of
QLC NAND write operation, the QLC NAND write operation for obtaining eight seed types about application Gray code rule please refer to embodiment one
Step S2, does not repeat herein.
Likewise, page 0, page 1, page 2 and page 3, which is respectively adopted, in four page address of QLC NAND indicates, the QLC NAND
The storage of single storage unit 4 bit datas bit 0 is respectively adopted, bit 1, bit 2 and bit 3 indicate, then QLC NAND
When write operation carries out writing data storage, to one of QLC NAND storage unit promotion storage voltage to 16 voltage ranges, 4 are completed
The storage of bit data.
Specifically, design has configurable TRIM register in storage control, eight types are configured in TRIM register
The write operation of at least one of the QLC NAND write operation of type, in this example, configured with write operation one to writing in TRIM register
The QLC NAND write operation of eight seed types of operation eight, and different types of QLC NAND write operation is correspondingly configured with different write
Operative configuration position makes the firmware of storage control input different write according to different data storage requirements and by interface protocol
Corresponding QLC NAND write operation is called in operative configuration position, to realize that the write-in to data in QLC NAND not same page stores.
The TRIM register of this example is built-in with 8 kinds of different write operation configuration bits, this 8 kinds different write operation configuration bits are corresponding to close
Joining 8 kinds of different write operations of above-mentioned QLC NAND, wherein the write operation configuration bit of TRIM register is characterized using 3 bits,
Schematic diagram in relation to the corresponding configuration different Q LC NAND write operations of write operation configuration bit different in TRIM register is as shown in Figure 4.
Configure QLC NAND's by the TRIM register configurable to storage control design, and in TRIM register
Different write operations, to flexibly be used in firmware design.
Based on above-mentioned storage control, this example also provides a kind of storage equipment, the storage equipment include memory device and
Above-mentioned storage control, functional block diagram are write as shown in figure 5, may be configured with a variety of different QLC NAND in storage control
Operation makes storage control select matched QLC NAND write operation to carry out memory device according to different data storage requirements
Different QLC NAND write operations.
It that is to say, store the TRIM register that the storage control in equipment realizes specified write operation in the hardware design
TRIM [2:0], at the same in firmware design (Firmware) 8 according to listed by embodiment 1 in write operation separately design realization pair
The write-in of data does not store algorithm in same page (page), can realize the configurable difference for QLC NAND in storage equipment
Write operation, can be according to the write-in functions of the QLC NAND different information realization data dispatched from the factory, so as to effectively improve QLC
NAND chip storage performance reduces corrupt data rate, improves error correction capability when system application.
The schematic diagram of the storage equipment concrete application of this example is as shown in fig. 6, specifically, host equipment is different according to system
Data storage requirement and interface instruction collection issue instruction to the storage control in storage equipment, to hard in storage control
Part TRIM register carries out set processing.Storage control is right according to current data treatment situation and firmware algorithm for design
Different channels or the configuration of specified nand memory part input different data, select different write operations.
After configured TRIM register value, by nand flash memory associated instruction set and driving to nand memory
Part is advanced actual different data write operation.
The application of write operation is illustrated with different types of storage equipment citing below.
For example, equipment is stored for SSD, and it can be by host side according to PCIe or SATA interface agreement, input setting is write
Operative configuration position is equal to " 101 " into SSD controller, and the value of setting TRIM register is " 101 "；Then according to SSD controller
Middle firmware assignment algorithm and driving, determine the write operation of the nand memory part on certain channel be " first by 0 data of bit and
Page 0 and page 1 is written simultaneously in 1 data of bit, 2 data of bit and 3 data of bit is then written to page 2 and page 3 " simultaneously, at this time
Host side is first successively inputted the data of page0 and page1 by write command requirements, is write the time as defined in one section of waiting and is completed this and write
After operation, be further continued for successively finally waiting one section again by the data of write command requirement input page2 and page3 as defined in when writing
Between after complete the data write-in of 4 page so that SSD controller can easily be realized in each nand memory part it is various
QLC write operation.
For example, equipment is stored for UFS, it can be by host side according to UFS agreement, input setting write operation Configuration Values
" 000 " is into the write operation TRIM register in UFS controller；Then according to firmware assignment algorithm in UFS controller and
Driving is first written the data of page0 by UFS write command from host side, writes the time as defined in one section of waiting and complete this write operation
Afterwards, be further continued for successively by write command requirement input page1 data+wait this write operation complete, data+waiting of page2
The data of the completion of this write operation and page3+this write operation is waited to complete.So that UFS controller can easily be deposited in NAND
Different QLC write operations is realized in memory device.
Use above specific case is illustrated the present invention, the present invention is merely used to help understand, not to limit
The present invention.For those skilled in the art, according to the thought of the present invention, it can also make and several simply push away
It drills, deform or replaces.Such as, storage equipment of the invention and storage control include but is not limited to SSD, and the data such as UFS, eMMC are deposited
Storage device, any type of storage equipment are included in the range of present invention storage equipment.Storage equipment of the present invention
Control is also not necessarily limited to controller, and all to storing, equipment carries out the equipment of operation control or controller belongs to this storage equipment hair
Bright scope.
Claims (13)
1. the write operation configuration method based on QLC nand flash memory, which is characterized in that comprising steps of the QLC NAND is stored
16 voltage ranges of unit are characterized using 4 bits, each bit is characterized as a page address, make the QLC NAND
There are four page address for tool；
Binary coding mapping is carried out to voltage range each in 16 voltage ranges using coding rule, according to binary coding
By promoting storage voltage to specific voltage range, realization is mapped a variety of different mapping relations based on four page address
QLC NAND write operation；
A variety of QLC NAND write operations are configured, matched QLC NAND can be selected according to different data storage requirements
Write operation realizes that the write-in to data in QLC NAND not same page stores.
2. write operation configuration method as described in claim 1, which is characterized in that four page address of the QLC NAND are distinguished
It is indicated using page 0, page 1, page 2 and page 3, ratio is respectively adopted in 4 bit datas of the single storage unit storage of the QLC NAND
Spy 0, bit 1, bit 2 and bit 3 indicate, when the QLC NAND write operation carries out writing data storage, store to QLC NAND
Unit lifting stores voltage to one of 16 voltage ranges, completes the storage of 4 bit datas.
3. write operation configuration method as claimed in claim 2, which is characterized in that the QLC NAND write operation includes following eight
Seed type:
Write operation one: 0 data of bit are first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit, will then compare
Special 2 data are written to page 2, and 3 data of bit are finally written to page 3；
Write operation two: 0 data of bit are first written to 0 address of page in data writing operation, then simultaneously by 2 data of 1 data of bit and bit
It is written to page 2 and page 3,3 data of bit are finally written to page 3；
Write operation three: 0 data of bit are first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit, will then compare
Special 2 data and 3 data of bit are written to page 2 and page 3 simultaneously；
Write operation four: 0 data of bit are first written to 0 address of page in data writing operation, then by 1 data of bit, 2 data of bit and bit
3 data are written to page 1, page 2 and page 3 simultaneously；
Write operation five: first page 0 and page 1 is written simultaneously in 0 data of bit and 1 data of bit by data writing operation, then by the number of bit 2
According to page 2 is written to, 3 data of bit are finally written to page 3；
Write operation six: first page 0 and page 1 is written simultaneously in 0 data of bit and 1 data of bit by data writing operation, then by the number of bit 2
It is written to page 2 and page 3 simultaneously according to 3 data of bit；
Write operation seven: first page 0, page 1 and page is written in 0 data of bit, 1 data of bit and 2 data of bit by data writing operation simultaneously
2,3 data of bit are then written to page 3；
Write operation eight: data writing operation by 0 data of bit, 1 data of bit, 2 data of bit and 3 data of bit simultaneously be written page 0,
Page 1, page 2 and page 3.
4. write operation configuration method as claimed in claim 1 or 3, which is characterized in that further include the QLC to each type
Corresponding write operation configuration bit is arranged in NAND write operation, and firmware is made to input different write operation configuration bits according to different demands to adjust
With corresponding QLC NAND write operation, the write-in of data in QLC NAND not same page is stored with realization.
5. 16 voltage ranges of a kind of storage control based on QLC nand flash memory, the QLC NAND storage unit use
4 bits characterize, each bit is characterized as page address, and there are four page address, feature exists the QLC NAND tool
In, for four page address configuration there are many different QLC NAND write operations in the storage control, and a variety of QLC
NAND write operation flexibly configurable makes the storage control select matched QLC NAND according to different data storage requirements
Write operation, to realize that the no write de-lay to data in QLC NAND not same page stores.
6. storage control as claimed in claim 5, which is characterized in that each voltage range institute in 16 voltage ranges
Corresponding binary coding mapping ruler is that the binary coding in neighboring voltage section only has bit difference, to reduce
Corrupt data possibility.
7. storage control as claimed in claim 6, which is characterized in that pass through Rapid Combination according to the coding mapping rule
The data of need storage in multiple pages obtain a variety of QLC NAND and write to characterize the voltage of 16 voltage ranges
Operation.
8. storage control as claimed in claim 7, which is characterized in that four page address of the QLC NAND are respectively adopted
Page 0, page 1, page 2 and page 3 indicate, 4 bit datas of the single storage unit storage of the QLC NAND be respectively adopted bit 0,
Bit 1, bit 2 and bit 3 indicate, when the QLC NAND write operation carries out writing data storage, to QLC NAND storage unit
Storage voltage is promoted to one of 16 voltage ranges, completes the storage of 4 bit datas.
9. storage control as claimed in claim 8, which is characterized in that the QLC NAND write operation includes following eight type
Type:
Write operation one: 0 data of bit are first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit, will then compare
Special 2 data are written to page 2, and 3 data of bit are finally written to page 3；
Write operation two: 0 data of bit are first written to 0 address of page in data writing operation, then simultaneously by 2 data of 1 data of bit and bit
It is written to page 2 and page 3,3 data of bit are finally written to page 3；
Write operation three: 0 data of bit are first written to 0 address of page in data writing operation, then page 1 is written in 1 data of bit, will then compare
Special 2 data and 3 data of bit are written to page 2 and page 3 simultaneously；
Write operation four: 0 data of bit are first written to 0 address of page in data writing operation, then by 1 data of bit, 2 data of bit and bit
3 data are written to page 1, page 2 and page 3 simultaneously；
Write operation five: first page 0 and page 1 is written simultaneously in 0 data of bit and 1 data of bit by data writing operation, then by the number of bit 2
According to page 2 is written to, 3 data of bit are finally written to page 3；
Write operation six: first page 0 and page 1 is written simultaneously in 0 data of bit and 1 data of bit by data writing operation, then by the number of bit 2
It is written to page 2 and page 3 simultaneously according to 3 data of bit；
Write operation seven: first page 0, page 1 and page is written in 0 data of bit, 1 data of bit and 2 data of bit by data writing operation simultaneously
2,3 data of bit are then written to page 3；
Write operation eight: data writing operation by 0 data of bit, 1 data of bit, 2 data of bit and 3 data of bit simultaneously be written page 0,
Page 1, page 2 and page 3.
10. storage control as claimed in claim 9, which is characterized in that there is configurable design in the storage control
TRIM register, at least one of described QLC NAND write operation in the TRIM register configured with eight seed types are write
Operation.
11. storage control as claimed in claim 10, which is characterized in that be configured with write operation one in the TRIM register
To the QLC NAND write operation of eight seed types of write operation eight, and a variety of QLC NAND write operations are correspondingly configured with not
Same write operation configuration bit makes the firmware of the storage control input different write operation configuration bits by different demands and calls phase
The QLC NAND write operation answered, to realize that the write-in to data in QLC NAND not same page stores.
12. storage control as claimed in claim 11, which is characterized in that the write operation configuration bit of the TRIM register is adopted
It is characterized with 3 bits.
13. a kind of storage equipment, which is characterized in that including memory device and the described in any item storage controls of claim 5-12
Device may be configured with a variety of different QLC NAND write operations in the storage control, make the storage control according to difference
Data storage requirement select matched QLC NAND write operation to carry out different QLC NAND write operations to the memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811301413.8A CN109542801B (en) | 2018-11-02 | 2018-11-02 | Write operation configuration method based on QLC NAND flash memory, memory controller and memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811301413.8A CN109542801B (en) | 2018-11-02 | 2018-11-02 | Write operation configuration method based on QLC NAND flash memory, memory controller and memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109542801A true CN109542801A (en) | 2019-03-29 |
| CN109542801B CN109542801B (en) | 2023-03-14 |
Family
ID=65846299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811301413.8A Active CN109542801B (en) | 2018-11-02 | 2018-11-02 | Write operation configuration method based on QLC NAND flash memory, memory controller and memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109542801B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111708724A (en) * | 2020-05-29 | 2020-09-25 | 苏州浪潮智能科技有限公司 | Method and equipment for allocating resources of PCIe board card |
| CN112486853A (en) * | 2020-12-15 | 2021-03-12 | 长江存储科技有限责任公司 | Page mapping decoding method and system of NAND flash memory, storage medium and terminal |
| CN112802514A (en) * | 2021-01-25 | 2021-05-14 | 长江存储科技有限责任公司 | Operation method and device of flash memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102687125A (en) * | 2010-01-27 | 2012-09-19 | 株式会社东芝 | Memory device and host device |
| US20150006791A1 (en) * | 2013-07-01 | 2015-01-01 | Younggeon Yoo | Storage device and method of writing and reading the same |
| CN105679364A (en) * | 2014-12-08 | 2016-06-15 | 桑迪士克技术有限公司 | Rewritable multibit non-volatile memory with soft decode optimization |
-
2018
- 2018-11-02 CN CN201811301413.8A patent/CN109542801B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102687125A (en) * | 2010-01-27 | 2012-09-19 | 株式会社东芝 | Memory device and host device |
| US20150006791A1 (en) * | 2013-07-01 | 2015-01-01 | Younggeon Yoo | Storage device and method of writing and reading the same |
| CN105679364A (en) * | 2014-12-08 | 2016-06-15 | 桑迪士克技术有限公司 | Rewritable multibit non-volatile memory with soft decode optimization |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111708724A (en) * | 2020-05-29 | 2020-09-25 | 苏州浪潮智能科技有限公司 | Method and equipment for allocating resources of PCIe board card |
| CN112486853A (en) * | 2020-12-15 | 2021-03-12 | 长江存储科技有限责任公司 | Page mapping decoding method and system of NAND flash memory, storage medium and terminal |
| CN112486853B (en) * | 2020-12-15 | 2022-11-01 | 长江存储科技有限责任公司 | Page mapping decoding method and system of NAND flash memory, storage medium and terminal |
| CN112802514A (en) * | 2021-01-25 | 2021-05-14 | 长江存储科技有限责任公司 | Operation method and device of flash memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109542801B (en) | 2023-03-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107967121A (en) | Method for writing data and storage device | |
| CN109542801A (en) | Write operation configuration method, storage control and storage equipment based on QLC nand flash memory | |
| US8825947B1 (en) | System and method for managing data access in non-volatile memory | |
| EP2940691A1 (en) | Storage controller, storage device, storage system and method of operating the storage controller | |
| TWI470641B (en) | Methods and apparatus for interfacing between a flash memory controller and a flash memory array | |
| CN101908368A (en) | Electronic storage device and operation method thereof | |
| US20130060992A1 (en) | Data compression method | |
| US20100250826A1 (en) | Memory systems with a plurality of structures and methods for operating the same | |
| US11210005B2 (en) | Unbalanced plane management method, associated data storage device and controller thereof | |
| US20190332331A1 (en) | Memory management method and storage controller | |
| US9141530B2 (en) | Data writing method, memory controller and memory storage device | |
| TWI571882B (en) | Wear leveling method, memory control circuit unit and memory storage device | |
| US20190304547A1 (en) | Decoding method and storage controller | |
| US20170052704A1 (en) | Memory management method, memory control circuit unit and memory storage device | |
| US11347640B2 (en) | Data storage device and data processing method | |
| CN108733580A (en) | Method for scheduling read commands | |
| CN105279108A (en) | Method for writing data of solid-state drive | |
| JP2016162407A (en) | Control device, control method, and control program | |
| CN112181274B (en) | Large block organization method for improving performance stability of storage device and storage device thereof | |
| CN106354651B (en) | Average wear method, memory control circuit unit and memory storage device | |
| CN204270293U (en) | Hyperchannel Flash controller | |
| CN110364207B (en) | Decoding method and storage controller | |
| CN113096713B (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN107239224B (en) | Data protection method, memory control circuit unit and memory storage device | |
| US20240361934A1 (en) | Data storage device and data processing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 201613 area C13, building 1, 120 Rongjiang Road, Songjiang Industrial Zone, Songjiang District, Shanghai Applicant after: SHANGHAI BAIGONG SEMICONDUCTOR Co.,Ltd. Address before: 201409 room 2170, building 1, 2011 Xinfeng Road, Fengcheng Town, Fengxian District, Shanghai Applicant before: SHANGHAI BAIGONG SEMICONDUCTOR Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |