CN109542801B

CN109542801B - Write operation configuration method based on QLC NAND flash memory, memory controller and memory device

Info

Publication number: CN109542801B
Application number: CN201811301413.8A
Authority: CN
Inventors: 刘世军; 于楠; 陈敬沧; 陈刚
Original assignee: Shanghai Baigong Semiconductor Co ltd
Current assignee: Shanghai Baigong Semiconductor Co ltd
Priority date: 2018-11-02
Filing date: 2018-11-02
Publication date: 2023-03-14
Anticipated expiration: 2038-11-02
Also published as: CN109542801A

Abstract

The write operation configuration method based on the QLC NAND flash memory comprises the following steps: representing 16 voltage intervals of the QLC NAND memory unit by adopting 4 bits, wherein each bit is represented as a page address, so that the QLC NAND has four page addresses; binary coding mapping is carried out on each voltage interval in the 16 voltage intervals by adopting a coding rule, and various different QLC NAND writing operations based on four page address mapping are realized by promoting storage voltage to a specific voltage interval according to the binary coding mapping relation; and configuring various QLC NAND writing operations, and selecting matched QLC NAND writing operations according to different data storage requirements. The invention provides a method which can effectively improve the use performance of a QLC NAND chip in a storage device by configuring different write operation modes in a storage controller according to the characteristics of the storage controller and the write operation characteristics of a QLC NAND flash memory, thereby realizing the storage device with the optimal data write-in performance.

Description

Write operation configuration method based on QLC NAND flash memory, memory controller and memory device

Technical Field

The invention relates to the technical field of storage, in particular to a write operation configuration method based on a QLC NAND flash memory, a storage controller and storage equipment.

Background

With the development of 3D QLC flash memory technology, the multilayer stacked 3D structure becomes a hot spot for future application and research due to its advantages of high capacity and low cost. The QLC NAND refers to a NAND flash memory capable of storing 4bit data in each memory cell, and the 3D design refers to a chip design for realizing three-dimensional stacking of multiple layers in the vertical direction of a silicon chip. However, due to the span of 16 voltage intervals representing data values of the QLC NAND, the gap between each data storage voltage interval is reduced, and the complexity of the manufacturing process of the QLC is increased, four data bits stored in each QLC memory cell need to be written for many times and then reach a certain storage voltage domain, so that actual four-bit data can be represented.

The common practice is to adopt a more complex ECC read data error correction algorithm, optimize an algorithm for related read data in Firmware (Firmware), and the like as much as possible, and ensure the correctness of data written into the QLC flash memory after reading and the usability of the storage device.

Disclosure of Invention

In order to overcome the defects or the improvement requirements of the prior art, the invention provides a method for configuring a plurality of different write operations for a storage device (such as an SSD hard disk) adopting a QLC NAND memory flash memory, and aims to implement different write operations by configuring the attributes of a used 3D QLC NAND through the configuration setting of a storage controller in the storage device, thereby changing the write operation times and the sequence of the QLC NAND flash memory and improving the performance of the stored data of a QLC NAND chip.

According to a first aspect, to implement write operation configuration in a storage controller in a storage device, the present application provides a write operation configuration method based on a QLC NAND flash memory, including the steps of:

representing 16 voltage intervals of the QLC NAND memory unit by adopting 4 bits, wherein each bit is represented as a page address, so that the QLC NAND has four page addresses;

binary coding mapping is carried out on each voltage interval in the 16 voltage intervals by adopting a coding rule, and various different QLC NAND writing operations based on mapping of the four page addresses are realized by promoting storage voltage to a specific voltage interval according to a binary coding mapping relation;

and various QLC NAND writing operations are configured, matched QLC NAND writing operations can be selected according to different data storage requirements, and writing and storage of data in different pages of the QLC NAND are realized.

In one embodiment, four page addresses of the QLC NAND are represented by page0, page1, page2, and page3, respectively, 4-bit data stored in a single memory cell of the QLC NAND is represented by bit 0, bit 1, bit 2, and bit 3, respectively, and when the QLC NAND write operation performs write data storage, the storage voltage is raised to one of the 16 voltage intervals for the QLC NAND memory cell, so as to complete storage of the 4-bit data.

In one embodiment, the QLC NAND write operations include the following eight types:

writing operation one: in the data writing operation, bit 0 data is written into a page0 address, then bit 1 data is written into a page1, then bit 2 data is written into a page2, and finally bit 3 data is written into a page 3;

and a second write operation: the data writing operation writes bit 0 data into a page0 address, then writes bit 1 data and bit 2 data into a page2 and a page3 at the same time, and finally writes bit 3 data into a page 3;

and (3) writing operation III: the data writing operation firstly writes bit 0 data into a page0 address, then writes bit 1 data into a page1, and then writes bit 2 data and bit 3 data into a page2 and a page3 simultaneously;

and writing operation four: the data writing operation writes bit 0 data into a page0 address, and then writes bit 1 data, bit 2 data and bit 3 data into page1, page2 and page3 simultaneously;

and fifthly, writing operation: the data writing operation writes bit 0 data and bit 1 data into page0 and page1 at the same time, then writes bit 2 data into page2, and finally writes bit 3 data into page 3;

and a sixth write operation: the write data operation writes bit 0 data and bit 1 data into page0 and page1 simultaneously, and then writes bit 2 data and bit 3 data into page2 and page3 simultaneously;

the write operation seven: the data writing operation writes bit 0 data, bit 1 data, and bit 2 data into page0, page1, and page2 at the same time, and then writes bit 3 data into page 3;

and eight write operations: the write data operation writes bit 0 data, bit 1 data, bit 2 data, and bit 3 data to page0, page1, page2, and page3 simultaneously.

In one embodiment, the method further comprises setting corresponding write configuration bits for each type of QLC NAND write operation, so that the firmware inputs different write configuration bits according to different requirements to call the corresponding QLC NAND write operation, so as to implement write storage of data in different pages of the QLC NAND.

According to a second aspect, the present application provides a storage controller based on a QLC NAND flash memory, wherein 16 voltage intervals of a QLC NAND memory cell are characterized by 4 bits, each bit is characterized by a page address, the QLC NAND has four page addresses, the storage controller is configured with a plurality of different QLC NAND write operations for the four page addresses, and the plurality of QLC NAND write operations are flexibly configured, so that the storage controller selects the matched QLC NAND write operation according to different data storage requirements, so as to realize fast write-in storage of data in different pages of the QLC NAND.

In one embodiment, the mapping rule of the binary codes corresponding to each of the 16 voltage intervals is that the binary codes of adjacent voltage intervals have only one bit of binary numbers different from each other, so as to reduce the possibility of data errors.

In one embodiment, the QLC NAND write operations are obtained by rapidly combining data to be stored in a plurality of pages according to the encoding mapping rule, thereby representing the voltages of the 16 voltage intervals.

In one embodiment, four page addresses of the QLC NAND are set as page0, page1, page2 and page3, respectively, 4-bit data stored in a single memory cell of the QLC NAND are represented by bit 0, bit 1, bit 2 and bit 3, respectively, and when writing data is performed in the QLC NAND writing operation for storage, the storage voltage is increased to one of the 16 voltage intervals for the QLC NAND memory cell, so that the storage of the 4-bit data is completed.

In one embodiment, the write operation of the QLC includes the following eight types:

writing operation one: the data writing operation can write bit 0 data to page0 address, then write bit 1 data to page1, then write bit 2 data to page2, and finally write bit 3 data to page 3;

and a second write operation: the data writing operation can write bit 0 data to page0 address, then write bit 1 data and bit 2 data to page2 and page3 at the same time, and finally write bit 3 data to page 3;

and (3) writing operation III: the data writing operation can write bit 0 data to page0 address, then write bit 1 data to page1, and then write bit 2 data and bit 3 data to page2 and page3 simultaneously;

and writing operation four: the write data operation may write bit 0 data to page0 address first, and then write bit 1 data, bit 2 data, and bit 3 data to page1, page2, and page3 simultaneously;

and fifthly, writing operation: the data writing operation may write bit 0 data and bit 1 data into page0 and page1 at the same time, then write bit 2 data into page2, and finally write bit 3 data into page 3;

and a sixth write operation: the write data operation may first write bit 0 data and bit 1 data to page0 and page1 simultaneously, and then write bit 2 data and bit 3 data to page2 and page3 simultaneously;

and a seventh write operation: the write data operation may write bit 0 data, bit 1 data, and bit 2 data to page0, page1, and page2 simultaneously, followed by bit 3 data to page 3;

In one embodiment, a configurable TRIM register is designed in the memory controller, and at least one of eight types of the QLC NAND write operations is configured in the TRIM register.

In one embodiment, eight types of the QLC NAND write operations from one write operation to eight write operations are configured in the TRIM register, and different write operation configuration bits are configured for multiple types of the QLC NAND write operations, so that the firmware of the memory controller inputs different write operation configuration bits according to different requirements to call corresponding QLC NAND write operations, so as to implement write-in and storage of data in different pages of the QLC NAND.

In one embodiment, the write configuration bits of the TRIM register are characterized by 3 bits.

According to a third aspect, the present application further provides a memory device, which includes a memory device and the above memory controller, wherein the memory controller may be configured with a plurality of different QLC NAND write operations, so that the memory controller selects a matching QLC NAND write operation according to different data storage requirements to perform different QLC NAND write operations on the memory device.

According to the write operation configuration method of the embodiment, aiming at the characteristics of the QLC NAND type flash memory chip, various write operations are configured and realized in the memory controller; the data writing operation of the storage device is realized by different configurations, so that the firmware design is flexible to use. According to the characteristics of the storage controller and the research and engineering requirements of the write operation characteristics of the QLC NAND flash memory, the invention provides a method which can effectively improve the use performance of the QLC NAND chip in the storage device by configuring different write operation modes in the storage controller, thereby realizing the storage device which meets the requirements of the storage system and has the most suitable write efficiency and the best data write performance. According to the invention, different configurable write operations aiming at the QLC NAND are realized in the storage device, and the data write-in function can be realized according to different factory information of the QLC NAND, so that the storage performance of the QLC NAND chip can be effectively improved.

Drawings

FIG. 1 is a flow chart of a QLC NAND write operation configuration;

FIG. 2 is a QLC NAND voltage distribution diagram;

FIG. 3 is a diagram of different write operations of a QLC NAND;

wherein, fig. 3 (a) shows a write operation one: sequentially writing data into pages 0-1-2-3;

FIG. 3 (b) shows write operation two: sequentially writing data into pages 0-1-2/3;

FIG. 3 (c) shows write operation three: sequentially writing data into pages 0-1/2-3;

FIG. 3 (d) shows a fourth write operation: sequentially writing data into pages 0-1/2/3;

FIG. 3 (e) shows write operation five: sequentially writing data into pages 0/1-2-3;

FIG. 3 (f) shows a write operation six: sequentially writing data into pages 0/1-2/3;

FIG. 3 (g) shows a write operation seven: sequentially writing data into pages 0/1/2-3;

FIG. 3 (h) shows a write operation eight: simultaneously writing data into page0/1/2/3;

FIG. 4 is a diagram of the configuration of the write operation in the controller for the QLC NAND;

FIG. 5 is a functional block diagram of a memory device;

fig. 6 is a schematic diagram of the application of fig. 5.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.

The storage device based on the QLC NAND flash memory is designed by using a QLC NAND storage controller and integrating a 3D QLC NAND chip to realize data reading and writing. To achieve the above object, this example proposes a basic idea of configuring a memory controller to implement various write operations.

The first embodiment is as follows:

the present example provides a write operation configuration method based on a QLC NAND flash memory, which implements a plurality of different QLC NAND write operations in a memory controller, and a flowchart thereof is shown in fig. 1, and specifically includes the following steps.

S1: the 16 voltage intervals of the QLC NAND memory unit are characterized by 4 bits, each bit is characterized by a page address, and the QLC NAND memory unit has four page addresses.

Specifically, for the QLC NAND memory cell, because the voltage characteristics thereof have 16 voltage intervals in total, and the QLC NAND voltage distribution diagram is as shown in fig. 2, the 16 voltage intervals can be converted into 4 bits (bit) for representation, each bit can be regarded as a page address, so that the QLC NAND cell has 4 page addresses which can be set as page0 (page 0), page1 (page 1), page2 (page 2) and page3 (page 3), respectively, and correspondingly, 4-bit data stored by a single memory cell of the QLC NAND cell are represented by bit 0, bit 1, bit 2 and bit 3, respectively, and when the QLC NAND write operation is performed to write data for storage, the storage voltage of the QLC NAND memory cell is raised to one of 16 voltage intervals, so as to complete storage of the 4-bit data.

The conventional write operation of the QLC NAND is only one type at present, i.e. sequential write operation: bit 0 data is written to page0 address, then bit 1 data is written to page1, then bit 2 data is written to page2, and finally bit 3 data is written to page 3.

The basic concept of the multiple write operations proposed in this example is to break through this single write operation sequence and configure multiple QLC NAND write operations, so as to change the number and order of write operations of the QLC NAND flash memory and improve the performance of the stored data of the QLC NAND chip, and the specific operation process is step S2 and step S3.

S2: and binary coding mapping is carried out on each voltage interval in the 16 voltage intervals by adopting a coding rule, and various different QLC NAND writing operations based on four page address mappings are realized by promoting the storage voltage to a specific voltage interval according to the binary coding mapping relation.

Because each voltage interval in 16 voltage intervals is represented by 4 bits, in order to enable binary codes of any two adjacent voltage intervals to have only one binary number, the encoding rule of the embodiment adopts a gray code rule to respectively carry out binary encoding mapping on each voltage interval in 16 voltage intervals, and according to the binary encoding mapping relation, the storage voltage is promoted to a certain specific voltage interval in the 16 voltage intervals, so that the QLC NAND writing operation corresponding to the specific voltage interval is obtained, and various different QLC NAND writing operations based on four page address mappings are realized.

Specifically, the QLC NAND write operation generated by the present example using the gray code rule by raising the storage voltage to a specific voltage interval of 16 voltage intervals includes the following eight types:

the first writing operation: in the data writing operation, bit 0 data is written into a page0 address, then bit 1 data is written into a page1, then bit 2 data is written into a page2, and finally bit 3 data is written into a page 3; the procedure of write operation one is shown in fig. 3 (a).

And a second write operation: the data writing operation writes bit 0 data into a page0 address, then writes bit 1 data and bit 2 data into a page2 and a page3 at the same time, and finally writes bit 3 data into a page 3; the process of write operation two is shown in fig. 3 (b).

And (3) writing operation III: the write data operation writes bit 0 data to page0 address, then bit 1 data to page1, and then bit 2 data and bit 3 data to page2 and page3 simultaneously.

And (4) writing operation four: the write data operation writes bit 0 data to page0 address first, and then writes bit 1 data, bit 2 data, and bit 3 data to page1, page2, and page3 simultaneously.

And fifthly, writing operation: the write data operation writes bit 0 data and bit 1 data to page0 and page1 simultaneously, then writes bit 2 data to page2, and finally writes bit 3 data to page 3.

And a sixth write operation: the write data operation writes bit 0 data and bit 1 data into page0 and page1 simultaneously, and then writes bit 2 data and bit 3 data into page2 and page3 simultaneously; the process of write operation six is shown in fig. 3 (f).

The write operation seven: the write data operation writes bit 0 data, bit 1 data, and bit 2 data into page0, page1, and page2 simultaneously, and then writes bit 3 data into page 3; the process of write operation seven is shown in fig. 3 (g).

And eight write operations: a write data operation writes bit 0 data, bit 1 data, bit 2 data, and bit 3 data to page0, page1, page2, and page3 simultaneously; the procedure for write operation eight is shown in fig. 3 (h).

S3: and various QLC NAND writing operations are configured, matched QLC NAND writing operations can be selected according to different data storage requirements, and writing and storage of data in different pages of the QLC NAND are realized.

Further, in this example, a corresponding write configuration bit is set for each type of QLC NAND write operation, so that the firmware of the memory controller inputs different write configuration bits through an interface protocol according to different data storage requirements to call the corresponding QLC NAND write operation, thereby implementing write storage of data in different pages of the QLC NAND. For example, the interface protocol may be PCIe, SATA, UFS, or the like, and in order to accommodate 8 different write operations of the QLC NAND, 8 different write operation configuration bits are correspondingly configured, where the 8 different write operation configuration bits correspond to 8 different write operations associated with the QLC, and the write operation configuration bits are characterized by 3bits (3 bits).

The example provides different write operation configuration methods of the QLC NAND flash memory, so as to implement different write operations by performing attribute configuration according to 3D QLC NAND, thereby changing the write operation times and sequence of the QLC NAND flash memory.

Example two:

according to a first embodiment, the present example provides a storage controller based on a QLC NAND flash memory, and QLC NAND different write operations are configured in the storage controller.

The 16 voltage intervals of the QLC NAND memory unit are represented by 4 bits, each bit is represented by a page address, the QLC NAND is provided with four page addresses, various QLC NAND writing operations are configured for the four page addresses in the memory controller, the various QLC NAND writing operations can be flexibly configured, and the memory controller selects the matched QLC NAND writing operation according to different data storage requirements to realize the rapid writing and storage of data in different pages of the QLC NAND.

The mapping rule of the binary codes corresponding to each voltage interval in the 16 voltage intervals is that the binary codes of adjacent voltage intervals have only one binary number difference, so as to reduce the possibility of data errors, for example, the gray code rule, and the voltages in the 16 voltage intervals are represented by quickly combining the data to be stored in the multiple pages according to the mapping rule, so as to obtain multiple kinds of QLC NAND write operations.

Similarly, four page addresses of the QLC NAND are represented by page0, page1, page2 and page3, respectively, and 4-bit data stored in a single memory cell of the QLC NAND are represented by bit 0, bit 1, bit 2 and bit 3, respectively, so that when a write data is stored in the QLC NAND write operation, the storage voltage is raised to one of 16 voltage intervals for the QLC NAND memory cell, and the storage of the 4-bit data is completed.

Specifically, a configurable TRIM register is designed in the memory controller, and at least one write operation of eight types of QLC NAND write operations is configured in the TRIM register, in this example, eight types of QLC NAND write operations from one write operation to eight write operations are configured in the TRIM register, and different write operation configuration bits are correspondingly configured for the different types of QLC NAND write operations, so that the firmware of the memory controller inputs different write operation configuration bits through an interface protocol according to different data storage requirements to call the corresponding QLC NAND write operations, thereby implementing write storage of data in different pages of the QLC NAND.

The TRIM register of this example is embedded with 8 different write configuration bits, where the 8 different write configuration bits correspond to 8 different write operations associated with the QLC NAND, where the write configuration bits of the TRIM register are represented by 3bits, and a schematic diagram of the write operations of the QLC NAND configured correspondingly by the different write configuration bits in the TRIM register is shown in fig. 4.

By designing configurable TRIM registers for the memory controller and configuring different write operations of the QLC NAND in the TRIM registers, the method is flexible to use in firmware design.

Based on the above memory controller, this example also provides a memory device, which includes a memory device and the above memory controller, and its functional block diagram is shown in fig. 5, where the memory controller may be configured with a plurality of different QLC NAND write operations, so that the memory controller can select a matching QLC NAND write operation according to different data storage requirements to perform different QLC NAND write operations on the memory device.

That is, a memory controller in the memory device implements TRIM register TRIM [ 2.

Fig. 6 shows a schematic diagram of a specific application of the storage device in this example, specifically, the host device sends an instruction to the storage controller in the storage device according to different data storage requirements and interface instruction sets of the system, and sets a hardware TRIM register in the storage controller. And the memory controller inputs different data to different channels or appointed NAND memory device configurations according to the current data processing condition and a firmware design algorithm, and selects different write operations.

After passing through the configured TRIM register values, actual different data write operations are performed on the NAND memory device through the NAND flash memory related instruction set and driver.

The application of the write operation is exemplified below with different types of storage devices.

For example, for the SSD storage device, the write operation configuration bit is set to be equal to "101" and the value of the TRIM register is set to "101" by inputting to the SSD controller through the host according to the PCIe or SATA interface protocol; then according to a firmware designated algorithm and drive in the SSD controller, the write operation of the NAND memory device on a certain channel is determined as that firstly, bit 0 data and bit 1 data are written into page0 and page1 simultaneously, then, bit 2 data and bit 3 data are written into page2 and page3 simultaneously, at the moment, the host end inputs the data of page0 and page1 according to the write instruction requirements in sequence, after the write operation is completed within a specified write time, the data of page2 and page3 are continuously input according to the write instruction requirements in sequence, and finally, the data write operation of 4 pages is completed after the write operation is completed within the specified write time, so that the SSD controller can conveniently realize various QLC write operations in each NAND memory device.

For example, for the UFS storage device, a write operation configuration value "000" may be input to a write operation TRIM register in the UFS controller through the host according to the UFS protocol; and then according to a firmware designated algorithm and drive in the UFS controller, writing data of page0 from the host according to the UFS writing instruction, waiting for a specified writing time to finish the writing operation, then continuing to input data of page1 according to the writing instruction requirement in sequence, waiting for the completion of the writing operation, data of page2, waiting for the completion of the writing operation, and data of page3, waiting for the completion of the writing operation. So that the UFS controller can conveniently implement different QLC write operations in the NAND memory device.

The present invention is illustrated above using specific examples, which are only used to help understanding of the present invention, and are not used to limit the present invention. Numerous simple deductions, modifications or substitutions may also be made by those skilled in the art in light of the present teachings. For example, the storage devices and storage controllers of the present invention include, but are not limited to, data storage devices such as SSD, UFS, eMMC, etc., and any type of storage device is included within the scope of the present invention. The storage device control described in the present invention is not limited to the controller, and any device or controller that controls the operation of the storage device belongs to the scope of the present invention.

Claims

1. The write operation configuration method based on the QLC NAND flash memory is characterized by comprising the following steps: representing 16 voltage intervals of the QLC NAND memory unit by adopting 4 bits, wherein each bit is represented as a page address, so that the QLC NAND has four page addresses;

binary coding mapping is carried out on each voltage interval in the 16 voltage intervals by adopting a coding rule, and various different QLC NAND writing operations based on four page address mapping are realized by promoting storage voltage to a specific voltage interval according to the binary coding mapping relation;

2. The write operation configuration method as claimed in claim 1, wherein four page addresses of the QLC NAND are represented by page0, page1, page2 and page3, respectively, 4-bit data stored in a single memory cell of the QLC NAND are represented by bit 0, bit 1, bit 2 and bit 3, respectively, and when the QLC NAND write operation performs write data storage, the storage voltage is raised to one of the 16 voltage intervals for the QLC NAND memory cell, so as to complete storage of the 4-bit data.

3. The write operation configuration method of claim 2, wherein the QLC NAND write operations comprise the following eight types:

the first writing operation: in the data writing operation, bit 0 data is written into a page0 address, then bit 1 data is written into a page1, then bit 2 data is written into a page2, and finally bit 3 data is written into a page 3;

and (3) writing operation III: the data writing operation writes bit 0 data into a page0 address, writes bit 1 data into a page1, and then writes bit 2 data and bit 3 data into a page2 and a page3 simultaneously;

and a seventh write operation: the write data operation writes bit 0 data, bit 1 data, and bit 2 data into page0, page1, and page2 simultaneously, and then writes bit 3 data into page 3;

4. The write operation configuration method as claimed in claim 1 or 3, further comprising setting corresponding write operation configuration bits for each type of QLC NAND write operation, so that the firmware inputs different write operation configuration bits according to different requirements to call the corresponding QLC NAND write operation, so as to implement write storage of data in different pages of the QLC NAND.

5. A storage controller based on a QLC NAND flash memory is characterized in that a plurality of different QLC NAND writing operations are configured in the storage controller for the four page addresses, the various QLC NAND writing operations can be flexibly configured, so that the storage controller selects the matched QLC NAND writing operation according to different data storage requirements, and the rapid writing and storage of data in different pages of the QLC NAND are realized.

6. The memory controller of claim 5, wherein each of the 16 voltage intervals corresponds to a binary code mapping rule that binary codes of adjacent voltage intervals have only one binary number difference, so as to reduce the possibility of data errors.

7. The memory controller of claim 6, wherein a plurality of said QLC NAND write operations are obtained by rapidly combining data to be stored in a plurality of pages according to said code mapping rules, thereby characterizing the voltages of said 16 voltage intervals.

8. The memory controller as claimed in claim 7, wherein the four page addresses of the QLC NAND are represented by page0, page1, page2 and page3, respectively, and the 4-bit data stored in a single memory cell of the QLC NAND is represented by bit 0, bit 1, bit 2 and bit 3, respectively, and when the QLC NAND write operation performs write data storage, the storage voltage is raised to one of the 16 voltage intervals for the QLC NAND memory cell, so as to complete the storage of the 4-bit data.

9. The memory controller of claim 8, in which the QLC NAND write operations comprise eight types:

and (4) writing operation four: the data writing operation writes bit 0 data into a page0 address, and then writes bit 1 data, bit 2 data and bit 3 data into page1, page2 and page3 simultaneously;

and a fifth write operation: the data writing operation writes bit 0 data and bit 1 data into page0 and page1 at the same time, then writes bit 2 data into page2, and finally writes bit 3 data into page 3;

the write operation seven: the write data operation writes bit 0 data, bit 1 data, and bit 2 data into page0, page1, and page2 simultaneously, and then writes bit 3 data into page 3;

10. The memory controller of claim 9, wherein the memory controller has a configurable TRIM register programmed therein, the TRIM register having at least one of eight types of the QLC NAND write configured therein.

11. The memory controller as claimed in claim 10, wherein eight types of the QLC NAND write operations, i.e. one write operation to eight write operations, are configured in the TRIM register, and different write configuration bits are correspondingly configured for the plurality of types of the QLC NAND write operations, so that the firmware of the memory controller inputs different write configuration bits according to different requirements to call the corresponding QLC NAND write operation, so as to implement write storage of data in different pages of the QLC NAND.

12. The memory controller of claim 11, wherein the write configuration bit of the TRIM register is characterized with 3 bits.

13. A memory device comprising a memory device and the memory controller of any of claims 5-12, wherein the memory controller is configured with a plurality of different QLC NAND write operations, such that the memory controller selects a matching QLC NAND write operation for a different QLC NAND write operation on the memory device according to different data storage requirements.