CN109526144A - A kind of analysis method and system that difference via hole aperture influences the magnitude of current - Google Patents
A kind of analysis method and system that difference via hole aperture influences the magnitude of current Download PDFInfo
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- CN109526144A CN109526144A CN201811569869.2A CN201811569869A CN109526144A CN 109526144 A CN109526144 A CN 109526144A CN 201811569869 A CN201811569869 A CN 201811569869A CN 109526144 A CN109526144 A CN 109526144A
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- 238000004458 analytical method Methods 0.000 title claims description 33
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000013178 mathematical model Methods 0.000 claims abstract description 6
- 230000003071 parasitic effect Effects 0.000 claims description 16
- 230000000694 effects Effects 0.000 claims description 6
- 238000004088 simulation Methods 0.000 claims description 4
- 238000004364 calculation method Methods 0.000 claims 1
- 230000005611 electricity Effects 0.000 abstract description 3
- 230000008859 change Effects 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004141 dimensional analysis Methods 0.000 description 2
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- 238000003801 milling Methods 0.000 description 2
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- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
本发明提供了一种不同过孔孔径对电流量影响的分析方法与系统，包括以下步骤：S1、通过数学模型分析短柱对信号完整性影响，确定电路的谐振频率；S2、在信号换层之后的参考层仍然是同一平面时，获取电流通过率；S3、在信号换层之后参考相同性质的不同平面时，获取电流通过率；S4、在信号换层之后参考不同性质的平面时，获取电流通过率；S5、比对不同情况下的电流通过率，选取最优叠层结构。本发明实现确定电路的谐振频率，确保每块子卡运行平稳，解决了现有技术中过孔电量通过量按照1A处理时造成过孔数量增加以及高速线走线空间变少的问题，实现对过孔的通流能力进行验证，保证信号完整性，增强系统可靠性，保证能够正常的运行。
The present invention provides a method and system for analyzing the influence of different via hole diameters on the amount of current, including the following steps: S1, analyzing the influence of the short column on the signal integrity through a mathematical model, and determining the resonant frequency of the circuit; S2, changing layers in the signal When the subsequent reference layer is still the same plane, the current passing rate is obtained; S3, when the signal is changed to layers with reference to different planes of the same nature, the current passing rate is obtained; S4, after the signal layer is changed, the current passing rate is obtained when referring to different planes Current passing rate; S5, compare the current passing rate under different conditions, and select the optimal laminated structure. The invention realizes the determination of the resonant frequency of the circuit, ensures the stable operation of each sub-card, solves the problems of increasing the number of via holes and reducing the routing space of high-speed lines in the prior art when the electricity throughput of the via holes is processed according to 1A, and realizes The flow capacity of the via hole is verified to ensure signal integrity, enhance system reliability, and ensure normal operation.
Description
Technical field
The present invention relates to high speed transmission of signals technical field, especially a kind of point that different via hole apertures influence the magnitude of current
Analyse method and system.
Background technique
With the continuous improvement of digital circuit rate and clock frequency, in High Speed System, high speed signal is by interconnection
Line can generate the problems of Signal Integrity such as delay, reflection, decaying, crosstalk.Problems of Signal Integrity has become high speed number
One of whether successful critical issue of word circuit design.
The principal element of high-speed figure PCB signal integrity is influenced in addition to PCB design and pcb board material select, via hole pair
Signal integrity has larger impact.In high speed multi-layer PCB, when signal is transferred to certain layer internal from top layer, connected with through-hole
Extra via hole short column will be generated, short column largely affects the transmission quality of signal.
When signal is when being transferred to another sandwich circuit of impedance matching by via hole, has part energy and be passed to
On the short column in hole, and this is partially due to not any impedance terminates, it is possible to be counted as standard-sized sheet line state.Therefore,
This branch will cause the total reflection of dump energy, this greatly weakens signal quality, damage the complete of original signal
Property.
In the prior art, the magnitude of current of 1A usually is corresponded to be handled according to a via hole using for via hole, but
It is that this way will cause number of vias increase, high-speed line cabling space tails off.
Summary of the invention
The object of the present invention is to provide a kind of analysis methods and system that different via hole apertures influence the magnitude of current, it is intended to solve
Certainly number of vias is excessive in the prior art, the very few problem of high-speed line cabling space, and the through-current capability of via hole is tested in realization
Card guarantees signal integrity, enhances system reliability, guarantees normally to run.
To reach above-mentioned technical purpose, the present invention provides a kind of analysis sides that different via hole apertures influence the magnitude of current
Method, comprising the following steps:
S1, signal integrity is influenced by mathematics model analysis short column, determines the resonance frequency of circuit；
S2, when the reference layer after signal changes layer is still same plane, obtain current passing rate；
S3, after signal changes layer refer to same nature Different Plane when, obtain current passing rate；
S4, after signal changes layer refer to plane of different nature when, obtain current passing rate；
Current passing rate under S5, comparison different situations, chooses optimal laminated construction.
Preferably, the step S1 concrete operations are as follows:
Obtain the equivalent model of short column via hole；
The resonance conditions at via hole are calculated using resonant frequency equation；
Influence of the simulating, verifying via hole aperture to signal.
Preferably, the resonant frequency equation are as follows:
fresThe resonance frequency generated for short column end；L is the parasitic inductance of short column；C is the parasitic capacitance of short column.
Preferably, need to be arranged via diameter, interior pad diameter and via height before obtaining current passing rate.
The present invention also provides a kind of analysis system that different via hole apertures influence the magnitude of current, the system comprises:
Harmonic analysis module determines the resonance of circuit for influencing by mathematics model analysis short column on signal integrity
Frequency；
Same reference planes analysis module, for obtaining when the reference layer after signal changes layer is still same plane
Current passing rate；
Same nature Different Plane analysis module, for after signal changes layer refer to same nature Different Plane when,
Obtain current passing rate；
Heterogeneity two dimensional analysis module, for obtaining electric current when referring to plane of different nature after signal changes layer
Percent of pass；
Comparison module chooses optimal laminated construction for comparing the current passing rate under different situations.
Preferably, the harmonic analysis module includes:
Equivalent model acquiring unit, for obtaining the equivalent model of short column via hole；
Resonance computing unit, for calculating the resonance conditions at via hole using resonant frequency equation；
Simulation unit, the influence for simulating, verifying via hole aperture to signal.
Preferably, the resonant frequency equation are as follows:
fresThe resonance frequency generated for short column end；L is the parasitic inductance of short column；C is the parasitic capacitance of short column.
Preferably, described to need to be arranged via diameter, interior pad diameter and via height before obtaining current passing rate.
The effect provided in summary of the invention is only the effect of embodiment, rather than invents all whole effects, above-mentioned
A technical solution in technical solution have the following advantages that or the utility model has the advantages that
Compared with prior art, the present invention is in a manner of mathematical model analyzing influence of the short column to signal integrity,
Respectively when the reference layer after signal changes layer is still same plane, signal change after layer the Different Plane for referring to same nature
When, electric current throughput when signal changes after layer with reference to plane of different nature, to realize the resonance frequency of determining circuit, really
It protects every piece of subcard to run smoothly, solves and cause number of vias to increase when via hole electricity throughput is handled according to 1A in the prior art
And the through-current capability of via hole is verified in high-speed line cabling space the problem of tailing off, realization, guarantees signal integrity, enhancing
System reliability guarantees normally to run.
Detailed description of the invention
Fig. 1 is a kind of analysis method process that different via hole apertures influence the magnitude of current provided in the embodiment of the present invention
Figure；
When Fig. 2 is still same plane for a kind of reference layer after signal changes layer provided in the embodiment of the present invention
Schematic diagram of laminated structure；
Fig. 3 is a kind of when referring to the Different Plane of same nature after signal changes layer provided in the embodiment of the present invention
Schematic diagram of laminated structure；
Fig. 4 is a kind of folded when referring to plane of different nature after signal changes layer provided in the embodiment of the present invention
Schematic diagram of a layer structure；
Fig. 5 is a kind of analysis system structure that different via hole apertures influence the magnitude of current provided in the embodiment of the present invention
Block diagram.
Specific embodiment
In order to clearly illustrate the technical characterstic of this programme, below by specific embodiment, and its attached drawing is combined, to this
Invention is described in detail.Following disclosure provides many different embodiments or example is used to realize different knots of the invention
Structure.In order to simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relationship between various embodiments and/or setting is discussed.It should be noted that illustrated component is not necessarily to scale in the accompanying drawings
It draws.Present invention omits the descriptions to known assemblies and treatment technology and process to avoid the present invention is unnecessarily limiting.
It is provided for the embodiments of the invention a kind of analysis that different via hole apertures influence the magnitude of current with reference to the accompanying drawing
Method and system is described in detail.
As shown in Figure 1, the embodiment of the invention discloses a kind of analysis method that different via hole apertures influence the magnitude of current, packet
Include following steps:
S1, signal integrity is influenced by mathematics model analysis short column, determines the resonance frequency of circuit；
S2, when the reference layer after signal changes layer is still same plane, obtain current passing rate；
S3, after signal changes layer refer to same nature Different Plane when, obtain current passing rate；
S4, after signal changes layer refer to plane of different nature when, obtain current passing rate；
Current passing rate under S5, comparison different situations, chooses optimal laminated construction.
Using server master board as core, other subcards are auxiliary, are connected by cable or other kinds of electric wire, by
In the influence that nearly all can inevitably encounter via hole short column in actual circuit plate, so being divided by way of mathematical model
Influence of the short column to signal integrity is precipitated, determines the resonance frequency of circuit, so that it is guaranteed that every piece of subcard runs smoothly, it is then whole
A system can normally be run.
The equivalent model for obtaining short column via hole calculates the resonance conditions at via hole, simulating, verifying using resonant frequency equation
Influence of the via hole aperture to signal.It is as follows that the resonance frequency calculates formula:
fresThe resonance frequency generated for short column end；L is the parasitic inductance of short column；C is the parasitic capacitance of short column.
Test plate (panel) is made, production process is as follows:
Sawing sheet-drying-plate-internal layer dry film-internal layer etching-interior AOI- brownification-lamination-milling side-drilling-desmearing-sinks copper-outside
Layer plating-graphic plating-control gun drilling-outer layer etching-outer layer dry film-graphic plating-outer layer etching-outer AOI- welding resistance-turmeric-
Milling plate.
The level that signal flows through is respectively first layer and third layer, thus from third layer via hole below not can
On.When signal will continue to flow through to the levels such as the 4th layer and layer 5 after third layer, when being transferred to the bottom, this phase
When in open circuit, at this moment reflection coefficient is 1, and signal can be reflected.When signal after reflection passes through third layer, due to the change of impedance
Change, and the levels such as the 4th layer and layer 5 can be reflected to, back and forth, strong influence the integrality of signal.
Signal schematic representation, the signal that Fig. 2-4 is respectively the reference layer that changes after layer of signal when being still same plane change layer
Letter when signal schematic representation, signal when referring to the Different Plane of same nature later change after layer with reference to plane of different nature
Number schematic diagram.For high speed signal, via hole can generate parasitic capacitance and parasitic inductance, and parasitic capacitance mainly rises digital signal
Along slowing down, particularly with multiple signal transition, the speed of circuit is seriously reduced, the harm of parasitic inductance bring is often bigger,
The validity that electrical power by-pass capacitor can be reduced by series inductance makes entire power supply power supply filter effect be deteriorated.
Respectively when the reference layer after signal changes layer is still same plane, signal changes after layer with reference to same nature
When Different Plane, when signal is changed after layer with reference to plane of different nature, setting via diameter, interior pad diameter and via hole are high
Degree obtains current passing rate, compares the current passing rate under different situations, chooses optimal laminated construction.
The embodiment of the present invention in a manner of mathematical model analyzing influence of the short column to signal integrity, respectively in signal
Change the reference layer after layer when being still same plane, signal changes after layer when referring to the Different Plane of same nature, signal changes
Electric current throughput when after layer with reference to plane of different nature, to realize the resonance frequency of determining circuit, it is ensured that every piece of son
Card runs smoothly, and solves and causes number of vias increase and high speed when via hole electricity throughput is handled according to 1A in the prior art
The through-current capability of via hole is verified in the problem of line cabling space tails off, realization, guarantees signal integrity, and enhancing system is reliable
Property, guarantee normally to run.
As shown in figure 5, the embodiment of the invention also discloses a kind of analysis system that different via hole apertures influence the magnitude of current,
The system comprises:
Harmonic analysis module determines the resonance of circuit for influencing by mathematics model analysis short column on signal integrity
Frequency；
Same reference planes analysis module, for obtaining when the reference layer after signal changes layer is still same plane
Current passing rate；
Same nature Different Plane analysis module, for after signal changes layer refer to same nature Different Plane when,
Obtain current passing rate；
Heterogeneity two dimensional analysis module, for obtaining electric current when referring to plane of different nature after signal changes layer
Percent of pass；
Comparison module chooses optimal laminated construction for comparing the current passing rate under different situations.
The harmonic analysis module includes:
Equivalent model acquiring unit, for obtaining the equivalent model of short column via hole；
Resonance computing unit, for calculating the resonance conditions at via hole using resonant frequency equation；
Simulation unit, the influence for simulating, verifying via hole aperture to signal.
The resonant frequency equation are as follows:
fresThe resonance frequency generated for short column end；L is the parasitic inductance of short column；C is the parasitic capacitance of short column.
It is described to need to be arranged via diameter, interior pad diameter and via height before obtaining current passing rate.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811569869.2A CN109526144B (en) | 2018-12-21 | 2018-12-21 | A method and system for analyzing the influence of different via hole diameters on current flow |
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| CN201811569869.2A CN109526144B (en) | 2018-12-21 | 2018-12-21 | A method and system for analyzing the influence of different via hole diameters on current flow |
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| CN109526144B CN109526144B (en) | 2021-07-27 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5863447A (en) * | 1997-04-08 | 1999-01-26 | International Business Machines Corporation | Method for providing a selective reference layer isolation technique for the production of printed circuit boards |
| JP2002368432A (en) * | 2001-06-04 | 2002-12-20 | Murata Mach Ltd | Multilayer board and cad device for designing the same |
| CN202425186U (en) * | 2011-09-27 | 2012-09-05 | 京信通信系统（中国）有限公司 | Pcb |
| CN103260348A (en) * | 2013-04-01 | 2013-08-21 | 广州兴森快捷电路科技有限公司 | High-speed PCB and difference via hole impedance control method |
| CN105357903A (en) * | 2015-12-04 | 2016-02-24 | 浪潮(北京)电子信息产业有限公司 | Lamination method of PCB, and PCB |
| CN107169233A (en) * | 2017-06-09 | 2017-09-15 | 郑州云海信息技术有限公司 | The Rack server design methods of research are influenceed on signal integrity based on short column resonance |
| CN107273601A (en) * | 2017-06-09 | 2017-10-20 | 郑州云海信息技术有限公司 | Method is influenceed to signal integrity based on FDTD Algorithm Analysis ground hole |
-
2018
- 2018-12-21 CN CN201811569869.2A patent/CN109526144B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5863447A (en) * | 1997-04-08 | 1999-01-26 | International Business Machines Corporation | Method for providing a selective reference layer isolation technique for the production of printed circuit boards |
| JP2002368432A (en) * | 2001-06-04 | 2002-12-20 | Murata Mach Ltd | Multilayer board and cad device for designing the same |
| CN202425186U (en) * | 2011-09-27 | 2012-09-05 | 京信通信系统（中国）有限公司 | Pcb |
| CN103260348A (en) * | 2013-04-01 | 2013-08-21 | 广州兴森快捷电路科技有限公司 | High-speed PCB and difference via hole impedance control method |
| CN105357903A (en) * | 2015-12-04 | 2016-02-24 | 浪潮(北京)电子信息产业有限公司 | Lamination method of PCB, and PCB |
| CN107169233A (en) * | 2017-06-09 | 2017-09-15 | 郑州云海信息技术有限公司 | The Rack server design methods of research are influenceed on signal integrity based on short column resonance |
| CN107273601A (en) * | 2017-06-09 | 2017-10-20 | 郑州云海信息技术有限公司 | Method is influenceed to signal integrity based on FDTD Algorithm Analysis ground hole |
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