CN109525844A - A kind of acceleration system and method for multi-channel video encoding and decoding - Google Patents
A kind of acceleration system and method for multi-channel video encoding and decoding Download PDFInfo
- Publication number
- CN109525844A CN109525844A CN201910090918.2A CN201910090918A CN109525844A CN 109525844 A CN109525844 A CN 109525844A CN 201910090918 A CN201910090918 A CN 201910090918A CN 109525844 A CN109525844 A CN 109525844A
- Authority
- CN
- China
- Prior art keywords
- chip
- decoding
- fpga
- camera
- accelerator card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001133 acceleration Effects 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 35
- 230000015654 memory Effects 0.000 claims abstract description 34
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 claims abstract description 8
- 241001269238 Data Species 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 230000006870 function Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/231—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
- H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
- H04N21/234309—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4 or from Quicktime to Realvideo
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention proposes the acceleration system and method for a kind of multi-channel video encoding and decoding, which includes Camera, Server and accelerator card.Accelerator card includes BMC control module, chip processing module and power module；BMC control module is used for out of band supervision management, and chip processing module is BMC control module and chip processing module for power supply for carrying out multi-channel video encoding and decoding, power module.Wherein chip processing module includes 2,3 or 4 fpga chips, and fpga chip is separately connected two DDR4 memory bars, jtag circuit, SPI Flash and EMMC, is interconnected between each fpga chip using Chiplink, and fpga chip is connected to Switch.Based on the acceleration system, it is also proposed that the accelerated method of multi-channel video encoding and decoding.The present invention is realized using fpga chip, without using the CPU for having coding and decoding video function, such as the E3 of intel, is cooperated the tall and handsome P4 card reached, is greatly reduced in cost.In addition 2,3 or 3 fpga chips are used, the speed of coding and decoding video can be improved according to actual needs.
Description
Technical field
The present invention relates to server video encoding and decoding technique fields, specifically provide a kind of acceleration of multi-channel video encoding and decoding
System and method.
Background technique
In recent years, the life of the continuous development let us of network technology is more and more abundant colorful.There is this convenience of network
Carrier, the progress that multimedia technology is also maked rapid progress, as the core and key of multimedia technology, multimedia video
Encoding and decoding all achieve major progress in technology and application aspect in recent years.The main function of Video coding is by video image prime number
It is collapsed into video code flow according to RGB or YUV etc., to reduce the data volume of video.
More and more for the application demand of present coding and decoding video, present client is all based on to compile with video and solve
The CPU of code function, such as the E3 of intel, cooperate the tall and handsome P4 card reached.Current E3 integrated codec chip maximum processing capability
It is 12 road 1080P.And only have 2 chips to be used for coding and decoding video in P4 card, if being intended only as encoding and decoding single application, P4
Other calculated performances possessed by blocking undoubtedly are exactly to waste, and the price of P4 card is more expensive.Based on current many customers' places
Small video is managed, the multiple business such as live streaming even more occurs in security protection, on the road of encoding and decoding and cost has higher want
It asks.
Summary of the invention
For disadvantage mentioned above, the embodiment of the present invention proposes the acceleration system and method for a kind of multi-channel video encoding and decoding, drop
Low cost, while improving the speed of the encoding and decoding of multi-channel video.
The embodiment of the present invention proposes a kind of acceleration system of multi-channel video encoding and decoding, including Camera, Server and adds
Speed card, the accelerator card includes BMC control module, chip processing module and power module；
The BMC control module includes BMC, house dog, fan, temperature sensor and EEPROM；The BMC passes through UART
It is connected with house dog；The BMC is connected with fan, temperature sensor and EEPROM respectively by I2C；
The chip processing module includes 2,3 or 4 fpga chips；The fpga chip is separately connected two DDR4 memories
Item, jtag circuit, SPI Flash and EMMC；It is interconnected between the fpga chip using Chiplink, and the fpga chip
Switch is also connected to by UART；
The power module includes power regulator；The power regulator connects external+12V power supply, while controlling with BMC
Molding block is connected with chip processing module；
The power module is BMC control module and chip processing module for power supply；The BMC control module is used for out-of-band supervision
Keyholed back plate reason；The chip processing module is for carrying out multi-channel video encoding and decoding.
Further, the accelerator card further include programmable clock chip, indicator light key, reset key, test point by
Key and external interface；
The programmable clock chip is for being kept for synchronous clock, display and record time；
The indicator light key, which is used to indicate, accelerates card failure or in place；
The reset key is used to restart in case of constant power when accelerator card breaks down；
The input and output of pin when the test point key is tested for fpga chip；
The external interface includes USB and HUB.
Further, the fpga chip uses the ZU7EV chip of Xilinx.
Further, the capacity of the DDR4 memory bar is 4GB.
Further, it is interconnected between the fpga chip using Chiplink, is used between the fpga chip
The port specification of Chiplink interconnection is Serdes x4, and the fpga chip walks line rate 10Gbps.
A kind of accelerated method of multi-channel video encoding and decoding is that the acceleration system based on a kind of multi-channel video encoding and decoding is realized,
It the described method comprises the following steps:
The H.264/H.265 coded data that S1:Server transmits Camera IP Camera is sent in accelerator card
Chip processing module；
S2: the H.264/H.265 coded data that the chip processing module in accelerator card transmits Camera IP Camera
It is averagely allocated to each fpga chip according to code stream, each fpga chip is decoded the bit stream data received, so first
CNN reasoning acceleration is carried out afterwards and retrieval accelerates；
S3: accelerator card will be sent to Server by each processed bit stream data of fpga chip in chip processing module
In memory.
Further, step S1 includes:
Server memory is written in the H.264/H.265 coded data that NIC transmits Camera IP Camera in Server
First memory headroom of middle App process；
Accelerator card driving is called, and applies for the second required memory headroom of accelerator card driving in accelerator card memory, and will
The H.264/H.265 coded data copy of Camera IP Camera transmission is mapped to the second memory headroom.
Further, step S2 includes:
Server writes the PCIE accelerator card register in the space MMCFG, and FPGA reads Camera IP Camera using DMA
The H.264/H.265 coded data of transmission, by the H.264/H.265 coded data of Camera IP Camera transmission from the
Two spaces are transported to chip processing module, are evenly distributed to each fpga chip according to code stream by Switch；
H.264/H.265, the fpga chip is decoded the bit stream data that comes of distribution, and by decoded data
It carries out CNN reasoning acceleration and retrieval accelerates.
Further, step S3 includes:
After the fpga chip completes CNN reasoning acceleration and retrieval acceleration, MSI interrupt is initiated to Server, Server writes
PCIE accelerator card register in the space MMCFG, FPGA use DMA write operation, after completing CNN reasoning acceleration and retrieval acceleration
Data copy the second memory headroom to from FPGA；
Server is copied the data that CNN reasoning accelerates and retrieves after accelerating are completed or is mapped to from the second memory headroom
First memory headroom of App process；
Accelerator card driving, which is called, to be returned.
The effect provided in summary of the invention is only the effect of embodiment, rather than invents all whole effects, above-mentioned
A technical solution in technical solution have the following advantages that or the utility model has the advantages that
The embodiment of the present invention proposes a kind of acceleration system of multi-channel video encoding and decoding, the system include Camera,
Server and accelerator card.Wherein accelerator card includes BMC control module, chip processing module and power module；BMC control module is used
In out of band supervision management, chip processing module is BMC control module and chip for carrying out multi-channel video encoding and decoding, power module
Processing module power supply.BMC control module includes BMC, house dog, fan, temperature sensor and EEPROM, BMC by UART with
House dog is connected, and BMC also passes through I2C and is connected respectively with fan, temperature sensor and EEPROM.Chip processing module includes 2,3
Or 4 fpga chips, fpga chip is separately connected two DDR4 memory bars, jtag circuit, SPI Flash and EMMC, each
It is interconnected between fpga chip using Chiplink, and fpga chip is connected to Switch.Power module includes electric power adjustment
Device, power regulator connects external+12V power supply, while being connected with BMC control module and chip processing module.Based on the multichannel
A kind of acceleration system of coding and decoding video, it is also proposed that accelerated method of multi-channel video encoding and decoding.The present invention uses fpga chip
It realizes, without using the CPU for having coding and decoding video function, such as the E3 of intel, cooperates the tall and handsome P4 card reached, it is big in cost
Amplitude is reduced.In addition 2,3 or 3 fpga chips are used, the speed of coding and decoding video can be improved according to actual needs.
Fpga chip uses the ZU7EV chip of Xilinx, and each ZU7EV chip can carry out the coding and decoding video on 8 tunnels, 2 FPGA cores
Piece can carry out 16 road coding and decoding videos, and 3 fpga chips can carry out 24 road coding and decoding videos, and 4 fpga chips can be into
32 road coding and decoding video of row, improves the speed of coding and decoding video.
Detailed description of the invention
Fig. 1 is the structure connection signal of accelerator card in a kind of acceleration system of the multi-channel video encoding and decoding of the embodiment of the present invention 1
Figure；
Fig. 2 is 4 fpga chips of accelerator card in the acceleration system based on a kind of multi-channel video encoding and decoding of the embodiment of the present invention 1
Interconnect topological diagram；
Fig. 3 is the overall data process figure of the accelerated method based on a kind of multi-channel video encoding and decoding of the embodiment of the present invention 1.
Specific embodiment
In order to clarify the technical characteristics of the invention, below by specific embodiment, and its attached drawing is combined, to this hair
It is bright to be described in detail.Following disclosure provides many different embodiments or example is used to realize different knots of the invention
Structure.In order to simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relationship between various embodiments and/or setting is discussed.It should be noted that illustrated component is not necessarily to scale in the accompanying drawings
It draws.Present invention omits the descriptions to known assemblies and treatment technology and process to avoid the present invention is unnecessarily limiting.
Embodiment 1
The embodiment of the present invention 1 provides a kind of acceleration system of multi-channel video encoding and decoding, the system include Camera,
Server and accelerator card.
Camera is for providing video data；Server receives video data for connecting, and to accelerator card encoding and decoding number
According to carrying out control management.
It is the structure company of accelerator card in a kind of acceleration system of the multi-channel video encoding and decoding of the embodiment of the present invention 1 as shown in Figure 1
Connect schematic diagram.Accelerator card includes BMC control module, chip processing module and power module；
BMC control module is used for out of band supervision management, and chip processing module is for carrying out multi-channel video encoding and decoding, power supply mould
Block is BMC control module and chip processing module for power supply.
BMC control module includes BMC, house dog, fan, temperature sensor and EEPROM, and BMC passes through UART and house dog
It is connected, BMC also passes through I2C and is connected respectively with fan, temperature sensor and EEPROM.
Chip processing module includes 2,3 or 4 fpga chips, and fpga chip is separately connected two DDR4 memory bars, JTAG
Circuit, SPI Flash and EMMC.The capacity of two of them DDR4 memory bar is 4GB, band ECC, frequency 2400MH.
It is interconnected between each fpga chip using Chiplink.It is based on a kind of multichannel of the embodiment of the present invention 1 as shown in Figure 2
4 fpga chips of accelerator card interconnect topological diagram in the acceleration system of coding and decoding video；The port specification of each fpga chip
Serdes (GTH) x4, walking line rate is 10Gbps.
Fpga chip is connected to Switch by UART.Accelerator card is communicated by PCIE golden finger with Server,
Server server provides the signal of X8, is converted into the signal of 4 X8 to fpga chip by PCIe Switch.
Fpga chip uses the ZU7EV chip of Xilinx, and each ZU7EV chip can carry out the coding and decoding video on 8 tunnels, and 2
A fpga chip can carry out 16 road coding and decoding videos, and 3 fpga chips can carry out 24 road coding and decoding videos, 4 FPGA cores
Piece can carry out 32 road coding and decoding videos.Using 4 fpga chips as explanation in the embodiment of the present invention 1, the model that the present invention protects
It encloses and is not limited to the embodiment 1.
Power module includes power regulator, and power regulator connects external+12V power supply, at the same with BMC control module and
Chip processing module is connected.
Accelerator card further includes programmable clock chip, indicator light key, reset key, test point key and external interface；
Programmable clock chip is for being kept for synchronous clock, display and record time；Programmable clock chip respectively with
ZU7EV0 chip, ZU7EV1 chip, ZU7EV2 chip are connected with ZU7EV3 chip.
Indicator light key, which is used to indicate, accelerates card failure or in place；
Reset key is used to restart in case of constant power when accelerator card breaks down；
The input and output of pin when test point key is tested for fpga chip；
External interface includes USB and HUB.
Accelerator card further includes high-definition digital display interface Display port, high-definition digital display interface Display port
It is connected with ZU7EV0 chip, ZU7EV1 chip, ZU7EV2 chip and ZU7EV3 chip.
A kind of acceleration system based on a kind of multi-channel video encoding and decoding that the embodiment of the present invention 1 proposes, it is also proposed that multichannel
The accelerated method of coding and decoding video.
Before the accelerated method for executing a kind of multi-channel video encoding and decoding, 32 road camera videos compile solution in Camera first
Code data Camera0, Camera1 ... Camera31 passes through the NIP that Switch is sent to Server.
Then, the 32 road cameras that execution execution step S1:Server transmits Camera IP Camera are H.264/
H.265 coded data is sent to the chip processing module in accelerator card；
S2: the 32 road cameras that the chip processing module in accelerator card transmits Camera IP Camera are H.264/
H.265 coded data distributes 8 road bit stream datas according to each fpga chip, and each fpga chip is to the 8 road code stream numbers received
According to be decoded first, then carry out CNN reasoning acceleration and retrieval accelerate；
S3: accelerator card will be sent to Server by each processed bit stream data of fpga chip in chip processing module
In memory.
It is illustrated in figure 3 the overall data stream of the accelerated method based on a kind of multi-channel video encoding and decoding of the embodiment of the present invention 1
Cheng Tu.
The 32 road cameras that NIC transmits Camera IP Camera in process 1:Server H.264/H.265 coded number
According to the first memory headroom of App process in write-in Server memory.
Process 2: calling accelerator card driving, and applies for that the second required memory of accelerator card driving is empty in accelerator card memory
Between, and H.264/H.265 coded data is copied or is mapped in second by 32 road cameras that Camera IP Camera transmits
Deposit space.
Process 3:Server writes the PCIE accelerator card register in the space MMCFG, and FPGA reads Camera network using DMA
32 road cameras of thecamera head H.264/H.265 coded data, and the 32 tunnels camera shooting that Camera IP Camera is transmitted
H.264/H.265 coded data from second space is transported to chip processing module to head, by Switch according to each fpga chip
Distribute 8 road bit stream datas.
H.264/H.265, process 4:FPGA chip is decoded the 8 road bit stream datas that distribution comes.
Decoded data are carried out CNN reasoning acceleration to process 5:FPGA chip and retrieval accelerates.
After process 6:FPGA chip completes CNN reasoning acceleration and retrieval acceleration, MSI interrupt, Server are initiated to Server
The PCIE accelerator card register in the space MMCFG is write, FPGA uses DMA write operation, will complete CNN reasoning and accelerate and retrieve to accelerate
Data afterwards copy the second memory headroom to from fpga chip；
Process 7:Server is copied the data that CNN reasoning accelerates and retrieves after accelerating are completed or is reflected from the second memory headroom
It is mapped to the first memory headroom of App process.
Process 8: accelerator card driving, which is called, to be returned.
Although specification and drawings and examples have been carried out detailed description to the invention, this field skill
Art personnel should be appreciated that and still can be modified or replaced equivalently to the invention；And all do not depart from wound of the present invention
The technical solution and its improvement for the spirit and scope made, are encompassed by the protection scope of the invention patent.
Claims (9)
1. a kind of acceleration system of multi-channel video encoding and decoding, including Camera, Server and accelerator card, which is characterized in that described
Accelerator card includes BMC control module, chip processing module and power module；
The BMC control module includes BMC, house dog, fan, temperature sensor and EEPROM；The BMC passes through UART and sees
Door dog is connected；The BMC is connected with fan, temperature sensor and EEPROM respectively by I2C；
The chip processing module includes 2,3 or 4 fpga chips；The fpga chip be separately connected two DDR4 memory bars,
Jtag circuit, SPI Flash and EMMC；It is interconnected between the fpga chip using Chiplink, and the fpga chip is equal
Switch is connected to by UART；
The power module includes power regulator；The power regulator connects external+12V power supply, while controlling mould with BMC
Block is connected with chip processing module；
The power module is BMC control module and chip processing module for power supply；The BMC control module is used for out-of-band supervision keyholed back plate
Reason；The chip processing module is for carrying out multi-channel video encoding and decoding.
2. a kind of acceleration system of multi-channel video encoding and decoding according to claim 1, which is characterized in that the accelerator card is also
Including programmable clock chip, indicator light key, reset key, test point key and external interface；
The programmable clock chip is for being kept for synchronous clock, display and record time；
The indicator light key, which is used to indicate, accelerates card failure or in place；
The reset key is used to restart in case of constant power when accelerator card breaks down；
The test point key is used for the input and output of the pin in fpga chip test；
The external interface includes USB and HUB.
3. a kind of acceleration system of multi-channel video encoding and decoding according to claim 1, which is characterized in that the fpga chip
Using the ZU7EV chip of Xilinx.
4. a kind of acceleration system of multi-channel video encoding and decoding according to claim 1, which is characterized in that the DDR4 memory
The capacity of item is 4GB.
5. a kind of acceleration system of multi-channel video encoding and decoding according to claim 1, which is characterized in that the fpga chip
Between interconnected using Chiplink, use between the fpga chip port specification of Chiplink interconnection for Serdes x4, institute
It states fpga chip and walks line rate 10Gbps.
6. a kind of accelerated method of multi-channel video encoding and decoding, based on a kind of multi-channel video described in claim 1 to 5 any one
What the acceleration systems of encoding and decoding was realized, which is characterized in that the method the following steps are included:
The H.264/H.265 coded data that S1:Server transmits Camera IP Camera is sent to the chip in accelerator card
Processing module；
S2: the H.264/H.265 coded data that the chip processing module in accelerator card transmits Camera IP Camera according to
Each fpga chip distributes 8 road bit stream datas, and each fpga chip is decoded, so the 8 road bit stream datas received first
CNN reasoning acceleration is carried out afterwards and retrieval accelerates；
S3: accelerator card will be sent to Server memory by each processed bit stream data of fpga chip in chip processing module
In.
7. a kind of accelerated method of multi-channel video encoding and decoding according to claim 6, which is characterized in that step S1 includes:
App in the H.264/H.265 coded data write-in Server memory that NIC transmits Camera IP Camera in Server
First memory headroom of process；
Accelerator card driving is called, and applies for the second required memory headroom of accelerator card driving in accelerator card memory, and will
The H.264/H.265 coded data copy of Camera IP Camera transmission is mapped to the second memory headroom.
8. a kind of accelerated method of multi-channel video encoding and decoding according to claim 6, which is characterized in that step S2 includes:
Server writes the PCIE accelerator card register in the space MMCFG, and FPGA reads the transmission of Camera IP Camera using DMA
H.264/H.265 coded data, by the Camera IP Camera transmission H.264/H.265 coded data from second sky
Between be transported to chip processing module, by Switch according to each fpga chip distribute 8 road bit stream datas；
H.264/H.265, the fpga chip is decoded the 8 road bit stream datas that come of distribution, and by decoded data into
Row CNN reasoning accelerates and retrieval accelerates.
9. a kind of accelerated method of multi-channel video encoding and decoding according to claim 6, which is characterized in that step S3 includes:
After the fpga chip completes CNN reasoning acceleration and retrieval acceleration, MSI interrupt is initiated to Server, Server writes MMCFG
PCIE accelerator card register in space, FPGA use DMA write operation, will complete CNN reasoning and accelerate and retrieve the number after accelerating
The second memory headroom is copied to according to from fpga chip；
The data that Server will complete after CNN reasoning acceleration and retrieval acceleration copy or are mapped to from the second memory headroom described
First memory headroom of App process；
Accelerator card driving, which is called, to be returned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910090918.2A CN109525844B (en) | 2019-01-30 | 2019-01-30 | Acceleration system and method for multi-channel video coding and decoding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910090918.2A CN109525844B (en) | 2019-01-30 | 2019-01-30 | Acceleration system and method for multi-channel video coding and decoding |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109525844A true CN109525844A (en) | 2019-03-26 |
| CN109525844B CN109525844B (en) | 2021-07-27 |
Family
ID=65799779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910090918.2A Active CN109525844B (en) | 2019-01-30 | 2019-01-30 | Acceleration system and method for multi-channel video coding and decoding |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109525844B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111131873A (en) * | 2019-12-26 | 2020-05-08 | 曙光网络科技有限公司 | Server audio and video data processing method and processing device |
| CN112672166A (en) * | 2020-12-24 | 2021-04-16 | 北京睿芯高通量科技有限公司 | Multi-code stream decoding acceleration system and method of video decoder |
| CN112686901A (en) * | 2021-03-11 | 2021-04-20 | 北京小白世纪网络科技有限公司 | US-CT image segmentation method and device based on deep neural network |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020072047A1 (en) * | 1999-12-13 | 2002-06-13 | Michelson Daniel R. | System and method for generating composite video images for karaoke applications |
| EP1797721A1 (en) * | 2004-09-08 | 2007-06-20 | Inlet Technologies, Inc. | Slab-based processing engine for motion video |
| CN101729879A (en) * | 2009-12-15 | 2010-06-09 | 山东大学 | Method for realizing real-time video transmission based on MIMO-OFDM system |
| US20140219361A1 (en) * | 2013-02-01 | 2014-08-07 | Samplify Systems, Inc. | Image data encoding for access by raster and by macroblock |
| CN106210725A (en) * | 2016-08-03 | 2016-12-07 | 广东技术师范学院 | A kind of video image compression perception coder/decoder system and decoding method thereof |
| CN206807656U (en) * | 2017-06-12 | 2017-12-26 | 普讯科技（大连）有限公司 | AV signal processing unit |
| CN208316891U (en) * | 2018-07-03 | 2019-01-01 | 都邑科技（北京）有限公司 | A kind of image processing system |
-
2019
- 2019-01-30 CN CN201910090918.2A patent/CN109525844B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020072047A1 (en) * | 1999-12-13 | 2002-06-13 | Michelson Daniel R. | System and method for generating composite video images for karaoke applications |
| EP1797721A1 (en) * | 2004-09-08 | 2007-06-20 | Inlet Technologies, Inc. | Slab-based processing engine for motion video |
| CN101729879A (en) * | 2009-12-15 | 2010-06-09 | 山东大学 | Method for realizing real-time video transmission based on MIMO-OFDM system |
| US20140219361A1 (en) * | 2013-02-01 | 2014-08-07 | Samplify Systems, Inc. | Image data encoding for access by raster and by macroblock |
| CN106210725A (en) * | 2016-08-03 | 2016-12-07 | 广东技术师范学院 | A kind of video image compression perception coder/decoder system and decoding method thereof |
| CN206807656U (en) * | 2017-06-12 | 2017-12-26 | 普讯科技（大连）有限公司 | AV signal processing unit |
| CN208316891U (en) * | 2018-07-03 | 2019-01-01 | 都邑科技（北京）有限公司 | A kind of image processing system |
Non-Patent Citations (1)
| Title |
|---|
| 吴明美: "基于FPGA的硬件图像处理技术", 《中国优秀硕士论文电子期刊》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111131873A (en) * | 2019-12-26 | 2020-05-08 | 曙光网络科技有限公司 | Server audio and video data processing method and processing device |
| CN112672166A (en) * | 2020-12-24 | 2021-04-16 | 北京睿芯高通量科技有限公司 | Multi-code stream decoding acceleration system and method of video decoder |
| CN112672166B (en) * | 2020-12-24 | 2023-05-05 | 北京睿芯高通量科技有限公司 | Multi-code stream decoding acceleration system and method for video decoder |
| CN112686901A (en) * | 2021-03-11 | 2021-04-20 | 北京小白世纪网络科技有限公司 | US-CT image segmentation method and device based on deep neural network |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109525844B (en) | 2021-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10606787B2 (en) | Methods and apparatuses for providing data received by a state machine engine | |
| CN109525844A (en) | A kind of acceleration system and method for multi-channel video encoding and decoding | |
| CN108268425B (en) | Programmable matrix processing engine | |
| US11016790B2 (en) | Overflow detection and correction in state machine engines | |
| US10831701B2 (en) | Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’) | |
| US10671401B1 (en) | Memory hierarchy to transfer vector data for operators of a directed acyclic graph | |
| CN102566958B (en) | Image segmentation processing device based on SGDMA (scatter gather direct memory access) | |
| CN107003975A (en) | Method and apparatus for controlling link power state | |
| CN110119374A (en) | Application processor, automotive electronics processor and computing device | |
| US20140063183A1 (en) | Method of processing multi-view image and apparatus for executing the same | |
| US11580055B2 (en) | Devices for time division multiplexing of state machine engine signals | |
| CN102547238A (en) | Video cascade system applied in multi-channel DVRs (digital video recorder) and method | |
| CN110166733B (en) | Pre-monitoring method and device, output box, server and splicing system | |
| US9330112B2 (en) | Grouping and compressing similar photos | |
| CN115964333A (en) | Communication method of multi-chip neural network algorithm based on FPGA (field programmable Gate array) master control | |
| US12072730B2 (en) | Synchronization signal generating circuit, chip and synchronization method and device, based on multi-core architecture | |
| CN205249414U (en) | Real -time image compression platform structure of multi -processor framework | |
| WO2021237513A1 (en) | Data compression storage system and method, processor, and computer storage medium | |
| CN104598407A (en) | System on chip and control method | |
| US20140146067A1 (en) | Accessing Configuration and Status Registers for a Configuration Space | |
| CN109213710A (en) | HSSI High-Speed Serial Interface device and its data transmission method | |
| CN107248883B (en) | A kind of real-time monitoring system towards high-throughput load balance hardware | |
| US9223393B2 (en) | Collective operation management in a parallel computer | |
| CN204652526U (en) | A kind of video acquisition memory circuit based on FPGA | |
| Sheng et al. | Implementation of accelerating video preprocessing based on zynq platform resource management |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |