CN109521238A - A kind of decoding, triggering and the analysis system and method for oscillograph platform high-speed bus - Google Patents
A kind of decoding, triggering and the analysis system and method for oscillograph platform high-speed bus Download PDFInfo
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- CN109521238A CN109521238A CN201811330416.4A CN201811330416A CN109521238A CN 109521238 A CN109521238 A CN 109521238A CN 201811330416 A CN201811330416 A CN 201811330416A CN 109521238 A CN109521238 A CN 109521238A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/029—Software therefor
Abstract
The invention discloses decoding, triggering and the analysis system of a kind of oscillograph platform high-speed bus and method, which includes that simulated-bus signal path conditioning module, bus data acquisition module, parameter register, bus data decoder module, memory, bus compare trigger module, triggering address control module, controller and software display waveform control module；The bus data decoder module, memory, bus compare trigger module, triggering address control module and controller and all build in FPGA, system and method disclosed by the invention directly carries out front-end collection to high-speed bus analog signal, substantially increase sample rate, the time of acquisition is set to shorten, the resolution ratio of acquisition time is higher, it is easier to capture interested signal waveform, avoids the acquisition due to caused by sample rate is inadequate and be distorted；The bus message solved is more real-time effectively.
Description
Technical field
The present invention relates to the triggering field of high speed signal, in particular to a kind of decoding of oscillograph platform high-speed bus, touching
Hair and analysis system and method.
Background technique
With the development of modern processors technology, in interconnection technique field, it is total that universal serial bus substitutes parallel bus, high speed
It is trend of the times that line, which replaces low speed bus,.Universal serial bus can be used higher clock frequency, make compared with single-ended parallel signal
With less signal wire, while requiring its rate also higher and higher.High-speed serial bus has reached Gbps or more at present, this is to string
Row bus analysis exploitation debugging has higher requirement.Universal serial bus decoding is that oscillograph to be allowed can be analyzed serially always with triggering
Line, this method are the dedicated trigger mode that oscillograph increases universal serial bus, and the data decoding after triggering is given and is shown
Wave device is shown, improves the development efficiency of bus, is easier to capture interested information.But currently without the string to high-speed bus
Row Decoding Analysis, such as USB2.0, USB3.0, pci bus, PCIe bus etc., this greatly reduces the development efficiency of high-speed bus,
So how fast and accurately to realize that the observation problems demand to high-speed bus transmission data solves.
Existing oscillograph bus triggering and to decode a kind of mode first sampled every time a certain amount of by software realization
Data are placed in memory, by pointer shifting function, realize triggering reconciliation according to serial bus protocol feature and parameter setting
Code process.When reaching pre-trigger depth and meeting triggering requirement, software, which then synchronizes, transfers acquisition waveform and real-time display solution
The label analysed.The maximum disadvantage of software decoding is exactly time-consuming, is easy to miss the interested signal of user.
Another way is realized by hardware, and bus signals are deposited by carrying out sampling into AD behind simulated modulation channel
Storage, by the threshold value comparison of setting, is converted into corresponding low and high level, and bus encoding/decoding module carries out sampling processing again, carries out
The relevant operation of the bus analysis such as decoding triggering.This process has carried out double sampling, and this mode greatly reduces sample rate,
Cause wave distortion, is easier to not acquire accurate data.And requirement of the high-speed bus analysis to sample rate is higher, if sample rate
It is not achieved, it is easier to miss the interested signal of user.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of decoding of oscillograph platform high-speed bus, triggering and dividing
Analysis system and method directly carry out front-end collection to high-speed bus analog signal, substantially increase sample rate, make the time of acquisition
It shortens, the resolution ratio of acquisition time is higher, is easier to capture interested signal waveform, avoids since sample rate not enough causes
Acquisition distortion；With it is traditional can only edging trigger compare, it is easier to capture interested bus waveform.Compared with software decoding
Compared with faster, the bus message solved is more real-time effectively for speed.
In order to achieve the above objectives, technical scheme is as follows:
A kind of decoding, triggering and the analysis system of oscillograph platform high-speed bus, including the conditioning of simulated-bus signal path
Module, bus data acquisition module, parameter register, bus data decoder module, memory, bus compare trigger module, touching
Send out address control module, controller and software display waveform control module；The bus data decoder module, memory, bus
Compare trigger module, triggering address control module and controller all to build in FPGA；
The simulated-bus signal path conditioning module improves high speed bus signals to be measured to bus data acquisition mould
Block is capable of the range of normal acquisition, and bus data acquisition module is enable accurately to acquire measured signal；
Bus data acquisition module is acquired high speed signal with quick sampling rate, and carries out reduction of speed processing；
Parameter register, the related ginseng for storing the relevant parameter of bus encoding/decoding set by user to configuring trigger condition
Number；
Bus data decoder module is decoded and is judged to the bus data of acquisition according to the relevant parameter of setting, root
According to different fields, corresponding tag types are generated, and these labels are sequentially stored into phase according to certain timing and sequence
In corresponding memory, so that rear end is shown；
Bus compares trigger module, the interested field of user field corresponding with decoding can be compared, if
It is consistent then generate corresponding trigger signal, it is sent to triggering address control module；
Trigger address control module, when trigger generate when, generate corresponding triggering address, and this address told soft
Part, software read back, so as to lock trigger position；
Controller controls other modules in FPGA；
Software display waveform control module can be by corresponding storage bus mark according to triggering address and Address count
The length real-time display of the type of label and the field on the screen, different fields is shown using different colors.
In above scheme, in the simulated-bus signal path conditioning module include fixed attenuator, impedance transformer and
Data control gain amplifier.
It include high-speed bus level threshold parameter set by user, bit rate in the parameter register in above scheme
Parameter, decoding parametric and whether contain LCRC check bit.
It include frame field extraction module in the bus data decoder module in above scheme.
In above scheme, it includes additional information comparator, data information comparator and touching that the bus, which compares trigger module,
Send out generation module.
A kind of decoding, triggering and the analysis method of oscillograph platform high-speed bus, using a kind of above-mentioned oscillograph platform
Decoding, triggering and the analysis system of high-speed bus, comprise the following processes:
High speed bus signals are acquired and handle with reduction of speed, subsequently into FPGA after channel improves；User configuration
Decode the relevant parameter of relevant parameter and trigger condition；According to the relevant parameter of setting, the bus data of acquisition is decoded
And judgement, and store；The interested field of user field corresponding with decoding is compared, is generated if consistent corresponding
Trigger signal, and corresponding triggering address is generated, and tell software, software to read back this address, so as to trigger
Position locking；Software is according to triggering address and Address count, by the type of corresponding storage bus label and the field
Length real-time display on the screen, different fields is shown using different colors.
Through the above technical solutions, decoding, triggering and the analysis system of oscillograph platform high-speed bus provided by the invention
And method directly carries out front-end collection to high-speed bus analog signal, substantially increases sample rate, so that the time of acquisition is shortened, adopts
Collect the time resolution ratio it is higher, be easier to capture interested signal waveform, avoid due to sample rate it is inadequate caused by acquisition
Distortion；With it is traditional can only edging trigger compare, it is easier to capture interested bus waveform.Compared with software decoding, speed
Faster, the bus message solved is more real-time effectively for degree.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described.
Fig. 1 is a kind of decoding, triggering and the analysis system of oscillograph platform high-speed bus disclosed in the embodiment of the present invention
Schematic diagram；
Fig. 2 is that state machine disclosed in the embodiment of the present invention jumps schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description.
The present invention provides decoding, triggering and the analysis system of a kind of oscillograph platform high-speed bus and method, this method
Sample rate is high, it is easier to capture interested bus waveform, faster, the bus message solved is more real-time effectively for speed.
Decoding, triggering and the analysis system of a kind of oscillograph platform high-speed bus as shown in Figure 1, including simulated-bus letter
Number channel conditioning module, bus data acquisition module, parameter register, bus data decoder module, memory, bus compare touching
Send out module, triggering address control module, controller and software display waveform control module；Bus data decoder module, memory,
Bus compares trigger module, triggering address control module and controller and all builds in FPGA.
A kind of decoding, triggering and the analysis method of oscillograph platform high-speed bus, comprise the following processes:
High speed bus signals are acquired and handle with reduction of speed, subsequently into FPGA after channel improves；User configuration
Decode the relevant parameter of relevant parameter and trigger condition；According to the relevant parameter of setting, the bus data of acquisition is decoded
And judgement, and store；The interested field of user field corresponding with decoding is compared, is generated if consistent corresponding
Trigger signal, and corresponding triggering address is generated, and tell software, software to read back this address, so as to trigger
Position locking；Software is according to triggering address and Address count, by the type of corresponding storage bus label and the field
Length real-time display on the screen, different fields is shown using different colors.
The present embodiment introduces PCIE bus encoding/decoding, triggering and analysis method by taking PCIE bus protocol as an example as follows:
1, in simulated-bus signal path conditioning module, there is a fixed attenuator, fixed attenuator, which is that one kind is passive, to decline
Subtract network, is the important component part in analog signal conditioner channel.Due in analog channel Data control gain amplifier to signal
Attenuation range is limited, is unable to satisfy the attenuation requirement of big gear, matches therefore, it is necessary to design a set of controllable attenuation network with it
It closes.
2, in simulated-bus signal path conditioning module, there is an impedance transformer, impedance transformer specifically act on be by
Input impedance becomes very high, usually megaohm or more；Output impedance is become very low, usually less than 50 Ω.Its purpose is to
The influence between front stage circuit is isolated, increases the driving capability to rear class.
3, in simulated-bus signal path conditioning module, there are a Data control gain amplifier, Data control gain amplifier difference
In previous voltage control Amplifier, it is made of two parts: digital control module and amplifier section.In newly increasing
Portion's digital control module quantifies amplification factor, and both amplifier section is identical, internal to pass through the biggish fixed increasing of multiple first
Beneficial amplifier amplifies signal, the attenuation network being then made of precision resistance, according to the principle of impedance matching, according to number
The control signal that control module provides switches internal midget relay, accurately decays to signal, finally believed
Number.Data control gain amplifier can be controlled by amplitude of the convenient digital interface to signal, have the very high linearity
With good anti-interference ability, the features such as insertion loss is small.
4, in bus data acquisition module, the differential clocks that AD is sent into FPGA are sent to after IBUFGDS becomes single-ended
Enter MMCM_ADV and carry out scaling down processing, obtains required clock signal.Pass through PSCLK, PSEN, PSINCDEC of MMCM_ADV
Come adjust output clock delay, correctly to be stored to data.
5, it in bus data acquisition module, is handled for convenience of the processing of data using reduction of speed.Due to using height
The data rate that fast AD, AD are sent into FPGA is very high, and FPGA cannot be handled directly, therefore carry out reduction of speed processing.Reduction of speed processing is just
It is the method using space throw-over degree, data bit width is doubled, data speed is reduced to the half of original data.
6, user sets PCIE bus level threshold parameter and is stored in parameter register, the deposit of acquisition module read threshold
Value after digital quantization is generated 0/1 sequence signal compared with threshold parameter and gives snap shot module by device value, if simulated-bus is believed
Number be three level, then be arranged height two threshold parameters, acquisition module generate two 0/1 sequences give snap shot module.
7, user sets PCIE bus bit-rate parameters and is stored in parameter register, and sampling module reads register value,
And according to used sample rate and bus baud rate, sample rate can be N times of bit rate, (N is integer, N=8 of the present invention).
8, whether user's setting PCIE bus contains LCRC check bit and is stored in parameter register, one frame number of PCIE bus
According to check bit can be contained, it is located at postamble.It can also be without this part.According to whether being carried out containing LCRC check bit when decoding
It is correctly decoded.
9, PCIE bus is serial sum, and data are single BIT transmission during transmitting data in physical layer, by sentencing
The format of each field of breaking and type generate different tag types, and format and type include STP field, Sequence word
Section, DataPayload field, LCRC field, END field.
10, PCIE bus encoding/decoding parameter is arranged by software interface in user.The starting of frame is first determined whether in decoder module
Position, bus keeps logic 1 in an idle state.Enter STP field after detecting low level, decoder module generates STP field
Label, and it is stored in storage wherein, in order to which use is compared in software reading display and triggering.
11, after STP field, back to back 15 bytes are Sequence field.If under STATE_L_SAMPLE state
For 7 low levels, STATE_H_SAMPLE continues 12 to 27 high level behind, and decoder module can determine whether that the part is
Sequence field, and the numerical value of the field can be judged by the counter values of high level position.Corresponding label is generated,
And numerical value is stored in together in corresponding memory, in order to which use is compared in software reading display and triggering.
12, in bus data decoder module, carry out that data field is low level adopts under DATA_L_SAMPLE state
Collection, if 8 lasting low levels, passes through high level under DATA_H_SAMPLE state into DATA_H_SAMPLE state
Counter calculates high level duration.And corresponding numerical value is solved by decoding module.Of data field
Number, is determined by number in DataPayload.Each data field can generate corresponding data label, then will count
It is stored in corresponding memory according to label and corresponding numerical value, in order to which use is compared in software reading display and triggering.
13, in bus data decoder module, if in the parameter of input, verifying section comprising LCRC in PCIE bus frame, then
Section decoded state is verified into LCRC, the low level acquisition of CRC check field is carried out under LCRC_L_SAMPLE state, if 8
A lasting low level, into LCRC_H_SAMPLE state, under LCRC_H_SAMPLE state, by high level counter come
Calculate high level duration.And corresponding numerical value is solved by decoding module.LCRC check field can generate phase
Corresponding LCRC verifies label, and LCRC is then verified label and corresponding numerical value is stored in corresponding memory, so as to
Display is read in software and use is compared in triggering.
14, frame field extraction module in bus data decoder module receives adopting for bit information and coding redundancy module
N (N=8) frequency-dividing clock of sample clock carries out frame information extraction to the information between frame end to frame homing sequence, and in frame knot
Sent after beam frame end signal originate to frame/terminate detection sequence, as shown in Fig. 2, frame field extraction module presses following 6 states
Orderly decode the different field information of frame structure:
State 1: idle state, after electrification reset, state machine is in the state, in this state, when receiving acquisition mould
The frame start signal (logical zero) that block is sent to then enters state 2, and otherwise state does not jump；
State 2: after entering state 2, if keeping 15 bytes in this case, it is determined as the STP field of frame, enters
State 3, otherwise state transition to state 1；
State 3:Sequence field status after entering state 3, if keeping 32 bytes in this case, determines
For the Sequence field of frame, into state 4, otherwise state is not jumped；
State 4: data field state, each data field include the data of 8bit, and the number of data field has data minus
The number of load determines.Number is loaded when the value for calculating the counter of data amount check in decoding process is equal to, illustrates number in the frame
It is completed according to the acquisition of section, then enters state 5, otherwise state does not jump；
State 5:LCRC field detecting state, the state include the information of 16 bytes, and the information which is included is used
Verify whether the frame is correct, if the value of the LCRC calculated by acquisition and the value of the LCRC received are inconsistent, illustrates this
Frame changes during transmission, and LCRC error label, display and triggering for software are generated in decoder module
Module.Subsequently into state 6, otherwise state is not jumped；
State 6:END field detecting state, END field indicate the end of the frame data.END word is generated in decoder module
Segment mark label, display and trigger module for software.The field continues 8 bytes.Subsequently into state 1, otherwise state is not
It jumps.
15, bus compares trigger module according to triggering mode parameter set by user is received, and is called not according to trigger parameter
Each frame information that same comparator combination generates decoder module is compared with trigger condition set by user, if eligible
It generates triggering generation logic and generates trigger signal, the triggering mode and comparative approach that user can set to trigger signal generation module
It is as follows:
STP triggering: STP comparator detects that STP field generates triggering；
Sequence triggering: the Sequence that Sequence comparator obtains 15 byte data set by user and decoding
Field information compares generation triggering, if comparator output is logical one, generates trigger signal；
Data bit triggering: when select data-triggered, can choose trigger data length and the data to be triggered, than
Compared with logical relation in can be it is equal, unequal, be greater than, be less than, be more than or equal to, be less than or equal to, in range and outside range.
Data comparator generates triggering from the subsequent data byte of this numerical value for what decoding obtained compared with data word set by user；
LCRC erroneous trigger: the LCRC frame that LCRC comparator obtains check code computing module calculated value and decoder module is believed
Breath compares, if unequal generation erroneous trigger.
END triggering: END pause bit comparator detects that END field generates triggering.
16, address control module is triggered, when triggering generation, generates corresponding triggering address, and this address is told
Software, software read back, so as to lock trigger position.
17, software display waveform control module can be by corresponding storage bus according to triggering address and Address count
The length real-time display of the type of label and the field on the screen, different fields is shown using different colors.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (6)
1. a kind of decoding, triggering and the analysis system of oscillograph platform high-speed bus, which is characterized in that including simulated-bus signal
Channel conditioning module, bus data acquisition module, parameter register, bus data decoder module, memory, bus compare triggering
Module, triggering address control module, controller and software display waveform control module；The bus data decoder module, storage
Device, bus compare trigger module, triggering address control module and controller and all build in FPGA；
The simulated-bus signal path conditioning module improves high speed bus signals to be measured to bus data acquisition module energy
The range of enough normal acquisitions, enables bus data acquisition module accurately to acquire measured signal；
Bus data acquisition module is acquired high speed signal with quick sampling rate, and carries out reduction of speed processing；
Parameter register, for storing the relevant parameter of bus encoding/decoding set by user and configuring the relevant parameter of trigger condition；
Bus data decoder module is decoded and is judged to the bus data of acquisition, according to or not the relevant parameter of setting
With field, generate corresponding tag types, and these labels are sequentially stored into according to certain timing and sequence corresponding
Memory in, so that rear end is shown；
Bus compares trigger module, the interested field of user field corresponding with decoding can be compared, if unanimously
Corresponding trigger signal is then generated, triggering address control module is sent to；
Address control module is triggered, when triggering generation, generates corresponding triggering address, and tell this address to software, it is soft
Part reads back, so as to lock trigger position；
Controller controls other modules in FPGA；
Software display waveform control module can be by corresponding storage bus label according to triggering address and Address count
The length real-time display of type and the field on the screen, different fields is shown using different colors.
2. decoding, triggering and the analysis system of a kind of oscillograph platform high-speed bus according to claim 1, feature exist
In including fixed attenuator, impedance transformer and Data control gain amplifier in the simulated-bus signal path conditioning module.
3. decoding, triggering and the analysis system of a kind of oscillograph platform high-speed bus according to claim 1, feature exist
In, in the parameter register comprising high-speed bus level threshold parameter set by user, bit-rate parameters, decoding parametric, with
And whether contain LCRC check bit.
4. decoding, triggering and the analysis system of a kind of oscillograph platform high-speed bus according to claim 1, feature exist
In comprising frame field extraction module in the bus data decoder module.
5. decoding, triggering and the analysis system of a kind of oscillograph platform high-speed bus according to claim 1, feature exist
In it includes additional information comparator, data information comparator and triggering generation module that the bus, which compares trigger module,.
6. a kind of decoding, triggering and the analysis method of oscillograph platform high-speed bus, using a kind of oscillography described in claim 1
Decoding, triggering and the analysis system of device platform high-speed bus, which is characterized in that comprise the following processes:
High speed bus signals are acquired and handle with reduction of speed, subsequently into FPGA after channel improves；User configuration decoding
The relevant parameter of relevant parameter and trigger condition；According to the relevant parameter of setting, the bus data of acquisition is decoded and sentenced
It is disconnected, and store；The interested field of user field corresponding with decoding is compared, generates corresponding touching if consistent
It signals, and generates corresponding triggering address, and tell software, software to read back this address, so as to by trigger position
Locking；Software is according to triggering address and Address count, by the type of corresponding storage bus label and the length of the field
Real-time display on the screen, different fields is shown using different colors.
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