CN109508263B - Server system and detection method thereof - Google Patents
Server system and detection method thereof Download PDFInfo
- Publication number
- CN109508263B CN109508263B CN201710827162.6A CN201710827162A CN109508263B CN 109508263 B CN109508263 B CN 109508263B CN 201710827162 A CN201710827162 A CN 201710827162A CN 109508263 B CN109508263 B CN 109508263B
- Authority
- CN
- China
- Prior art keywords
- decoder
- unit
- code
- code symbol
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Programmable Controllers (AREA)
- Stored Programmes (AREA)
Abstract
The invention provides a server system and a detection method thereof, which are applied by matching with a detection module. The detection module comprises a decoder and a code symbol display. The server system comprises a logic programmable unit and a switching controller. The logic programmable unit transmits an operation code generated by each section of operation program sequentially executed in a power-on sequence instruction to the decoder, and the decoder decodes the operation code sequentially to enable the code symbol display to display corresponding code symbols sequentially. When the logic programmable unit executes a certain section of operation program of the power-on sequence instruction and cannot successfully finish execution, the execution of the power-on sequence instruction is stopped, and at the moment, the code symbol display displays the code symbol of the processing code corresponding to the interrupted operation program executed by the logic programmable unit at the moment, so that the problem of the section of operation program executed by the logic programmable unit can be known, the time is effectively saved, and the efficiency is improved.
Description
Technical Field
The present invention relates to a server, and more particularly, to a server system and a detection method thereof.
Background
In recent years, Complex Programmable Logic Devices (CPLDs) are widely used and play an important role in a server system, and generally, when the server system is powered on, the CPLDs execute internal program instructions (CPLDs) to power on and start and control a motherboard and hardware elements, and when the CPLDs execute the program instructions, the Complex Programmable Logic elements perform subsequent power-on operations.
Therefore, the server system is detected before leaving the factory, if the complex programmable logic element executes a certain section of program in the program instruction and cannot complete execution, the state or signal of the corresponding main board or hardware element in the section of program is problematic, the complex programmable logic element stops working and causes the server system to crash (Hang up), and a detector can confirm and maintain the problem, so as to ensure the quality stability of the server system. Generally, a server system has a plurality of power-on programs, and when an error occurs in the power-on process of the server system, a motherboard or a hardware element in the server system cannot be powered on smoothly, which may result in a failure in powering on smoothly, however, a tester cannot know which stage of the power-on and powering on the server system has the error, so that the tester must manually measure data such as voltage/current/waveform of the motherboard or the hardware element in each program in the power-on program one by one to determine which program in the power-on program has a problem, and perform subsequent processing actions, which causes a problem that the tester needs to measure related status signals one by one in a time and labor consuming manner, and then can determine an actual problem, which is time consuming and greatly needs to be discussed and improved.
Disclosure of Invention
The invention aims to provide a server system detection method which saves time and improves detection efficiency.
In order to solve the above technical problems, the server system detection method of the present invention is applied to a detection module for detecting a server system. The server system comprises a mainboard, a processing unit, a plurality of hardware units, a logical programming unit and a switching controller. The detection module comprises a decoder connected with the switching controller and a code symbol display. The server system detection method comprises a step (A), a step (B), a step (C), a step (D) and a step (E).
In the step (a), when the server system is powered on, the switch controller is connected to the logic programmable unit and connects the logic programmable unit to the decoder, and the logic programmable unit executes a multi-stage operation program of a power-on sequence instruction and controls to power on the motherboard, the processing unit and the hardware unit.
In the step (B), the logically programmable unit sequentially transmits an operation code generated by each of the sequentially executed operation programs to the decoder, and the decoder sequentially decodes the operation code to sequentially display the corresponding code symbol on the code symbol display.
In step (C), during the execution of the power-on timing command by the logically programmable unit, the logically programmable unit continuously determines whether the executed power-on timing command is interrupted.
In the step (D), if the determination in the step (C) is negative, after the logically programmable unit executes the operation procedure of the power-on sequence instruction, the switching controller is controlled to switch to connect to the processing unit, so that the processing unit is connected to the decoder.
In the step (E), the processing unit executes a plurality of stages of processing procedures of a basic input/output instruction and sequentially transmits a processing code generated by each of the sequentially executed stages of processing procedures to the decoder, and the decoder sequentially decodes the processing code and sequentially displays the corresponding code symbol on the code symbol display.
Another technical problem to be solved by the present invention is to provide a server system that saves time and improves detection efficiency.
To solve the above technical problem, the server system of the present invention is used in conjunction with a detection module to detect applications. The detection module comprises a detection board, a decoder arranged on the detection board and a code symbol display arranged on the detection board and connected with the decoder.
The server system comprises a mainboard, a processing unit arranged on the mainboard, a plurality of hardware units arranged on the mainboard and controlled by the processing unit, a logic programmable unit arranged on the mainboard, and a switching controller of a decoder connecting the logic programmable unit and the detection module. The switching controller can be controlled by the logic programmable unit to switch and connect to the processing unit, so that the processing unit is connected to the decoder.
When the server system is started and powered on, the switching controller is connected to the logic programmable unit and enables the logic programmable unit to be connected to the decoder, the logic programmable unit executes a multi-section operation program of a power-on sequence instruction and controls the mainboard, the processing unit and the hardware unit to be powered on, and the logic programmable unit sequentially transmits an operation code generated by each section of operation program which is sequentially executed to the decoder. The decoder decodes the operation codes in sequence to enable the code symbol display to display corresponding code symbols in sequence, and when the logical programming unit executes the power-on sequence instruction to be interrupted, the code symbol display displays the code symbols corresponding to the operation codes generated by the operation program executed by the logical programming unit at present. When the logic programmable unit finishes executing the operation program of the power-on sequence instruction and controls the switching controller to switch and connect to the processing unit, the processing unit is connected to the decoder, the processing unit executes a plurality of sections of processing programs of a basic input and output instruction and sequentially transmits a processing code generated by each section of processing program to the decoder, and the decoder sequentially decodes the processing code to sequentially display the corresponding code symbol on the code symbol display.
Compared with the prior art, the server system detection method of the invention has the advantages that the switching controller is connected to the logic programmable unit and the logic programmable unit is connected to the decoder, and the decoder is matched to decode the operation code in sequence to make the code symbol display the corresponding code symbol in sequence, when the process of executing the power-on time sequence command by the logic programmable unit is interrupted, the code symbol display displays the code symbol corresponding to the operation code generated by the operation program executed by the logic programming unit at present, so that a user can know which operation program in the power-on sequence instruction is executed by the logic programming unit through the code symbol displayed by the code symbol display, the user can quickly perform subsequent adjustment and maintenance operation, the time is effectively saved, and the detection efficiency is improved.
[ description of the drawings ]
FIG. 1 is a block diagram illustrating an embodiment of a server system according to the present invention.
FIG. 2 is a flowchart illustrating an embodiment of a server system detection method according to the present invention.
[ detailed description ] embodiments
Referring to fig. 1 and fig. 2, the present invention provides a server system, which is used in conjunction with a detection module 5 for detection, wherein the detection module 5 includes a detection board 51, a decoder 52 disposed on the detection board 51, and a code symbol display 53 disposed on the detection board 51 and connected to the decoder 52. The server system includes a main board 1, a processing unit 2 disposed on the main board 1, a plurality of hardware units (not shown) disposed on the main board 1 and controlled by the processing unit 2, a logical programming unit 3 disposed on the main board 1, a switching controller 4 disposed on the main board 1 and connecting the logical programming unit 3 and a decoder 52 of the detecting module 5, and a detecting module 5 connected to the main board 1. The switching controller 4 can be controlled by the logic programmable unit 3 to switch the connection to the processing unit 2, so that the processing unit 2 is connected to the decoder 52.
When the server system is powered on, the switch controller 4 is connected to the logic programmable unit 3 and connects the logic programmable unit 3 to the decoder 52, and the logic programmable unit 3 executes a multi-stage operation program of a power-on sequence instruction and controls to power on the motherboard 1, the processing unit 2 and the hardware units. The logically programmable unit 3 sequentially transmits an operation code generated by each of the sequentially executed operation programs to the decoder 52. The decoder 52 decodes the operation codes in sequence to make the code symbol display 53 display the corresponding code symbols in sequence, and when the logical programming unit 3 stops executing the power-on sequence command, the code symbol display 53 displays the code symbols corresponding to the operation codes generated by the operation program executed by the logical programming unit 3 at the moment. In the present embodiment, the switch controller 4 is connected to the logical programming unit 3 at a predetermined position, so that the logical programming unit 3 is connected to the decoder 52 every time the server system is powered on. The operation program of the power-on timing sequence instruction is a program CODE pattern (CPLD CODE) inside the Programmable Logic Device (CPLD) 3, so that the Programmable Logic Device 3 executes the power-on timing sequence instruction to sequentially execute the operation program and sequentially display corresponding CODE symbols through the CODE symbol display 53, that is, in this embodiment, the Programmable Logic Device 3 sequentially executes each section of operation program to generate corresponding operation CODEs, and the CODE symbol display 53 sequentially displays the CODE symbols corresponding to each operation CODE, but not limited thereto.
Specifically, when the server system is powered on, the logically programmable unit 3 sequentially executes each operation program (CPLD CODE) in the power-on sequence command, and when each operation program executed by the logically programmable unit 3 generates its corresponding operation CODE, the decoder 52 sequentially decodes the operation CODE, so that the CODE symbol display 53 sequentially displays the corresponding CODE symbols. When the logic programmable unit 3 interrupts executing the power-on sequence instruction, that is, the logic programmable unit 3 interrupts executing the power-on sequence instruction due to an error in the process of executing the power-on sequence instruction, which means that a certain operation program currently executing the power-on sequence instruction cannot be successfully completed, the logic programmable unit 3 stops executing the power-on sequence instruction. Therefore, when an error occurs in the operation program of a certain section in the power-on sequence command executed by the logic programming unit 3, the operation of the operation program of the other subsequent section is stopped, and at this time, the code symbol displayed by the code symbol display 53 is the code symbol corresponding to the operation code generated by the operation program that cannot be successfully executed by the logic programming unit 3. Therefore, the user can know which operation procedure of the power-on sequence command the logic programmable unit 3 has a problem when executing through the code symbol displayed by the code symbol display 53, and can quickly perform subsequent adjustment and maintenance operations, thereby effectively saving time and improving detection efficiency.
Then, when the logically programmable unit 3 finishes executing the operation procedure of the power-on sequence instruction and controls the switching controller 4 to switch to connect to the processing unit 2, the processing unit 2 is connected to the decoder 52, and the processing unit 2 executes a plurality of stages of processing procedures of a basic input/output instruction and sequentially transmits a processing code generated by each stage of processing procedure executed sequentially to the decoder 52, and the decoder 52 sequentially decodes the processing code to sequentially display the corresponding code symbol on the code symbol display 53. In the embodiment, the basic input/output instruction (BIOS) is stored in a memory 21 connected to the processing unit 2, and the processing program of the BIOS is a program CODE pattern (BIOS CODE), so that the processing unit 2(CPU) executes the BIOS sequentially to execute the processing program, and the processing unit 2 generates the corresponding processing CODE when executing each processing program sequentially, and sequentially displays the CODE symbol corresponding to each processing CODE through the CODE symbol display 53. In other words, the logically programmable unit 3 finishes executing the operation procedure of the power-on sequence instruction, and the logically programmable unit 3 controls the switching controller 4 to switch to connect to the processing unit 2 and connect the processing unit 2 to the decoder 52, then the processing unit 2 executes the processing procedure of the bios and sequentially transfers the processing codes to the decoder 52, and the decoder 52 sequentially decodes the processing codes to sequentially display the corresponding code symbols on the code symbol display 53, if the processing unit 2 has an error in executing the bios, it represents that a certain processing procedure currently executing the bios cannot be successfully executed, and the processing unit 2 stops executing the bios, at this time, the code symbol displayed on the code symbol display 53 is the processing procedure that the processing unit 2 cannot be successfully executed at present The user can quickly know which processing program in the basic input/output instruction has a problem when the processing unit 2 executes, thereby effectively saving time. In the present embodiment, the code symbol display 53 is a seven-segment display, but not limited thereto, and it should be particularly noted that the code symbol display 53 has a two-code symbol display lamp 531 and two status indicator lamps 532. The status indicator lights 532 of the code symbol display 53 are illuminated when the switching controller 4 is connected to the logically programmable unit 3 and the logically programmable unit 3 is connected to the decoder 52; the switching controller 4 is connected to the processing unit 2 in a switching manner and connects the processing unit 2 to the decoder 52, and the status indicator 532 of the CODE symbol display 53 does not emit light, so that the user can know that a problem occurs in the stage of executing the power-on sequence command (CPLD CODE) by the logically programmable unit 3 or the stage of executing the basic input/output command (BIOS CODE) by the processing unit 2 by judging whether the status indicator 532 of the CODE symbol display 53 is lighted or not, and further know which operation program of the power-on sequence command (CPLD CODE) or which processing program of the basic input/output command (BIOS CODE) has a problem through the CODE symbol displayed by the CODE symbol display 531, so as to perform subsequent adjustment and maintenance operation, save time and labor, and improve the detection efficiency. Furthermore, by the design that the switching controller 4 can be connected to the logic programmable unit 3 and the logic programmable unit 3 is connected to the decoder 52 and can be switched to the processing unit 2 and the processing unit 2 is connected to the decoder 52, the application that the decoder 52 displays the corresponding code symbols sequentially through the code symbol display 53 can be matched, which not only effectively improves the tedious actions that 3 needs to be manually measured and detected one by one in the prior power-on timing sequence test process, but also the design that the logic programmable unit 3 and the processing unit 2 are switched and connected through the switching controller 4 does not need to separately connect the logic programmable unit 3 and the processing unit 2 to the decoder 52 of the detection module 5 through physical circuits respectively, and the code symbol display lamp 531 and the status indicator lamp 532 of the code symbol display 53 are matched, it is convenient for the user to determine whether the logic programmable unit 3 executes the power-on sequence command or the processing unit 2 executes the basic input/output command, and it is not necessary to prepare different detection modules 5 for different testing stages, and only one detection module 5 is needed.
Referring to fig. 1 and fig. 2, the server system detection method of the present invention is applied to the detection module 5 for detecting the server system. The server system detection method comprises a step (A), a step (B), a step (C), a step (D), a step (E) and a step (F).
First, in the step (a), when the server system is powered on, the switch controller 4 is connected to the logic programmable unit 3 and connects the logic programmable unit 3 to the decoder 52, and the logic programmable unit 3 executes a multi-stage operation program of a power-on sequence instruction and controls to power on the motherboard 1, the processing unit 2 and the hardware units. In short, when the server system is powered on, the logical programming unit 3 sequentially executes each operating program (CPLD CODE) in the power-on sequence instruction. In the embodiment, the operation procedure of the power-on sequence command is a program CODE pattern (CPLD CODE) inside the programmable logic unit 3(CPLD), and the predetermined location of the switch controller 4 is connected to the programmable logic unit 3 to connect the programmable logic unit 3 to the decoder 52, so that the programmable logic unit 3 is connected to the decoder 52 through the switch controller 4 each time the server system is powered on. The logic programmable unit 3 has a control pin 31, the switching controller 4 has a receiving pin 41 connected to the control pin 31, when the server system is powered on, the logic programmable unit 3 transmits a light signal from the control pin 31 to the decoder 52 via the receiving pin 41 of the switching controller 4, and the decoder 52 decodes the light signal to make the status indicator 532 of the code symbol display 53 emit light. In this embodiment, the control PIN 31 communicates with the receiving PIN 41 in a GPIO (general Purpose input/output) transmission manner, and the lighting signal causes the decoder 52 to raise a PIN Voltage level (PIN Voltage level) of a PIN corresponding to the status indicator 532, so as to cause the status indicator 532 to emit light, but not limited thereto.
Then, in the step (B), the logically programmable unit 3 sequentially transmits the operation codes generated by each of the sequentially executed operation procedures to the decoder 52, and the decoder 52 sequentially decodes the operation codes to sequentially display the corresponding code symbols on the code symbol display 53. In this embodiment, the logic programmable unit 3 executes the power-on sequence command to sequentially execute the operation programs and sequentially display the corresponding CODE symbols through the CODE symbol display 53, in this embodiment, each of the operation programs (CPLD CODE) has an output CODE program, when the logic programmable unit 3 sequentially executes the output CODE program of each of the operation programs, the corresponding operation CODEs are generated and sequentially transmitted to the decoder 52, and the decoder 52 sequentially decodes the operation CODEs and sequentially displays the CODE symbols corresponding to each of the operation CODEs on the CODE symbol display 53, but not limited thereto. That is, each operating program (CPLD CODE) has its corresponding operating CODE, so when the output CODE program of each operating program (CPLD CODE) is executed by the logical programming unit 3, the operating CODE corresponding to each operating program will be generated. In this embodiment, the design that the CPLD CODE (CPLD CODE) is built in the logical programming unit 3 and each segment of the operation program has a corresponding output CODE program allows the logical programming unit 3 to execute the output CODE program of each segment of the operation program to generate a corresponding operation CODE, and cooperate with the decoder 52 to decode the operation CODE to sequentially display the CODE symbol corresponding to each segment of the operation program on the CODE symbol display 53.
Then, in the step (C), during the execution of the power-on timing command by the logical programming unit 3, the logical programming unit 3 continuously determines whether the executed power-on timing command is interrupted. And in the step (F), if the determination in the step (C) is yes, the logically programmable unit 3 stops executing the power-on sequence instruction, at this time, the code symbol display 53 displays the code symbol of the operation code corresponding to the operation program executed by the logically programmable unit 3 currently. In other words, when the logically programmable unit 3 executes the power-on sequence instruction, that is, when the logically programmable unit 3 has an error in executing the power-on sequence instruction, it means that a certain operation program currently executing the power-on sequence instruction cannot be successfully executed, at this time, the logically programmable unit 3 determines that the executed power-on sequence instruction is the case of executing the interrupt. In addition, since the logical programming unit 3 executes the operation programs in sequence and displays the code symbols of the corresponding operation codes in sequence through the code symbol display 53, when an error occurs in one operation program in the power-on sequence command of the logical programming unit 3, the execution of the operation programs of other subsequent sections is stopped, at this time, the code symbol displayed by the code symbol display 53 is the code symbol corresponding to the operation code generated by the operation program which cannot be successfully executed by the logical programming unit 3, so that a user can quickly know which operation program in the power-on sequence command the logical programming unit 3 has a problem, and time is effectively saved.
Next, in the step (D), if the determination in the step (C) is negative, after the logically programmable unit 3 executes the operation procedure of completing the power-on sequence instruction, the switching controller 4 is controlled to switch to connect to the processing unit 2, so that the processing unit 2 is connected to the decoder 52. Finally, in the step (E), the processing unit 2 executes the multiple sections of the processing programs of the basic input/output instruction and sequentially transmits the processing codes corresponding to each of the sequentially executed processing programs to the decoder 52, and the decoder 52 sequentially decodes the processing codes and sequentially displays the corresponding code symbols on the code symbol display 53. In this embodiment, the logic programmable unit 3 controls the switching controller 4 to switch to the processing unit 2 by communicating with the receiving pin 41 of the switching controller 4 through the control pin 31 in a GPIO manner and switches the switching controller 4 to connect to the processing unit 2, so that the processing unit 2 is connected to the decoder 52, at this time, the logic programmable unit 3 synchronously transmits a dim signal through the control pin 31 to the decoder 52 through the receiving pin 41 of the switching controller 4, and the decoder 52 decodes the dim signal to make the status indicator 532 of the code symbol display 53 not emit light, but not limited thereto. The dim signal is to make the decoder 52 pull down the Voltage level (PIN Voltage level) of the PIN corresponding to the status indicator 532 to make the status indicator 532 not to emit light, but not limited to this, the processing program of the basic input/output instruction is a program CODE (BIOS CODE), so that the processing unit 2(CPU) executes the basic input/output instruction sequentially and displays the corresponding CODE symbols sequentially through the CODE symbol display 53. That is, the logic programmable unit 3 finishes executing the operation procedure of the power-on sequence command, and the logic programmable unit 3 controls the switching controller 4 to switch to connect to the processing unit 2 and connect the processing unit 2 to the decoder 52, and then the processing unit 2 executes the processing procedure of the bios command and sequentially transmits the processing codes to the decoder 52, and the decoder 52 sequentially decodes the processing codes to sequentially display the corresponding code symbols on the code symbol display 53. Additionally, if the processing unit 2 has an error during the execution of the bios instruction, it indicates that a certain processing program currently executing the bios instruction cannot be successfully executed, and the processing unit 2 stops executing the bios instruction, at this time, the code symbol displayed by the code symbol display 53 is the code symbol of the processing code corresponding to the processing program that the processing unit 2 cannot be successfully executed at present, so that the user can know which processing program in the bios instruction the processing unit 2 has executed has a problem, thereby effectively saving time.
In summary, the server system and the detection method thereof of the present invention use the switch controller 4 to connect to the logic programmable unit 3, connect the logic programmable unit 3 to the decoder 52, and cooperate with the decoder 52 to decode the operation codes in sequence to make the code symbol display 53 display the corresponding code symbols in sequence. When the logic programmable unit 3 interrupts the power-on sequence command, the code symbol display 53 will display the code symbol corresponding to the operation code generated by the operation program executed by the logic programmable unit 3, so as to know which operation program in the power-on sequence command the logic programmable unit 3 has a problem in executing, and perform the subsequent processing operation quickly, saving time and improving efficiency, thereby achieving the purpose of the present invention.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A detection method of a server system is applied to a detection module to detect a server system, and is characterized in that: the server system comprises a mainboard, a processing unit, a plurality of hardware units, a logical programming unit and a switching controller, the detection module comprises a decoder connected with the switching controller and a code symbol display, and the detection method of the server system comprises the following steps:
(A) when the server system is powered on, the switching controller is connected to the logic programmable unit and enables the logic programmable unit to be connected to the decoder, and the logic programmable unit executes a multi-stage operation program of a power-on sequence instruction and controls the mainboard, the processing unit and the hardware unit to be powered on;
(B) the logic programming unit transmits an operation code generated by each section of operation program which is executed in sequence to the decoder in sequence, and the decoder decodes the operation code in sequence to enable the code symbol display to display corresponding code symbols in sequence;
(C) during the process that the logic programmable unit executes the power-on time sequence instruction, the logic programmable unit continuously judges whether the executed power-on time sequence instruction executes interruption;
(D) if the step (C) is no, after the logical programmable unit executes the operation procedure of the power-on sequence command, controlling the switching controller to switch to connect to the processing unit, so that the processing unit is connected to the decoder;
(E) the processing unit executes a plurality of sections of processing programs of a basic input and output instruction and sequentially transmits a processing code generated by each section of processing program to the decoder, and the decoder sequentially decodes the processing code and enables the code symbol display to sequentially display corresponding code symbols; and
a step (F) following the step (C), wherein in the step (F), if the step (C) determines that the power-on sequence command is executed, the code symbol display displays a code symbol corresponding to an operation code generated by an operation program currently executed by the logic programmable unit.
2. The server system detection method according to claim 1, wherein: the code symbol display has two code symbol display lamps and two status indicator lamps, when the server system is powered on in the step (A), the logic programmable unit is connected to the decoder, the logic programmable unit transmits a light-up signal to the decoder through the switching controller, and the decoder decodes the light-up signal to make the status indicator lamps of the code symbol display emit light.
3. The server system detection method according to claim 2, wherein: the logic programmable unit has a control pin, the switching controller has a receiving pin connected with the control pin, in the step (A), when the logic programmable unit is connected with the decoder, the logic programmable unit transmits the light-up signal to the decoder through the receiving pin of the switching controller by the control pin, and the decoder decodes the light-up signal to make the state indicator light of the code symbol display illuminate, and in the step (D), when the logic programmable unit finishes the operation procedure of the power-up sequence instruction, the logic programmable unit transmits a switching signal to the receiving pin of the switching controller by the control pin to control the switching controller to switch and connect to the processing unit and make the processing unit connect to the decoder.
4. The server system detection method according to claim 3, wherein: in the step (D), the logic programmable unit transmits a switching signal to the receiving pin of the switching controller via the control pin, and controls the switching controller to switch and connect to the processing unit, and connects the processing unit to the decoder, at this time, the logic programmable unit synchronously transmits a dim light signal to the decoder via the receiving pin of the switching controller via the control pin, and the decoder decodes the dim light signal to make the status indicator light of the code symbol display not emit light.
5. The server system detection method according to claim 1, wherein: in the step (B), when the logic programmable unit sequentially executes the output code programs of each section of operation program, the logic programmable unit sequentially generates the operation codes corresponding to each section of operation program and sequentially transmits the operation codes to the decoder, and the decoder sequentially decodes the operation codes to enable the code symbol display to sequentially display corresponding code symbols.
6. The server system detection method according to claim 2, wherein: the logic programmable unit controls the switching controller to switch and connect to the decoder in a general input output transmission mode.
7. A server system, characterized by: in combination with a detection module detection application, the detection module comprises a detection board, a decoder arranged on the detection board, and a code symbol display arranged on the detection board and connected with the decoder, the server system comprises: a main board; a processing unit disposed on the motherboard; a plurality of hardware units arranged on the mainboard and controlled by the processing unit; a logic programming unit arranged on the mainboard; and a switching controller disposed on the motherboard and connected to the decoder of the logic programming unit and the detection module, wherein the switching controller is controlled by the logic programming unit to switch and connect to the processing unit to connect the processing unit to the decoder, when the server system is powered on, the switching controller is connected to the logic programming unit and connects the logic programming unit to the decoder, the logic programming unit executes a multi-stage operation program of a power-on sequence instruction and controls the power-on of the motherboard, the processing unit and the hardware unit, the logic programming unit sequentially transmits an operation code generated by each stage of operation program to the decoder, the decoder sequentially decodes the operation code to sequentially display corresponding code symbols on the code symbol display, and when the logic programming unit executes the power-on sequence instruction, at this time, the code symbol display displays the code symbol corresponding to the operation code generated by the operation program executed by the logic programmable unit, when the logic programmable unit finishes executing the operation program of the power-on sequence instruction and controls the switching controller to switch and connect to the processing unit, the processing unit is connected to the decoder, the processing unit executes a plurality of sections of processing programs of a basic input and output instruction and sequentially transmits a processing code generated by each section of processing program to the decoder, and the decoder sequentially decodes the processing code to sequentially display the corresponding code symbol on the code symbol display.
8. The server system according to claim 7, wherein: the code symbol display has two code symbol display lights and two status indicator lights, the status indicator lights of the code symbol display being illuminated when the switching controller is coupled to the logically programmable unit and the logically programmable unit is coupled to the decoder.
9. The server system according to claim 8, wherein: the logic programmable unit has a control pin, the switching controller has a receiving pin connected with the control pin, when the logic programmable unit is connected with the decoder, the logic programmable unit transmits a light-up signal to the decoder through the receiving pin of the switching controller by the control pin, and the decoder decodes the light-up signal to make the state indicator light of the code symbol display illuminate, when the logic programmable unit finishes the operation procedure of the power-up time sequence instruction, the logic programmable unit transmits a switching signal to the receiving pin of the switching controller by the control pin to control the switching controller to switch and connect to the processing unit, and the processing unit is connected to the processing unit, so that the processing unit is connected to the decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710827162.6A CN109508263B (en) | 2017-09-14 | 2017-09-14 | Server system and detection method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710827162.6A CN109508263B (en) | 2017-09-14 | 2017-09-14 | Server system and detection method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109508263A CN109508263A (en) | 2019-03-22 |
| CN109508263B true CN109508263B (en) | 2022-05-27 |
Family
ID=65744807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710827162.6A Active CN109508263B (en) | 2017-09-14 | 2017-09-14 | Server system and detection method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109508263B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110579733A (en) * | 2019-09-25 | 2019-12-17 | 苏州浪潮智能科技有限公司 | indicator lamp health detection device and use method thereof |
| CN113760612A (en) * | 2020-06-05 | 2021-12-07 | 佛山市顺德区顺达电脑厂有限公司 | Server debugging method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5305473B2 (en) * | 2010-11-26 | 2013-10-02 | Ｎｅｃインフロンティア株式会社 | Error code output device and error code output method |
| TW201227271A (en) * | 2010-12-22 | 2012-07-01 | Inventec Corp | A monitor system of the mother board in the POST |
| TWI489232B (en) * | 2012-11-14 | 2015-06-21 | Inst Information Industry | Remote monitoring systems and related methods and recording mediums thereof |
| CN104182314A (en) * | 2014-08-25 | 2014-12-03 | 浪潮集团有限公司 | Dragon core processor server motherboard maintaining method |
| TWI599876B (en) * | 2014-10-09 | 2017-09-21 | 緯創資通股份有限公司 | Methods for debugging in a post (power-on self-test) and apparatuses using the same |
| CN105160255A (en) * | 2015-08-06 | 2015-12-16 | 浪潮电子信息产业股份有限公司 | Trustworthy measurement apparatus and method |
-
2017
- 2017-09-14 CN CN201710827162.6A patent/CN109508263B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109508263A (en) | 2019-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7312605B2 (en) | AC power supply testing module and method for booting a main board | |
| US20090100287A1 (en) | Monitoring Apparatus and a Monitoring Method Thereof | |
| CN109508263B (en) | Server system and detection method thereof | |
| TWI528285B (en) | Manufacturing system and firmware burning method | |
| EP2750034A2 (en) | Electronic device having updatable bios and bios updating method thereof | |
| CN107589568B (en) | Automatic learning and detecting device and method for LED lamp string | |
| CN112654119B (en) | LED drive test method, driver, system and electronic equipment | |
| US8250409B2 (en) | Boot test apparatus and method of computer system | |
| CN106980569B (en) | Method for representing BIOS POST progress by USB keyboard lamp | |
| TW201527965A (en) | System and method for detecting a BIOS test process of a computer | |
| TW201310229A (en) | BIOS testing tool and method of using the same | |
| US7714604B2 (en) | System and method for testing an operating condition of LEDs on a motherboard | |
| CN107122276B (en) | Operation state output circuit and operation state output method | |
| US5923886A (en) | Automatic memory space switching method | |
| US20140164815A1 (en) | Server analyzing system | |
| CN112285597B (en) | Short circuit detection method and device for display panel | |
| CN111694302B (en) | IO module detection device and method and building control system | |
| TW202018507A (en) | A host boot detection method and its system | |
| GB2582402A (en) | Information processing system and relay device | |
| JP2002043071A (en) | Control system for illumination lamp | |
| CN1287252C (en) | Re-starting card and method for determining test moment of re-starting mechanism | |
| CN215987289U (en) | Abnormal display device for server equipment | |
| CN109947621A (en) | A kind of method and device of server test | |
| CN111324495B (en) | Host machine starting-up detection method and system thereof | |
| TWI726434B (en) | Control method for solving abnormal operation of me |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |