CN109507559A - A kind of test method and test device of silicon chip minority carrier life - Google Patents

A kind of test method and test device of silicon chip minority carrier life Download PDF

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Publication number
CN109507559A
CN109507559A CN201710833597.1A CN201710833597A CN109507559A CN 109507559 A CN109507559 A CN 109507559A CN 201710833597 A CN201710833597 A CN 201710833597A CN 109507559 A CN109507559 A CN 109507559A
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etching groove
silicon wafer
solution
test
minority carrier
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赵向阳
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Zing Semiconductor Corp
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Zing Semiconductor Corp
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Priority to CN201710833597.1A priority Critical patent/CN109507559A/en
Priority to TW106145180A priority patent/TWI657518B/en
Publication of CN109507559A publication Critical patent/CN109507559A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The present invention provides the test method and test device of a kind of silicon chip minority carrier life, which comprises provides silicon wafer to be tested；The silicon wafer is immersed in HF solution；The minority carrier life time of the silicon wafer in the HF solution is immersed in test.The test method and test device of silicon chip minority carrier life provided by the invention can reduce influence of the surface recombination to silicon chip minority carrier life test result.

Description

A kind of test method and test device of silicon chip minority carrier life
Technical field
The present invention relates to technical field of semiconductors, in particular to the test method and test of a kind of silicon chip minority carrier life Device.
Background technique
In the semiconductor element, although MOS element is mainly by majority carrier (more sons) control, minority carrier is (few Son) service life also function to important function, such as higher minority carrier life time helps to reduce the refresh time (refresh of DRAM time).Therefore, minority carrier life time is one of the important indicator for determining silicon crystal perfection.In addition, in crystal itself or warp The microdefect that generates can all have a certain impact to minority carrier life time after crossing processing, and current minority carrier lifetime equipment has and draws The function of (mapping) is made, therefore minority carrier life time plays a very important role for the improvement of crystal growing technology.
There are many method of test silicon wafer minority carrier life time at present, such as the method for photoconductivity decay measurement, surface photovoltaic method etc., wherein Since microwave photoconductive decay method (μ-PCD) easy to operate and measuring accuracy meets testing requirements, and become the few son of test silicon wafer The mainstream test method in service life.In μ-PCD method, the minority carrier life time of final test is actually the useful life of entire sample, It is the net result occurred in silicon chip surface, internal all complex superpositions, and the true body life time of silicon wafer, needs to utilize in order to obtain The influence of passivating method reduction surface recombination.
Therefore, it is necessary to the test method and test device of a kind of silicon chip minority carrier life be proposed, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of test method of silicon chip minority carrier life, which comprises Silicon wafer to be tested is provided；The silicon wafer is immersed in HF solution；Few son of the silicon wafer in the HF solution is immersed in test Service life.
Illustratively, the concentration of the HF solution is 1%-49%.
Illustratively, method used by the test is microwave photoconductive decay method.
It illustratively, include: that the quarter with etching groove top cover is provided by the step that the silicon wafer immerses in the HF solution Lose slot；Decline the etching groove；The silicon wafer is placed in the silicon wafer on the etching groove top cover to place in slot position；Described in rising Etching groove, until the etching groove is in contact with the etching groove top cover；HF solution is passed through into the etching groove, so that described Silicon wafer immerses in the HF solution.
Illustratively, after the step of minority carrier life time of the silicon wafer in the HF solution is immersed in test, further includes: H is passed through into the etching groove2O, to clean the silicon wafer and the etching groove.
Illustratively, after the step of minority carrier life time of the silicon wafer in the HF solution is immersed in test, further includes: Decline the etching groove again, and takes out the silicon wafer.
The present invention also provides a kind of test devices of silicon chip minority carrier life, comprising: for holding the etching groove of HF solution, institute Stating etching groove can move up and down；Etching groove top cover above the etching groove, etching groove top cover lower part, which is provided with, puts The silicon wafer for setting silicon wafer places slot position；And the detector above the etching groove top cover.
Illustratively, the screw rod of the etching trench bottom is driven to realize moving up and down for the etching groove by motor.
Illustratively, the two sides of the etching groove are respectively arranged with HF import and water inlet, and the bottom of the etching groove is set It is equipped with waste liquid row's mouth.
Illustratively, the material of the etching groove and the etching groove top cover includes tetrafluoroethylene-perfluoro alkoxy vinyl Base ether copolymer and/or polytetrafluoroethylene (PTFE).
The test method and test device of silicon chip minority carrier life provided by the invention, it is few to silicon wafer to can reduce surface recombination The influence of sub- life test result.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the process flow chart of the test method of the silicon chip minority carrier life of one embodiment of the invention offer.
Fig. 2A-Fig. 2 G be the step of successively implementation according to the method for one embodiment of the invention in test device schematic diagram.
Fig. 3 shows the schematic diagram of the test device of the silicon chip minority carrier life of one embodiment of the invention offer.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/ Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation, The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram as desirable embodiment (and intermediate structure) of the invention Bright embodiment.As a result, it is contemplated that from the variation of shown shape as caused by such as manufacturing technology and/or tolerance.Therefore, The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape Shape deviation.For example, being shown as the injection region of rectangle usually has round or bending features and/or implantation concentration ladder at its edge Degree, rather than binary from injection region to non-injection regions changes.Equally, which can lead to by the disposal area that injection is formed Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic , their shape is not intended the true form in the area of display device and is not intended to limit the scope of the invention.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, to illustrate proposition of the present invention Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with With other embodiments.
Minority carrier life time is one of the important indicator for being used to determine silicon wafer perfection.The side of test silicon wafer minority carrier life time at present There are many method, such as the method for photoconductivity decay measurement, surface photovoltaic method etc., wherein since microwave photoconductive decay method (μ-PCD) operates letter List and measuring accuracy meet testing requirements, and become the mainstream test method of test silicon wafer minority carrier life time.μ-PCD method the test That obtain is the test service life τ of samplemeas, silicon wafer 200 really body minority carrier life time τ itself can be corrected by following formulabulk:
1/τmeas=1/ τbulk+1/(τdiff+τsurf)
Wherein τdiffThe time required to being diffused into out of silicon wafer 200 body surface for few son, the thickness of it and silicon wafer and carrier Diffusion coefficient is related；τsurfFor the surface lifetime due to the compound generation of sample surfaces, the thickness and recombination velocity of it and silicon wafer Sr is related.τsurfHave a significant impact to the test service life, causes a deviation from body life time τbulk.In order to reduce the influence of surface recombination, need Processing is passivated to silicon wafer, reduces recombination velocity Sr.Traditional HF/HNO3/CH3The silicon chip surface of COOH nitration mixture etching is compound Speed is about Sr ≈ 105Cm/s, the silicon chip surface recombination velocity of oxidation processes are about Sr ≈ 20cm/s, immerse the silicon wafer of tincture of iodine essence Surface recombination velocity (S.R.V.) is about Sr ≈ 4cm/s, is unable to meet demand.
In view of the above-mentioned problems, the present invention provides a kind of test method of silicon chip minority carrier life, comprising: provide silicon to be tested Piece；The silicon wafer is immersed in HF solution；The minority carrier life time of the silicon wafer in the HF solution is immersed in test.
The concentration of the HF solution is 1%-49%.
Method used by the test is microwave photoconductive decay method.
It include: that the etching groove with etching groove top cover is provided by the step that the silicon wafer immerses in the HF solution；Decline The etching groove；The silicon wafer is placed in the silicon wafer on the etching groove top cover to place in slot position；Rise the etching groove, directly It is in contact to the etching groove with the etching groove top cover；HF solution is passed through into the etching groove, so that the silicon wafer immerses In the HF solution.
After the step of minority carrier life time of the silicon wafer in the HF solution is immersed in test, further includes: to the quarter H is passed through in erosion slot2O, to clean the silicon wafer and the etching groove.
After the step of minority carrier life time of the silicon wafer in the HF solution is immersed in test, further includes: decline again The etching groove, and take out the silicon wafer.
The present invention also provides a kind of test devices of silicon chip minority carrier life, comprising: for holding the etching groove of HF solution, institute Stating etching groove can move up and down；Etching groove top cover above the etching groove, etching groove top cover lower part, which is provided with, puts The silicon wafer for setting silicon wafer places slot position；And the detector above the etching groove top cover.
The screw rod of the etching trench bottom is driven to realize moving up and down for the etching groove by motor.
The two sides of the etching groove are respectively arranged with HF import and water inlet, and the bottom of the etching groove is provided with waste liquid row Mouthful.
The material of the etching groove and the etching groove top cover includes tetrafluoroethylene-perfluoro alkoxy vinyl ethers copolymer And/or polytetrafluoroethylene (PTFE).
The test method and test device of silicon chip minority carrier life provided by the invention, it is few to silicon wafer to can reduce surface recombination The influence of sub- life test result.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to illustrate this Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair It is bright to have other embodiments.[exemplary embodiment one]
Below with reference to Fig. 1 and Fig. 2A~Fig. 2 G, to the test side of the silicon chip minority carrier life of an embodiment of the present invention Method is described in detail.
Firstly, executing step 101, silicon wafer 200 to be tested is provided.The material of the silicon wafer 200 includes polysilicon or list Crystal silicon；Its conduction type can be p-type, or N-shaped；Its specific form can be bulk crystals silicon, can also be flake crystalline Body silicon.The silicon wafer 200 can be surface-treated first, to remove the dirt and oxide layer on its surface.Wherein, dirt is gone Except there are many modes, in order to improve removal efficiency, ultrasonic cleaning and chemical reagent cleaning can be selected.When using ultrasonic cleaning, Since the dirt of silicon chip surface is generally grease stain, silicon slice under test can be put into organic solvent and be cleaned by ultrasonic.When useization When learning reagent cleaning, the reagent with oxidation corrosion effect, such as the mixed liquor of the concentrated sulfuric acid and hydrogen peroxide can be used.In addition, The dirt on other modes removal 200 surface of silicon wafer, such as mechanical grinding can be used.Then can also by the immersion of chemical reagent come Remove removing oxide layer.
Then, step 102 is executed, the silicon wafer 200 is immersed in hydrofluoric acid (HF) solution.As an example, can first by The silicon wafer 200 is placed in etching groove, then HF solution is passed through into the etching groove, so that the silicon wafer immerses HF solution In.
Specifically, firstly, as shown in Figure 2 A, providing the etching groove 201 with etching groove top cover 202.The wherein etching Slot 201 can move up and down, and the silicon wafer placement slot position for placing the silicon wafer 200 is provided on the etching groove top cover 202.The quarter Erosion slot 201 is for holding HF, the PFA (tetrafluoroethylene-perfluoro alkoxy vinyl ethers copolymer) of the resistance to HF of material selection or poly- Tetrafluoroethene material.Then, decline etching groove 201.It can drive the screw rod of 201 bottom of etching groove come under by motor 207 The etching groove 201 drops.Then, as shown in Figure 2 B, the silicon wafer 200 silicon wafer on etching groove top cover 202 is placed in place In slot position.Biography piece can be carried out by wafer-handling robot.Then, as shown in Figure 2 C, rise etching groove 201, until etching groove 201 Top touches etching groove top cover 202, is placed in the silicon wafer 200 inside etching groove 201.
Then, as shown in Figure 2 D, HF solution is passed through into etching groove 201.
Specifically, the HF solution can be passed through into etching groove 201 by being set to the HF import 204 of etching groove side, HF solution is contacted to avoid operator.As an example, the concentration of the HF solution be 1%-49%, for example, 49%.One In a embodiment, the concentration of the HF solution is 2%.In another embodiment, the concentration of the HF solution is 25%.It is described HF solution makes 200 surface passivation of silicon wafer, reduces surface recombination.
Then, step 103 is executed, minority carrier lifetime is carried out to the silicon wafer 200 immersed in the HF solution.
In the present embodiment, the minority carrier life time of the silicon wafer is tested using RF-MW Photonics decaying (μ-PCD) method.Its Used test device is illustrated as being located at the detector 203 of 202 top of etching groove top cover.The RF-MW Photonics damped method is main It is injected including laser and generates electron-hole pair and microwave sounding signal the two processes.Illustratively, use wavelength for 904nm Laser carry out injection generate electron-hole pair so that silicon wafer conductivity increase, injection depth be about 30 μm.It is outer when removing When boundary's light injects, exponential damping, this trend reflect the attenuation trend of minority carrier indirectly, pass through microwave conductivity at any time The trend that detection conductivity changes over time can be obtained by the service life of minority carrier.What the μ-PCD method was tested is The test service life τ of samplemeas, silicon wafer 200 really body minority carrier life time τ itself can be corrected by following formulabulk:
1/τmeas=1/ τbulk+1/(τdiff+τsurf)
Wherein τdiffThe time required to being diffused into surface out of silicon wafer 200 body for few son, the thickness and carrier of it and silicon wafer 200 Diffusion coefficient it is related；τsurfFor the surface lifetime due to the compound generation of sample surfaces, the thickness of it and silicon wafer 200 and in conjunction with Speed Sr is related.Silicon wafer 200 is passivated using HF solution in the present invention, immerses the silicon wafer 200 surface recombination speed of HF solution Spending Sr is about 0.25cm/s, much smaller than the Sr of other reagents, to reduce surface recombination effect, reduces test service life τmeas With body minority carrier life time τbulkBetween deviation.
Then, as shown in Figure 2 E, the etching groove 201 and the silicon wafer 200 are cleaned.Specifically, by with HF import 204 Opposite water inlet 205 injects deionized water (DIW) into etching groove 201, cleans to silicon wafer 200 and etching groove 201.It is useless Acid can arrange mouth 206 by the spent acid of 201 bottom of etching groove and be discharged.HF import 204, the setting of water inlet 205 and spent acid row's mouth 206 It can avoid operator and contact HF solution, improve safety.
Then, the silicon wafer 200 is taken out.
Specifically, firstly, as shown in Figure 2 F, declining etching groove 201.201 bottom of etching groove can be driven by motor 207 Screw rod declines the etching groove 201.Then, as shown in Figure 2 G, placed from silicon wafer and remove the silicon wafer 200 in slot position.
So far, the introduction of the correlation step of the test method of the silicon chip minority carrier life of the embodiment of the present invention is completed.It can be with Understand, the test method of the present embodiment not only includes above-mentioned steps, before above-mentioned steps, among or may also include later Other desired step, is included in the range of present implementation.
The test method of silicon chip minority carrier life provided by the invention can reduce surface recombination and test silicon chip minority carrier life As a result influence.
[exemplary embodiment two]
Below with reference to Fig. 3, the test device of the silicon chip minority carrier life of an embodiment of the present invention is described in detail.Institute Test device is stated for realizing above-mentioned test method.
As shown, the test device includes: the etching groove 301 for holding HF solution, the etching groove 301 can on Lower movement；And the etching groove top cover 302 above the etching groove 301,302 lower part of etching groove top cover, which is provided with, puts The silicon wafer for setting silicon wafer 300 places slot position, and the test device further includes the detector positioned at 302 top of etching groove top cover 303。
In one embodiment, the screw rod of 301 bottom of etching groove is driven to realize the etching groove by motor 307 301 move up and down.
In one embodiment, the two sides of the etching groove 301 are respectively arranged with HF import 304 and water inlet 305, described The bottom of etching groove 301 is provided with waste liquid row's mouth 306.HF import 304, the setting of water inlet 305 and spent acid row's mouth 306 can avoid Operator contacts HF solution, improves safety.
In one embodiment, the material of the etching groove 301 and the etching groove top cover 302 includes the tetrafluoro second of resistance to HF Alkene-perfluorinated alkoxy vinyl ether copolymer (PFA) and/or polytetrafluoroethylene (PTFE).
The test device of silicon chip minority carrier life provided by the invention can reduce surface recombination and test silicon chip minority carrier life As a result influence.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (10)

1. a kind of test method of silicon chip minority carrier life, which is characterized in that the described method includes:
Silicon wafer to be tested is provided；
The silicon wafer is immersed in HF solution；
The minority carrier life time of the silicon wafer in the HF solution is immersed in test.
2. the method according to claim 1, wherein the concentration of the HF solution is 1%-49%.
3. the method according to claim 1, wherein method used by the test is microwave photoconductive decay Method.
4. the method according to claim 1, wherein the silicon wafer is immersed the step packet in the HF solution It includes:
The etching groove for having etching groove top cover is provided；
Decline the etching groove；
The silicon wafer is placed in the silicon wafer on the etching groove top cover to place in slot position；
Rise the etching groove, until the etching groove is in contact with the etching groove top cover；
HF solution is passed through into the etching groove, so that the silicon wafer immerses in the HF solution.
5. according to the method described in claim 4, it is characterized in that, testing lacking for the silicon wafer immersed in the HF solution After the step of sub- service life, further includes: be passed through H in Xiang Suoshu etching groove2O, to clean the silicon wafer and the etching groove.
6. according to the method described in claim 4, it is characterized in that, testing lacking for the silicon wafer immersed in the HF solution After the step of sub- service life, further includes: decline the etching groove again, and take out the silicon wafer.
7. a kind of test device of silicon chip minority carrier life characterized by comprising
For holding the etching groove of HF solution, the etching groove can be moved up and down；
Etching groove top cover above the etching groove, etching groove top cover lower part are provided with the silicon wafer placement for placing silicon wafer Slot position；And
Detector above the etching groove top cover.
8. device according to claim 7, which is characterized in that drive the screw rod of the etching trench bottom come real by motor The existing etching groove moves up and down.
9. device according to claim 7, which is characterized in that the two sides of the etching groove are respectively arranged with HF import and water Import, the bottom of the etching groove are provided with waste liquid row's mouth.
10. device according to claim 7, which is characterized in that the material packet of the etching groove and the etching groove top cover Include tetrafluoroethylene-perfluoro alkoxy vinyl ethers copolymer and/or polytetrafluoroethylene (PTFE).
CN201710833597.1A 2017-09-15 2017-09-15 A kind of test method and test device of silicon chip minority carrier life Pending CN109507559A (en)

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TW106145180A TWI657518B (en) 2017-09-15 2017-12-22 A lifetime testing method of minority carriers in silicon wafer, and a testing apparatus

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111398774A (en) * 2020-03-18 2020-07-10 西安奕斯伟硅片技术有限公司 Method and device for testing minority carrier lifetime of silicon wafer

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7249395B1 (en) * 2021-11-10 2023-03-30 株式会社Sumco Semiconductor sample evaluation method, semiconductor sample evaluation device, and semiconductor wafer manufacturing method
CN114509450A (en) * 2021-12-29 2022-05-17 西安奕斯伟材料科技有限公司 Device and method for representing efficiency of gettering metal impurities of silicon wafer by means of minority carrier lifetime

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162694A (en) * 2007-11-16 2008-04-16 中国科学院电工研究所 Chemical passivation method for measuring minority carrier lifetime of crystalline silicon
CN101592469A (en) * 2009-07-08 2009-12-02 中电电气（南京）光伏有限公司 Silicon chip of solar cell damage layer thickness and minority carrier life time measuring method and device
CN102364322A (en) * 2011-06-30 2012-02-29 常州天合光能有限公司 Surface treatment method for testing minority carrier lifetime of silicon wafer
CN102735510A (en) * 2012-06-20 2012-10-17 常州天合光能有限公司 Passivation method for measuring N-type silicon chip minority carrier life
CN102856432A (en) * 2012-08-12 2013-01-02 安阳市凤凰光伏科技有限公司 Surface passivation method of silicon chip
CN104359737A (en) * 2014-11-21 2015-02-18 中国科学院宁波材料技术与工程研究所 Testing method of bulk minority carrier lifetime of crystalline silicon
CN206301761U (en) * 2016-12-12 2017-07-04 河北大学 The atmosphere control device of silicon chip minority carrier life test
CN107154351A (en) * 2016-03-03 2017-09-12 中国科学院微电子研究所 Silicon wafer polishing method and device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980700680A (en) * 1995-10-17 1998-03-30 도미노 후꾸미 Semiconductor Treatment Apparatus
DE102007027111B4 (en) * 2006-10-04 2011-12-08 Siltronic Ag Silicon wafer with good intrinsic gettering capability and process for its preparation
JP5024865B2 (en) * 2007-02-26 2012-09-12 独立行政法人 宇宙航空研究開発機構 Semiconductor substrate evaluation method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162694A (en) * 2007-11-16 2008-04-16 中国科学院电工研究所 Chemical passivation method for measuring minority carrier lifetime of crystalline silicon
CN101592469A (en) * 2009-07-08 2009-12-02 中电电气（南京）光伏有限公司 Silicon chip of solar cell damage layer thickness and minority carrier life time measuring method and device
CN102364322A (en) * 2011-06-30 2012-02-29 常州天合光能有限公司 Surface treatment method for testing minority carrier lifetime of silicon wafer
CN102735510A (en) * 2012-06-20 2012-10-17 常州天合光能有限公司 Passivation method for measuring N-type silicon chip minority carrier life
CN102856432A (en) * 2012-08-12 2013-01-02 安阳市凤凰光伏科技有限公司 Surface passivation method of silicon chip
CN104359737A (en) * 2014-11-21 2015-02-18 中国科学院宁波材料技术与工程研究所 Testing method of bulk minority carrier lifetime of crystalline silicon
CN107154351A (en) * 2016-03-03 2017-09-12 中国科学院微电子研究所 Silicon wafer polishing method and device
CN206301761U (en) * 2016-12-12 2017-07-04 河北大学 The atmosphere control device of silicon chip minority carrier life test

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111398774A (en) * 2020-03-18 2020-07-10 西安奕斯伟硅片技术有限公司 Method and device for testing minority carrier lifetime of silicon wafer
CN111398774B (en) * 2020-03-18 2022-02-15 西安奕斯伟材料科技有限公司 Method and device for testing minority carrier lifetime of silicon wafer

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