CN109494228B - Nonvolatile memory with multi-bit storage function and preparation method thereof - Google Patents
Nonvolatile memory with multi-bit storage function and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to the field of non-volatile storage,the nonvolatile memory provided by the invention is of a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode; the ferroelectric gate dielectric layer with the three-layer composite structure sequentially comprises a ferroelectric film, an ultrathin insulating layer 1 and an ultrathin insulating layer 2; the ferroelectric film is made of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer or vinylidene fluoride-trifluoroethylene-chloroethylene copolymer. The erasing voltage of the nonvolatile memory with the multi-bit storage function is less than 40V, and the field effect mobility is more than 0.5cm2/Vs。
Description
Technical Field
The invention relates to the field of nonvolatile storage, in particular to a nonvolatile memory with a multi-bit storage function and a preparation method thereof.
Background
As a carrier for information storage, memory is a dominant position in the current information industry. The memory is classified into volatile and nonvolatile memory according to whether the stored information can be stored for a long time. There are various classifications of memory depending on the device structure and the storage mechanism. Among them, the organic transistor nonvolatile memory has the advantages of a memory cell with a single transistor structure, non-destructive reading of stored information, nonvolatile storage of information, flexible application, low-temperature preparation, solution-soluble processing, low cost and the like, so that the organic transistor nonvolatile memory is expected to become a new-generation nonvolatile memory technology, and is also considered to be a new-generation nonvolatile memory by more and more international research institutes and great companies. The organic transistor nonvolatile memory has wide application advantages in the fields of nonvolatile information storage, integrated circuits, flat panel displays, various wearable electronics and the like, and a research trend is raised globally in recent years.
The organic transistor nonvolatile memory refers to a memory device having an organic transistor structure fabricated based on an organic semiconductor as an active layer. According to the memory scheme, organic transistor nonvolatile memories include two major types, ferroelectric and floating gate. The ferroelectric organic transistor nonvolatile memory adopts ferroelectric materials as gate dielectric layers, and after the operation of erasing voltages with different polarities, the arrangement of dipoles inside the ferroelectric gate dielectric layers changes to generate different polarization states; and the polarization state can be maintained permanently after the external voltage is removed, different source-drain currents are induced and respectively correspond to logic '1' and '0' states, and therefore the nonvolatile information storage function is achieved. The floating gate type organic transistor nonvolatile memory adopts a gate dielectric layer with a floating gate structure; under a write voltage operation, charge is stored in the floating gate medium; under the operation of the erasing voltage, the charges stored in the floating gate medium are discharged; different source-drain currents are generated due to different quantities or polarities of charges stored in the floating gate medium and respectively correspond to logic '1' and '0' states; the ability to store charge in the floating gate medium for long periods of time results in a non-volatile information storage function for the organic transistor.
In recent years, reports of organic transistor nonvolatile memories have been increasing year by year. However, most of the reported organic transistor nonvolatile memories have only 1-bit memory function, that is: only two storage states, logic 0 and 1, are available. There are few reports on organic transistor non-volatile memories with multi-bit storage functions (e.g., 2-bit storage, i.e., having four memory states of logic 00, 01, 10, 11 on a single memory cell). In 2012, c.park et al in korea obtained ferroelectric organic transistor nonvolatile memory with multi-bit memory function by using ferroelectric polymer polyvinylidene fluoride-trifluoroethylene as gate dielectric layer [ adv.mater. (2012)24,5910](ii) a Chenwenchang et al, Taiwan, China, used a variety of polymeric electrets as charge-trapping media [ macromolecules. Rapid Commun. (2014)35,1039](ii) a Kim et al, korea, two-dimensional semiconductor MoS2Nanoflakes as charge trapping media [ nanoscales. (2014)6,12315](ii) a Tran et al, c.m. japan, use metal lithium ion encapsulated fullerenes as charge trapping media [ org.electron. (2017)45,234]Floating gate type organic transistor nonvolatile memories having a multi-bit memory function are obtained, respectively. However, these reported organic transistor nonvolatile memories having multi-bit memory function generally require high erasing voltage (80-200V), which is not suitable for practical use. Therefore, it is a prerequisite to significantly reduce the erase/write voltage of the organic transistor nonvolatile memory having the multi-bit memory function to a reasonable level to enable the practical and industrial production thereof.
The erasing voltage of the ferroelectric organic transistor nonvolatile memory depends to a large extent on the curie field of the ferroelectric material as the ferroelectric gate dielectric layer. Currently, the reported ferroelectric organic transistor memory generally uses the ferroelectric polymer polyvinylidene fluoride-trifluoroethylene as the gate dielectric layer, and the high curie field (up to 55 v/micron) of the ferroelectric organic transistor memory results in the need of high erasing voltage (more than 50 v) of the ferroelectric organic transistor memory, which prevents the industrial application of the ferroelectric organic transistor memory. In addition, in order to obtain a single electrically erasable multi-bit memory function and increase the operating speed of the memory, the organic transistor nonvolatile memory must have a field effect mobility large enough to obtain different levels of channel currents with controllable erasing voltages and distinct levels, and a fast erasing speed. However, in most of the reported ferroelectric organic transistor nonvolatile memories, due to the dipole effect of the ferroelectric domain micro-region of the ferroelectric gate dielectric layer, the transmission of carriers in the channel is affected, so that the field effect mobility is too low.
At present, no organic transistor nonvolatile memory with multi-bit storage function, which can work under a lower erasing voltage and has large field effect mobility, exists.
Disclosure of Invention
The invention provides a nonvolatile memory with a multi-bit storage function and a preparation method thereof. The erasing voltage of the nonvolatile memory with the multi-bit storage function is less than 40V, and the field effect mobility is more than 0.5cm2/Vs。
The invention provides a nonvolatile memory with a multi-bit storage function, which is of a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode; the ferroelectric gate dielectric layer with the three-layer composite structure sequentially comprises a ferroelectric film, an ultrathin insulating layer 1 and an ultrathin insulating layer 2, wherein the ultrathin insulating layer 2 is in contact with the organic semiconductor layer; the ferroelectric film is made of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer or vinylidene fluoride-trifluoroethylene-chloroethylene copolymer.
Preferably, the material of the ultrathin insulating layer 1 comprises one or more of alumina, zirconia, silica and poly (4-vinylphenol); the material of the ultrathin insulating layer 2 comprises one or more of polymethyl methacrylate, polystyrene, polyimide, polyvinyl alcohol and polyvinylpyrrolidone.
Preferably, the thickness of the ferroelectric thin film is 100-1000 nm, and the thickness of the ultrathin insulating layers 1 and 2 is independently 1-50 nm.
Preferably, the substrate is made of one or more of glass, silicon, polyethylene terephthalate, polymethyl methacrylate, polyethylene naphthalate, polyimide, polyether sulfone and paper.
Preferably, the materials of the gate electrode and the source-drain electrodes independently include one or more of indium tin oxide, silver, gold, copper, aluminum, graphene, carbon nanotubes and poly (3, 4-ethylenedioxythiophene).
Preferably, the organic semiconductor layer comprises a small molecule organic semiconductor layer or a polymer organic semiconductor layer.
Preferably, the material of the small molecule organic semiconductor layer comprises pentacene, copper phthalocyanine, zinc phthalocyanine, copper perfluorophthalocyanine, carbon 60, 6, 13-bis (triisopropylsilylethynyl) pentacene, 2, 7-bis-octyl [1] benzothieno [3,2-b ] [1] benzothiophene or 2, 9-didecylnaphtho [2,3-b: 2', 3' -F ] thieno [3,2-b ] thiophene.
Preferably, the material of the polymer organic semiconductor layer comprises poly (3-hexylthiophene-2, 5-diyl) and { [ N, n ' -bis (2-octyldodecanol) naphthalene-1, 4,5, 8-bis- (dicarboximide) -2, 6-diyl ] -5,5' - (2,2' -bithiophene) } copolymer or poly {2,2' - [2, 5-bis (2-octyldodecyl) -3, 6-dioxo-2, 3,5, 6-tetrahydropyrrolo [3,4-c ] pyrrol-1, 4-diyl ] dithiophene-5, 5' -diyl-alt-thieno [3,2-b ] thiophene-2, 5-diyl }.
Preferably, the thickness of the organic semiconductor layer is 20-100 nm.
The invention also provides a preparation method of the nonvolatile memory in the technical scheme, which comprises the following steps:
and sequentially preparing a gate electrode, a ferroelectric film, an ultrathin insulating layer 1, an ultrathin insulating layer 2, an organic semiconductor layer and a source-drain electrode on the surface of the substrate by adopting a vapor deposition or spin coating method to obtain the nonvolatile memory.
The invention provides a nonvolatile memory with a multi-bit storage function, which is of a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode; the ferroelectric gate dielectric layer with the three-layer composite structure sequentially comprises a ferroelectric film, an ultrathin insulating layer 1 and an ultrathin insulating layer 2; the ultrathin insulating layer 2 is in contact with the organic semiconductor layer; the ferroelectric film is made of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer or vinylidene fluoride-trifluoroethylene-chloroethylene copolymer.
The non-volatile memory with the multi-bit storage function provided by the invention has the advantages that the ferroelectric film is prepared by the ferroelectric polymer with the low Curie electric field, the Curie voltage required by the polarization reversal of the ferroelectric film is directly reduced, and the erasing voltage of the memory is obviously reduced. Experimental results show that the erasing voltage of the nonvolatile memory provided by the invention is not higher than 40V and is obviously lower than the erasing voltage of 80-200V required by similar memories in the prior art.
In addition, the ultrathin insulating layer 1 can smooth the polycrystalline surface of the ferroelectric film, improve the surface trap of the ferroelectric film, reduce the loss of ferroelectric polarization accumulated charges, improve the surface energy of the ferroelectric film and enhance the adhesiveness of the ultrathin insulating layer 2; meanwhile, the ultrathin insulating layer 2 can improve the surface energy of the ultrathin insulating layer 1, improve the film appearance and the microstructure quality of the organic semiconductor, improve the interface trap between the ultrathin insulating layer 2 and the organic semiconductor layer, and further remarkably improve the field effect mobility of the memory. Experimental results show that the field effect mobility of the nonvolatile memory provided by the invention is greater than 0.5cm2The Vs is obviously higher than that of most similar memories by 0.001-0.1 cm2the/Vs lays a foundation for the memory to have a multi-bit storage function and improve other performance parameters of the memory.
In the invention, the dielectric constants of the ultrathin insulating layers 1 and 2 are different, and when the applied gate voltage is changed, the three-layer composite ferroelectric gate dielectric layer formed by combining the ultrathin insulating layers 1 and 2 and the ferroelectric film can change the voltage values distributed on the ferroelectric film, so that the ferroelectric film can obtain different degrees of polarization, accumulate different charge densities, and produce different degrees of modulation on channel current, thereby obtaining the multi-bit storage characteristic; the combination of the ultrathin insulating layer 1 and the ultrathin insulating layer 2 can also prevent the loss of charges accumulated by the polarization of the ferroelectric thin film, so that the working reliability and stability of the memory can be improved.
Drawings
FIG. 1 is a schematic structural diagram of a non-volatile memory with multi-bit storage function according to the present invention;
fig. 2 is a current-voltage transfer curve of a nonvolatile memory with a multi-bit storage function in different gate voltage scanning ranges according to embodiment 1 of the present invention;
FIG. 3 is a graph showing the erase/write cycle operation of the non-volatile memory with multi-bit storage according to embodiment 1 of the present invention;
fig. 4 shows charge storage and retention characteristics of a nonvolatile memory having a multi-bit storage function according to embodiment 1 of the present invention.
Detailed Description
The invention provides a nonvolatile memory with a multi-bit storage function, which is of a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode; the ferroelectric gate dielectric layer with the three-layer composite structure sequentially comprises a ferroelectric film, an ultrathin insulating layer 1 and an ultrathin insulating layer 2, wherein the ultrathin insulating layer 2 is in contact with the organic semiconductor layer; the ferroelectric film is made of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer or vinylidene fluoride-trifluoroethylene-chloroethylene copolymer.
The non-volatile memory provided by the invention preferably has a 2-bit storage characteristic. In the present invention, the structure of the nonvolatile memory is shown in fig. 1, where 1 is a substrate, 2 is a gate electrode, 3 is a ferroelectric thin film, 4 is an ultra-thin insulating layer 1, 5 is an ultra-thin insulating layer 2,6 is an organic semiconductor layer, and 7 is a source-drain electrode. As can be seen from fig. 1, the structure of the nonvolatile memory provided by the present invention sequentially includes a substrate, a gate electrode, a ferroelectric thin film, an ultra-thin insulating layer 1, an ultra-thin insulating layer 2, an organic semiconductor layer, and source-drain electrodes.
In the present invention, all the substances are commercially available.
The invention provides a nonvolatile memory which comprises a substrate. In the present invention, the material of the substrate preferably includes one or more of glass, silicon, polyethylene terephthalate, polymethyl methacrylate, polyethylene naphthalate, polyimide, polyether sulfone, and paper.
The nonvolatile memory provided by the invention comprises a gate electrode. In the present invention, the material of the gate electrode preferably includes one or more of indium tin oxide, silver, gold, copper, aluminum, graphene, carbon nanotube, and poly (3, 4-ethylenedioxythiophene). In the present invention, the thickness of the gate electrode is preferably 30 to 100nm, and more preferably 40 to 80 nm.
The nonvolatile memory provided by the invention comprises a ferroelectric gate dielectric layer with a three-layer composite structure. In the invention, the ferroelectric gate dielectric layer with the three-layer composite structure sequentially comprises a ferroelectric film, an ultrathin insulating layer 1 and an ultrathin insulating layer 2, wherein the ultrathin insulating layer 2 is in contact with the organic semiconductor layer. In the invention, the material of the ferroelectric film comprises vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer or vinylidene fluoride-trifluoroethylene-chloroethylene copolymer. In the present invention, the thickness of the ferroelectric thin film is preferably 100 to 1000nm, more preferably 200 to 900nm, more preferably 400 to 800nm, and still more preferably 500 to 700 nm. The ferroelectric film is designed into the substance with the low Curie electric field, so that the Curie voltage required by polarization reversal of the ferroelectric film is effectively reduced, and the erasing voltage of the memory is obviously reduced.
In the present invention, the material of the ultra-thin insulating layer 1 preferably includes one or more of alumina, zirconia, silica and poly (4-vinylphenol); the material of the ultra-thin insulating layer 2 preferably includes one or more of polymethyl methacrylate, polystyrene, polyimide, polyvinyl alcohol, and polyvinyl pyrrolidone. In the present invention, the thicknesses of the ultra-thin insulating layers 1 and 2 are independently preferably 1 to 50nm, more preferably 5 to 45nm, even more preferably 10 to 40nm, and even more preferably 20 to 30 nm.
The nonvolatile memory provided by the invention comprises an organic semiconductor layer. In the present invention, the organic semiconductor layer preferably includes a small molecule organic semiconductor layer or a polymer organic semiconductor layer, and the material of the small molecule organic semiconductor layer preferably includes pentacene, copper phthalocyanine, zinc phthalocyanine, copper perfluorophthalocyanine, carbon 60, 6, 13-bis (triisopropylsilylethynyl) pentacene, 2, 7-bisoctyl [1] benzothieno [3,2-b ] [1] benzothiophene, or 2, 9-didecylnaphtho [2,3-b: 2', 3' -F ] thieno [3,2-b ] thiophene. In the invention, the structure of the copper perfluorophthalocyanine is shown as a formula I, the structure of the 6, 13-bis (triisopropylsilylethynyl) pentacene is shown as a formula II, the structure of the 2, 7-dioctyl [1] benzothieno [3,2-b ] [1] benzothiophene is shown as a formula III, and the structure of the 2, 9-didecyl naphtho [2,3-b: 2', 3' -F ] thieno [3,2-b ] thiophene is shown as a formula IV:
in the present invention, the material of the polymer organic semiconductor layer preferably comprises poly (3-hexylthiophene-2, 5-diyl), { [ N, N ' -bis (2-octyldodecanol) naphthalene-1, 4,5, 8-bis- (dicarboximide) -2, 6-diyl ] -5,5' - (2,2' -bithiophene) } copolymer or poly {2,2' - [ (2, 5-bis (2-octyldodecyl) -3, 6-dioxo-2, 3,5, 6-tetrahydropyrrolo [3,4-c ] pyrrol-1, 4-diyl) ] dithien-5, 5' -diyl-alt-thieno [3,2-b ] thiophene-2, 5-diyl }. In the invention, the structure of the poly (3-hexylthiophene-2, 5-diyl) is shown as a formula V, the structure of the { [ N, N ' -bis (2-octyldodecanol) naphthalene-1, 4,5, 8-bis- (dicarboximide) -2, 6-diyl ] -5,5' - (2,2' -bithiophene) } copolymer is shown as a formula VI, and the structure of the poly {2,2' - [ (2, 5-bis (2-octyldodecyl) -3, 6-dioxo-2, 3,5, 6-tetrahydropyrrolo [3,4-c ] pyrrole-1, 4-diyl) ] dithiophene-5, 5' -diyl-alt-thieno [3,2-b ] thiophene-2, the structure of 5-diyl } is shown in formula VII:
in the present invention, the thickness of the organic semiconductor layer is preferably 20 to 100nm, more preferably 30 to 90nm, more preferably 40 to 80nm, and even more preferably 50 to 70 nm.
The nonvolatile memory provided by the invention comprises a source-drain electrode. In the present invention, the material of the source-drain electrode independently preferably includes one or more of indium tin oxide, silver, gold, copper, aluminum, graphene, carbon nanotube, and poly (3, 4-ethylenedioxythiophene). In the present invention, the thickness of the source-drain electrode is preferably 70 to 90nm, and more preferably 75 to 85 nm.
The invention also provides a preparation method of the nonvolatile memory in the technical scheme, which comprises the following steps: and sequentially preparing a gate electrode, a ferroelectric film, an ultrathin insulating layer 1, an ultrathin insulating layer 2, an organic semiconductor layer and a source-drain electrode on the surface of the substrate by adopting a vapor deposition and/or spin coating method to obtain the nonvolatile memory.
In the present invention, the preparation method preferably includes the steps of:
(1) preparing a gate electrode on the surface of the substrate by adopting vacuum thermal deposition;
(2) spin-coating a ferroelectric polymer solution on the surface of the gate electrode obtained in the step (1) to obtain a ferroelectric film;
(3) preparing an ultrathin insulating layer 1 on the surface of the ferroelectric film obtained in the step (2) by adopting vacuum thermal deposition;
(4) spin-coating a polymer solution on the surface of the ultrathin insulating layer 1 obtained in the step (3) to obtain an ultrathin insulating layer 2;
(5) preparing an organic semiconductor layer on the surface of the ultrathin insulating layer 2 obtained in the step (4) by adopting vacuum thermal deposition;
(6) and (5) preparing a source-drain electrode on the surface of the organic semiconductor layer obtained in the step (5) by adopting vacuum thermal deposition to obtain the nonvolatile memory.
The invention adopts vacuum thermal deposition to prepare the gate electrode on the surface of the substrate. In the invention, the condition of the vacuum thermal deposition is preferably 8-9 multiplied by 10 vacuum atmosphere-4The thermal deposition rate is preferably 2 to 5A/s.
After the gate electrode is deposited on the surface of the substrate, the ferroelectric polymer solution is spin-coated on the surface of the gate electrode. In the present invention, the mass concentration of the ferroelectric polymer solution is preferably 5% to 15%, and more preferably 10%; the solvent of the ferroelectric polymer solution preferably comprises butyl acetate. In the invention, the spin coating condition is preferably that the spin coating speed is 2000-5000 rpm, and more preferably 3000 rpm. The invention can optimize and adjust the thickness of the obtained ferroelectric film by adjusting the solution concentration and the spin coating speed in the range.
After the spin coating is completed, the present invention preferably subjects the spin coating layer to a heat treatment to remove the solvent from the ferroelectric polymer solution to obtain a ferroelectric thin film. In the present invention, the temperature of the heat treatment is preferably 110 to 130 ℃, more preferably 120 ℃, and the time is preferably 110 to 130min, more preferably 120 min.
After the ferroelectric film is obtained, the invention adopts vacuum thermal deposition to prepare the ultrathin insulating layer 1 on the surface of the ferroelectric film. In the invention, when the ultrathin insulating layer 1 is poly (4-vinylphenol), the ultrathin insulating layer 1 is prepared on the surface of the ferroelectric film by directly adopting a spin coating process. In the present invention, the mass concentration of the poly (4-vinylphenol) is preferably 0.2% to 1%, and more preferably 0.5%; the spin coating condition is preferably that the spin coating speed is 1000-6000 rpm, and more preferably 3000 rpm. The thickness of the poly (4-vinylphenol) film can be optimally adjusted by adjusting the solution concentration and the spin coating rate within the above range.
In the invention, when the ultrathin insulating layer 1 is a metal oxide, the invention firstly adopts vacuum thermal deposition to deposit metal on the surface of the ferroelectric film, and then carries out ultraviolet ozone treatment to oxidize the metal into the metal oxide, thereby obtaining the ultrathin insulating layer 1. In the invention, the condition of the vacuum vapor deposition is preferably 5-7 × 10 of vacuum atmosphere-4Paris, feverThe deposition rate is preferably lower than 0.5 angstrom/second, and more preferably 0.1-0.3 angstrom/second; the time of the ultraviolet ozone treatment is preferably 25-35 min, and more preferably 30 min.
After the ultrathin insulating layer 1 is obtained, the polymer solution is coated on the surface of the ultrathin insulating layer 1 in a spin coating mode to obtain the ultrathin insulating layer 2. In the present invention, the mass concentration of the polymer solution is preferably 0.3% to 0.8%, and more preferably 0.5%; the solvent of the polymer solution preferably comprises chlorobenzene. In the invention, the spin coating condition is preferably that the spin coating speed is 1000-5000 rpm, and more preferably 2500 rpm.
After the spin coating is completed, the present invention preferably performs a heat treatment on the spin-coated layer to remove the solvent from the polymer solution, resulting in the ultra-thin insulating layer 2. In the present invention, the temperature of the heat treatment is preferably 110 to 130 ℃, more preferably 120 ℃, and the time is preferably 10 to 30min, more preferably 20 min.
After the ultrathin insulating layer 2 is obtained, the invention adopts vacuum thermal deposition to prepare the organic semiconductor layer on the surface of the ultrathin insulating layer 2. In the invention, the condition of the vacuum vapor deposition is preferably 1-4 x 10 of vacuum atmosphere-4The thermal deposition rate of the organic semiconductor is 0.1 to 0.5A/s.
After the organic semiconductor layer is obtained, the method adopts vacuum thermal deposition to prepare the source-drain electrode on the surface of the organic semiconductor layer, and the nonvolatile memory is obtained. The invention has no special requirement on vacuum vapor deposition in the preparation process of the source-drain electrode, and the method is commonly used by the technical personnel in the field.
The technical solution of the present invention will be clearly and completely described below with reference to the embodiments of the present invention.
Example 1:
a ferroelectric organic transistor nonvolatile memory is a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode from bottom to top; the ferroelectric gate dielectric layer with the three-layer composite structure is formed by superposing a ferroelectric film with a low Curie electric field and two ultrathin insulating layers (ultrathin insulating layers 1 and 2).
The substrate is a polyethylene naphthalate (PEN) flexible substrate, the gate electrode is aluminum, the ferroelectric film is a copolymer of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene, and the ultrathin insulating layer 1 is aluminum oxide; the ultrathin insulating layer 2 is polymethyl methacrylate; the organic semiconductor layer is pentacene, the source-drain electrode is copper,
the thickness of the gate electrode was 40nm, the thickness of the ferroelectric thin film was 700nm, the thickness of the ultra-thin insulating layer 1 was 4nm, the thickness of the ultra-thin insulating layer 2 was 30nm, the thickness of the organic semiconductor layer was 40nm, and the thickness of the source-drain electrode was 70 nm.
The preparation process of the nonvolatile memory comprises the following steps:
firstly, a substrate is placed in a multi-source organic molecule/metal vapor deposition system, and a vacuum thermal deposition process is adopted to serve as a gate electrode.
Then, dissolving a ferroelectric material vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer in a butyl acetate solvent to prepare a solution with the concentration of 10% (mass percentage), dripping the prepared solution of the vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer on a gate electrode, and preparing a layer of the ferroelectric film of the vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer by adopting a spin coating process. Then, the substrate with the ferroelectric thin film prepared is placed in an oven and heated at 120 ℃ for 120 minutes to remove the residual butyl acetate solvent.
And then placing the heated substrate in a multi-source organic molecule/metal vapor deposition system again, and growing an ultrathin aluminum film on the surface of the ultrathin ferroelectric film by adopting a vacuum thermal deposition process. Then, the substrate was placed in an ultraviolet ozone treatment system and subjected to ultraviolet ozone treatment for 30 minutes. So that the ultra-thin aluminum film prepared on the surface of the ferroelectric film is oxidized into an ultra-thin aluminum oxide film as the ultra-thin insulating layer 1.
Then, a polymer insulating material polymethyl methacrylate is dissolved in a chlorobenzene solvent to prepare a solution with the concentration of 0.5% (mass percent), and then the prepared solution of polymethyl methacrylate is dripped on the ultrathin alumina film (the ultrathin insulating layer 1) to prepare a layer of polymethyl methacrylate film by adopting a spin coating process. Then, the substrate with the ultrathin insulating layer 2 prepared was placed in an oven, heated at 120 ℃ for 20 minutes, and the residual chlorobenzene solvent was removed.
And finally, placing the three-layer ferroelectric gate dielectric layer with a composite structure in a multi-source organic molecule/metal vapor deposition system, and growing a pentacene (organic semiconductor) film on the surface of the ultrathin insulating layer 2 by adopting a vacuum thermal deposition process, wherein the evaporation rate is 0.2 angstrom/second. And then, growing a copper film on the surface of pentacene by adopting a vacuum thermal deposition process to serve as a source-drain electrode. The source-drain electrodes were patterned using a mask, and the channel length and width of the fabricated devices were 100 microns and 1000 microns, respectively.
Example 2:
a ferroelectric organic transistor nonvolatile memory is a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode from bottom to top; the ferroelectric gate dielectric layer with the three-layer composite structure is formed by superposing a ferroelectric film with a low Curie electric field and two ultrathin insulating layers (ultrathin insulating layers 1 and 2).
Wherein, the substrate is glass, the gate electrode is indium tin oxide, the ferroelectric film is vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer, and the ultrathin insulating layer 1 is poly (4-vinylphenol); the ultrathin insulating layer 2 is polystyrene; the organic semiconductor layer is 2, 7-dioctyl [1] benzothieno [3,2-b ] [1] benzothiophene, the source-drain electrode is gold,
the thickness of the gate electrode is 100nm, the thickness of the ferroelectric thin film is 800nm, the thickness of the ultra-thin insulating layer 1 is 30nm, the thickness of the ultra-thin insulating layer 2 is 25nm, the thickness of the organic semiconductor layer is 60nm, and the thickness of the source-drain electrode is 90 nm.
Example 3:
a ferroelectric organic transistor nonvolatile memory is a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode from bottom to top; the ferroelectric gate dielectric layer with the three-layer composite structure is formed by superposing a ferroelectric film with a low Curie electric field and two ultrathin insulating layers (ultrathin insulating layers 1 and 2).
The substrate is polyether sulfone, the grid electrode is silver, the ferroelectric film is a vinylidene fluoride-trifluoroethylene-vinyl chloride copolymer, and the ultrathin insulating layer 1 is zirconium oxide; the ultrathin insulating layer 2 is polyvinyl alcohol; the organic semiconductor layer is copper phthalocyanine, the source-drain electrode is copper,
the thickness of the gate electrode is 30nm, the thickness of the ferroelectric thin film is 850nm, the thickness of the ultra-thin insulating layer 1 is 5nm, the thickness of the ultra-thin insulating layer 2 is 35nm, the thickness of the organic semiconductor layer is 30nm, and the thickness of the source-drain electrode is 85 nm.
Example 4:
a ferroelectric organic transistor nonvolatile memory is a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode from bottom to top; the ferroelectric gate dielectric layer with the three-layer composite structure is formed by superposing a ferroelectric film with a low Curie electric field and two ultrathin insulating layers (ultrathin insulating layers 1 and 2).
The substrate is polyimide, the gate electrode is copper, the ferroelectric film is a vinylidene fluoride-trifluoroethylene-vinyl chloride copolymer, and the ultrathin insulating layer 1 is aluminum oxide; the ultrathin insulating layer 2 is polymethyl methacrylate; the organic semiconductor layer is { [ N, N ' -bis (2-octyldodecanol) naphthalene-1, 4,5, 8-bis- (dicarboximide) -2, 6-diyl ] -5,5' - (2,2' -bithiophene) } copolymer, the source-drain electrode is silver,
the thickness of the gate electrode was 45nm, the thickness of the ferroelectric thin film was 550nm, the thickness of the ultra-thin insulating layer 1 was 3nm, the thickness of the ultra-thin insulating layer 2 was 20nm, the thickness of the organic semiconductor layer was 55nm, and the thickness of the source-drain electrode was 75 nm.
Performance testing
The prepared ferroelectric organic transistor nonvolatile memory was tested for electrical properties using an Agilent B1500A semiconductor test analyzer, all tests were performed at room temperature in atmospheric environment.
The current-voltage transfer characteristics of the nonvolatile memory provided in embodiment 1 of the present invention in different gate voltage scanning ranges are shown in fig. 2; the storage cycle characteristics of the nonvolatile memory provided in embodiment 1 with multi-bit (2-bit) storage characteristics obtained under different erase-write voltage operations are shown in fig. 3; the charge storage retention characteristic of the nonvolatile memory provided in embodiment 1 is shown in fig. 4.
As can be seen from fig. 2 to 4, the nonvolatile memory provided by the present invention can obtain different storage window and storage current ratios in different gate voltage scanning ranges; under the operation of the erasing voltage of +40, 20, 30 and 40V, four memory states of 00, 01, 10 and 11 are obtained, the four memory states can be switched well and kept for a long time, and the currents of the four memory states of 00, 01, 10 and 11 are not obviously attenuated in the actual 2 ten thousand second data storage and keeping time test. These data indicate that the ferroelectric organic transistor nonvolatile memory of the present invention has excellent memory performance at a low erase voltage and has multi-bit memory characteristics. Compared with other reported organic transistor nonvolatile memories with multi-bit storage functions (the working voltage is generally 80-200V), the ferroelectric organic transistor nonvolatile memory provided by the invention has a good multi-bit (2-bit) storage function under low-voltage erasing and writing; in addition, as calculated from fig. 2, the field effect mobility of the nonvolatile memory provided in example 1 of the present application is > 0.5cm2the/Vs shows that the field effect mobility of the nonvolatile memory provided by the application is higher.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. The nonvolatile memory with the multi-bit storage function is of a bottom gate structure and sequentially comprises a substrate, a gate electrode, a ferroelectric gate dielectric layer with a three-layer composite structure, an organic semiconductor layer and a source-drain electrode; the ferroelectric gate dielectric layer with the three-layer composite structure sequentially comprises a ferroelectric film, an ultrathin insulating layer 1 and an ultrathin insulating layer 2, wherein the ultrathin insulating layer 2 is in contact with the organic semiconductor layer; the ferroelectric film is made of a vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer or a vinylidene fluoride-trifluoroethylene-chloroethylene copolymer; the thickness of the ferroelectric film is 200-900 nm, and the thickness of the ultrathin insulating layers 1 and 2 is independently 1-50 nm; the material of the ultrathin insulating layer 1 comprises one or more of alumina, zirconia, silica and poly (4-vinylphenol); the material of the ultrathin insulating layer 2 comprises one or more of polymethyl methacrylate, polystyrene, polyimide, polyvinyl alcohol and polyvinylpyrrolidone.
2. The nonvolatile memory according to claim 1, wherein the substrate is made of one or more of glass, silicon, polyethylene terephthalate, polymethyl methacrylate, polyethylene naphthalate, polyimide, polyether sulfone, and paper.
3. The nonvolatile memory as claimed in claim 1, wherein the gate electrode and the source-drain electrodes are made of one or more materials independently selected from indium tin oxide, silver, gold, copper, aluminum, graphene, carbon nanotube, and poly (3, 4-ethylenedioxythiophene).
4. The nonvolatile memory as in claim 1, wherein the organic semiconductor layer comprises a small molecule organic semiconductor layer or a polymer organic semiconductor layer.
5. The nonvolatile memory according to claim 4, wherein the material of the small molecule organic semiconductor layer comprises pentacene, copper phthalocyanine, zinc phthalocyanine, copper perfluorophthalocyanine, carbon 60, 6, 13-bis (triisopropylsilylethynyl) pentacene, 2, 7-bisoctyl [1] benzothieno [3,2-b ] [1] benzothiophene, or 2, 9-didecylnaphtho [2,3-b: 2', 3' -F ] thieno [3,2-b ] thiophene.
6. The nonvolatile memory as in claim 4, wherein the material of the polymer organic semiconductor layer comprises poly (3-hexylthiophene-2, 5-diyl), { [ N, N ' -bis (2-octyldodecanol) naphthalene-1, 4,5, 8-bis- (dicarboximide) -2, 6-diyl ] -5,5' - (2,2' -bithiophene) } copolymer or poly {2,2' - [ (2, 5-bis (2-octyldodecyl) -3, 6-dioxo-2, 3,5, 6-tetrahydropyrrolo [3,4-c ] pyrrole-1, 4-diyl) ] dithiophene-5, 5' -diyl-alt-thieno [3,2-b ] thiophene-2, 5-diyl }.
7. The nonvolatile memory according to any one of claims 4 to 6, wherein the thickness of the organic semiconductor layer is 20 to 100 nm.
8. A method of manufacturing a non-volatile memory device according to any of claims 1 to 7, comprising the steps of:
and sequentially preparing a gate electrode, a ferroelectric film, an ultrathin insulating layer 1, an ultrathin insulating layer 2, an organic semiconductor layer and a source-drain electrode on the surface of the substrate by adopting a vapor deposition and/or spin coating method to obtain the nonvolatile memory.
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