CN109491161A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN109491161A CN109491161A CN201811445530.1A CN201811445530A CN109491161A CN 109491161 A CN109491161 A CN 109491161A CN 201811445530 A CN201811445530 A CN 201811445530A CN 109491161 A CN109491161 A CN 109491161A
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- cabling
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
This application involves a kind of array substrate and display panels, wherein, array substrate includes: the first substrate at least set gradually under, the first conductive layer, the first passivation layer, the second conductive layer, the second passivation layer, first electrode layer, color blocking material layer, liquid crystal layer, the second electrode lay and the second substrate, the first passivation layer covering part first substrate；Second the first passivation layer of passivation layer covering part；The first conductive layer of first electrode layer covering part, the first passivation layer, the second conductive layer and the second passivation layer；First conductive layer includes a plurality of first cabling, and the second conductive layer includes a plurality of second cabling, wherein each first cabling connects multiple second cablings by the cabling of corresponding first electrode layer；There are overlapping regions with the projection of the first cabling on the first substrate for the projection of color blocking material layer on the first substrate.By the way that color blocking material layer is arranged between the first cabling and corresponding the second electrode lay, reduces the capacitor between the first conductive layer and the second electrode lay, reduce circuit load.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of array substrate and display panel.
Background technique
GOA (gate on array) is an important technology in panel design, and major advantage is can to remove gate drive from
Dynamic integrated circuit reduces product cost, and driving circuit generates clock signal and is sent to gate driving circuit, and gate driving circuit is logical
Oversampling clock signal line provides clock signal and is given to each gate driving circuit with into line scans.
It is responsible for offer signal due to clock signal line and gives gate driving circuit, signal is not intended to make by these cablings certainly
At signal attenuation, general PSA (Polymer SustainedAlignment, polymerization macromolecule auxiliary orientation) mode and VA
Under (VerticalAlignment, perpendicular alignmnet) mode, the signal resistance and signal capacitor of clock signal line, which are all fallen within, actively to be opened
How the wherein one or both ends closed, solve the problems, such as gate driving circuit load excessive, become important topic.
Summary of the invention
In order to solve the problems, such as gate drive circuit load excessive, the object of the present invention is to provide a kind of array substrate,
Include:
First substrate；
The first conductive layer being formed on first substrate；
The first passivation layer being formed on the first conductive layer, and the first passivation layer covering part first substrate；
The second conductive layer being formed on the first passivation layer；
The second passivation layer being formed on the second conductive layer, and second the first passivation layer of passivation layer covering part；
It is formed and the first electrode layer on the second passivation layer, the first conductive layer of first electrode layer covering part, the first passivation
Layer, the second conductive layer and the second passivation layer；
The color blocking material layer being formed in first electrode layer, color blocking material layer the second passivation layer of covering part；
It is formed in the liquid crystal layer of color blocking material layer, the second passivation layer of liquid crystal layer covering part；
The second electrode lay being formed on liquid crystal layer；
The second substrate being formed on the second electrode lay；
First conductive layer includes a plurality of first cabling, and the second conductive layer includes a plurality of second cabling, wherein each first cabling
Multiple second cablings are connected by the cabling of corresponding first electrode layer；
There are overlapping regions with the projection of the first cabling on the first substrate for the projection of color blocking material layer on the first substrate.
The projection of each first cabling on the first substrate is located at color blocking material layer in the first base in one of the embodiments,
Inside projection on plate.
The first cabling extends in a first direction in one of the embodiments, and the second cabling edge intersects with first direction
Second direction extends.
Be provided with target area on each first cabling in one of the embodiments, target area include the first cabling with
The cross-line region that each second cabling is formed.
Target area further includes the cross-connect field of the first cabling and the second cabling in one of the embodiments,.
It is formed with conductive bridge hole on the first conductive layer in one of the embodiments, first electrode layer is covered in first
On conductive layer and the second conductive layer.
Conductive bridge hole at least two in one of the embodiments,.
The first passivation layer is in target area covering part first substrate in one of the embodiments,.
Liquid crystal layer has a medium coefficient in one of the embodiments, and medium coefficient includes the dielectric system of parallel vector
Several dielectric coefficients with vertical vector.
A kind of display panel, including colored filter substrate, driving circuit and above-mentioned array substrate.
One or more embodiment provided by the invention at least has the advantages that battle array provided in an embodiment of the present invention
Column substrate, from the bottom to top successively include first substrate, the first conductive layer, the first passivation layer, the second conductive layer, the second passivation layer,
First electrode layer, color blocking material layer, liquid crystal layer and the second electrode lay and the second substrate, wherein the first conductive layer includes a plurality of
First cabling, the second conductive layer include a plurality of second cabling, and each first cabling is connected by the cabling of corresponding first electrode layer
Multiple second cablings, there are Chong Die with the projection on the first substrate of the first cabling for the projection of color blocking material layer on the first substrate
Region.By the way that color blocking material layer is arranged between the first cabling and corresponding the second electrode lay, reduce the first conductive layer and second
Capacitor between electrode layer, to reduce circuit load.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of display panel in one embodiment；
Fig. 2 is capacitive load circuit schematic diagram in an example；
Fig. 3 is the structural schematic diagram of array substrate in one embodiment；
Fig. 4 is the cross-sectional view of array substrate in another embodiment；
Fig. 5 is the structural schematic diagram of array substrate in another embodiment；
Fig. 6 is the cross-sectional view of array substrate in further embodiment.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing
Give preferred embodiment of the invention.But the invention can be realized in many different forms, however it is not limited to this paper institute
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
It should be noted that it can be directly to separately when an element is considered as " connection " another element
One element and it is in combination be integrated, or may be simultaneously present centering elements.Term as used herein " installation ", " one
End ", " other end " and similar statement are for illustrative purposes only.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the listed item of pass.
As shown in Figure 1, using the display panel with gate array driving of GOA technology, including colored filter substrate
10, array substrate 20, driving circuit 30 and gate driving circuit 40 are produced on array substrate by using gate driving circuit 40
On 20, the on-off of thin film transistor (TFT) is driven instead of the driving chip made by external silicon chip.Since GOA technology can be direct
Gate driving circuit 40 is set around the display area of display panel, simplifies production process, improves the degree of integration of display panel,
So that ultrathin design may be implemented in display panel.
Using gate driving circuit carry out gate drive when, capacitive load circuit as shown in Fig. 2, driving circuit send when
Clock voltage signal 100 is sent to active switch through signal line, signal resistance 200 caused by signal line, signal capacitor 300 and simultaneously
The shunt capacitance 400 being associated between the control terminal b of active switch and the first end a of active switch 500.Signal resistance 200, signal
Capacitor 300 and shunt capacitance 400 are all fallen on first end a and control terminal b, and circuit load is overweight, influence clock signal transmission effect
Fruit.
In order to solve the above-mentioned technical problem, the embodiment of the invention provides a kind of array substrates, as shown in Figure 3 and Figure 4, battle array
Column substrate, comprising: first substrate 1；The first conductive layer 2 being formed on first substrate 1；Be formed on the first conductive layer 2
One passivation layer 3, and 3 covering part first substrate 1 of the first passivation layer；The second conductive layer 4 being formed on the first passivation layer 3；Shape
At in the second passivation layer 5 on the second conductive layer 4, and 5 the first passivation layer of covering part 3 of the second passivation layer；It is formed and second blunt
Change the first electrode layer 6 on layer 5,6 covering part the first conductive layer 2 of first electrode layer, the first passivation layer 3,4 and of the second conductive layer
Second passivation layer 5；The color blocking material layer 7 being formed in first electrode layer 6,7 the second passivation layer of covering part 5 of color blocking material layer；
It is formed in the liquid crystal layer 8 of color blocking material layer 7,8 the second passivation layer of covering part 5 of liquid crystal layer；The second electricity being formed on liquid crystal layer 8
Pole layer 9；The second substrate 91 being formed on the second electrode lay 9；First conductive layer 2 includes a plurality of first cabling 21, and second is conductive
Layer 4 includes a plurality of second cabling 41, wherein each first cabling 21 passes through the cabling of corresponding first electrode layer 6 connection multiple the
Two cablings 41；There is weight with the projection of the first cabling 21 on first substrate 1 in the projection of color blocking material layer 7 on first substrate 1
Folded region.
Inventor's discovery circuit, which loads, impacts the signal transmission of clock signal line, such as excessive circuit load meeting
Decaying of the signal in transmission process is caused, is unfavorable for showing, and the size of capacitor is a weight for influencing circuit load between plate
Want factor.Array substrate provided in an embodiment of the present invention, by the way that color blocking material layer 7 is arranged in first electrode layer 6, so that first
The partial region opposite with the second electrode lay 9 of cabling 21 or whole region are isolated by color blocking material layer 7, that is, are reduced to the greatest extent
Or opposite relative area between double layer of metal is avoided, so that the capacitor between the first conductive layer 2 and the second electrode lay 9 is reduced,
Capacitor between reduction plate.To reduce the load of gate drive circuit, to reduce signal through in clock signal line transmission process
Signal attenuation improves signal transmission quality and reliability.Wherein, color blocking material layer 7 can be is made of resin material.
The projection of each first cabling 21 on first substrate 1 is located at color blocking material layer 7 in one of the embodiments,
On one substrate inside 1 projection.Specifically, the first cabling 21, which is incident upon the projection in color blocking material layer 7, is located at color blocking material layer 7
RGB color resistance material covered area in, guarantee pass through color between the corresponding the second electrode lay 9 of each first cabling 21
Resistance material layer 7 is isolated, and capacitor between plate is reduced.
The first cabling 21 extends in a first direction in one of the embodiments, and the second cabling 41 is handed over along with first direction
The second direction of fork extends.Specifically, each second cabling 41 is connected with corresponding first cabling 21, across be located at its corresponding the
Remaining first cabling 21 of the second direction side of one cabling 21, extends in a second direction.
Target area 92 is provided on each first cabling 21 in one of the embodiments, target area 92 includes first
The cross-line region 921 that cabling 21 and each second cabling 41 are formed, target area 92 is for reducing the first cabling 21 and the second electricity
The region of capacitor between pole layer 9.
Wherein, the target area 92 of the first cabling 21 refers to for reducing between the first cabling 21 and the second electrode lay 9
The region of capacitor.The first cabling 21 in target area 92 can be hollow out state, and the first cabling 21 in target area 92 is also
It can be set filled with non-conducting material in fluted, groove, to reduce capacitor between plate.This part i.e. in target area 92
First cabling 21 (can be solid metal, the hollow-out part etc. being also possible on the first cabling 21) with pair the second electrode lay
The capacitor formed between this first cabling of part 21 and the second electrode lay 9 that the capacitor C1 formed between 9 is less than outside target area.
Specific implementation be not limited only to this place for two examples.Cross-line region 921, refers on the first cabling 21 and the second cabling
41 intersect unconnected part.The embodiment of the present invention, which uses, is arranged mesh in the cross-line region of the first cabling 21 and each second cabling 41
Region 92 is marked, the capacitance of gate driving circuit cabling is effectively reduced, reduces gate driving circuit and walks linear load and reduce plate
Power.
In one of the embodiments, as shown in Figure 3 and Figure 4, target area 92 further includes that the first cabling 21 is walked with second
The cross-connect field 922 of line 41.Wherein, cross-connect field 922, which refers to, walks with the second cabling 41 in first be correspondingly connected with
Projection on line 21 has the region of intersection.On the first cabling 21 with 41 cross-connect field of the second cabling, 921 borehole or filling
The non-conducting materials such as resin reduce capacitor, to reduce the circuit load of gate driving circuit.
Conductive bridge hole 93 is formed on the first conductive layer in one of the embodiments, first electrode layer 9 is covered in
On one conductive layer 2 and the second conductive layer 3.It is conductive that conductive bridge hole 93 connects the first cabling 21 and second on the first conductive layer 2
The second cabling 41 on layer 4, reduces the capacitance of gate drive circuit.
Conductive bridge hole 93 at least two in one of the embodiments,.
In one of the embodiments, as shown in Figure 3 and Figure 4, the first passivation layer 3 is in 92 covering part first of target area
Substrate 1.First passivation layer 3 has dug hole on 92 covering part first substrate 1 of target area, i.e. the first cabling 21, in the hole
Without conductive material, the first passivation layer 3 fills the partial region, and contacts with first substrate 1 at place, capacity plate antenna is reduced, to drop
The capacitance of low gate driving circuit cabling.
Target area 92 is filled with non-conducting material in one of the embodiments,.92 potting resin etc. in target area
Non-conducting material reduces capacitor between plate, to reduce the load of gate driving circuit cabling.
Liquid crystal layer 8 has a medium coefficient in one of the embodiments, and medium coefficient includes the dielectric system of parallel vector
Several dielectric coefficients with vertical vector.First kind conductive bridge hole is formed on each first cabling 21, and simultaneously by first electrode
Layer 6 is covered on the first conductive layer 2, through conductive bridge hole transmission voltage signal in first electrode layer 6 and the second electrode lay 9,
Thus approaching the medium coefficient of liquid crystal layer 8 is that the dielectric coefficient of parallel vector (citing: is controlled by voltage signal size and is situated between
The gradient in electrostrictive coefficient direction), and effectively further decrease the capacitance of gate driving circuit cabling.Similarly, it is walked each second
The second class conductive bridge hole is formed on line 41, and the second electrode lay 9 is covered on the second conductive layer 4 simultaneously, through conducting bridge
Hole transmission voltage signal is connect in the second electrode lay 9 and the second electrode lay 9, thus approaches the medium coefficient of liquid crystal layer 8 and is
The dielectric coefficient (citing: by the gradient in voltage signal size control dielectric coefficient direction) of parallel vector, and effectively further
Reduce the capacitance of gate driving circuit cabling.
A kind of display panel, as shown in Figure 1, Figure 2, Figure 3, Figure 4, including colored filter substrate 10,30 and of driving circuit
Above-mentioned array substrate 20.Display panel provided in an embodiment of the present invention, the clock signal that driving circuit 30 generates are given to array base
The first cabling 21 and the second cabling 41 on plate 20, to drive thin film transistor (TFT), in corresponding first cabling of each second cabling 41
Target area 92 is set on 21, so that second cabling 41 is fallen in the target area 92 in the projection on the first cabling 21, i.e.,
So that the capacitor at the overlapping place of first cabling 21 connected to it of the second cabling 41 minimizes, to reduce gate driving circuit 40
The capacitance of cabling reduces platen power.
A kind of array substrate manufacturing method, comprising:
First substrate is provided；The first conductive layer is formed on the first substrate；The first passivation layer is formed on the first conductive layer,
And make the first passivation layer covering part first substrate；The second conductive layer is formed on the first passivation layer；On the second conductive layer
The second passivation layer is formed, and makes second the first passivation layer of passivation layer covering part；First electrode is formed on the second passivation layer
Layer, and make the first conductive layer of first electrode layer covering part, the first passivation layer, the second conductive layer and the second passivation layer；?
Color blocking material layer, color blocking material layer the second passivation layer of covering part are formed on one electrode layer；Liquid crystal is formed in color blocking material layer
Layer, the second passivation layer of liquid crystal layer covering part；The second electrode lay is formed on liquid crystal layer；The second base is formed on the second electrode layer
Plate；First conductive layer includes a plurality of first cabling, and the second conductive layer includes a plurality of second cabling, wherein each first cabling passes through
The cabling of corresponding first electrode layer connects multiple second cablings；The projection of color blocking material layer on the first substrate and the first cabling
There are overlapping regions for projection on the first substrate.It should be noted that noun paraphrase and above-described embodiment in the present embodiment
In it is identical, working principle is also identical, and this will not be repeated here.
In some embodiments in this application, display panel may include liquid crystal display panel, and wherein liquid crystal display panel can wrap
Switching array substrate, colorized optical filtering laminar substrate and the liquid crystal layer 8 being formed between two substrates are included, display panel can also be OLED
(Organic Light-Emitting Diode, Organic Electricity laser display) panel or QLED (Quantum Dot Light
Emitting Diodes, light emitting diode with quantum dots) panel.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of array substrate characterized by comprising
First substrate；
The first conductive layer being formed on the first substrate；
The first passivation layer being formed on first conductive layer, and first substrate described in the first passivation layer covering part；
The second conductive layer being formed on first passivation layer；
The second passivation layer being formed on second conductive layer, and the first passivation described in the second passivation layer covering part
Layer；
It is formed with the first electrode layer on second passivation layer, the first conductive layer described in the first electrode layer covering part,
First passivation layer, second conductive layer and second passivation layer；
The color blocking material layer being formed in the first electrode layer, the second passivation layer described in the color blocking material layer covering part；
It is formed in the liquid crystal layer of the color blocking material layer, the second passivation layer described in the liquid crystal layer covering part；It is formed in described
The second electrode lay on liquid crystal layer；
The second substrate being formed on the second electrode lay；
First conductive layer includes a plurality of first cabling, and second conductive layer includes a plurality of second cabling, wherein each described
First cabling connects multiple second cablings by the cabling of corresponding first electrode layer；
The projection and the projection of first cabling on the first substrate of the color blocking material layer on the first substrate
There are overlapping regions.
2. array substrate according to claim 1, which is characterized in that each first cabling is on the first substrate
Projection is located inside the projection of the color blocking material layer on the first substrate.
3. array substrate according to claim 1 or 2, which is characterized in that first cabling extends in a first direction, institute
The second cabling is stated to extend along the second direction intersected with the first direction.
4. array substrate according to claim 3, which is characterized in that it is provided with target area on each first cabling,
The target area includes the cross-line region that first cabling and each second cabling are formed, and the target area is to be used for
Reduce the region of capacitor between the first cabling and the second electrode lay.
5. array substrate according to claim 4, which is characterized in that the target area further include first cabling with
The cross-connect field of second cabling.
6. array substrate described according to claim 1 or 2 or 4 or 5, which is characterized in that be formed on first conductive layer
Conductive bridge hole, the first electrode layer are covered on first conductive layer and second conductive layer.
7. array substrate according to claim 6, which is characterized in that the conductive bridge hole at least two.
8. array substrate according to claim 4 or 5, which is characterized in that first passivation layer is in the target area
First substrate described in covering part.
9. according to claim 1 or 2 or 4 or 5 or 7 array substrates, which is characterized in that the liquid crystal layer has a medium system
Number, the medium coefficient includes the dielectric coefficient of parallel vector and the dielectric coefficient of vertical vector.
10. a kind of display panel, which is characterized in that including any in colored filter substrate, driving circuit and claim 1-9
Array substrate described in.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811445530.1A CN109491161A (en) | 2018-11-29 | 2018-11-29 | Array substrate and display panel |
| PCT/CN2019/071072 WO2020107664A1 (en) | 2018-11-29 | 2019-01-10 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811445530.1A CN109491161A (en) | 2018-11-29 | 2018-11-29 | Array substrate and display panel |
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| CN109491161A true CN109491161A (en) | 2019-03-19 |
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| CN201811445530.1A Pending CN109491161A (en) | 2018-11-29 | 2018-11-29 | Array substrate and display panel |
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| CN111427206A (en) * | 2020-03-24 | 2020-07-17 | 京东方科技集团股份有限公司 | Array substrate and display device |
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| CN111427206A (en) * | 2020-03-24 | 2020-07-17 | 京东方科技集团股份有限公司 | Array substrate and display device |
| WO2021190159A1 (en) * | 2020-03-24 | 2021-09-30 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN111427206B (en) * | 2020-03-24 | 2022-07-26 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN113539203A (en) * | 2021-06-29 | 2021-10-22 | 北海惠科光电技术有限公司 | Display panel's drive arrangement, display device |
| CN114740664A (en) * | 2022-04-21 | 2022-07-12 | 绵阳惠科光电科技有限公司 | Display panel and display screen |
| WO2023202089A1 (en) * | 2022-04-21 | 2023-10-26 | 绵阳惠科光电科技有限公司 | Display panel and display screen |
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Application publication date: 20190319 |