CN109298575A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN109298575A CN109298575A CN201811447419.6A CN201811447419A CN109298575A CN 109298575 A CN109298575 A CN 109298575A CN 201811447419 A CN201811447419 A CN 201811447419A CN 109298575 A CN109298575 A CN 109298575A
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- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 238000002161 passivation Methods 0.000 claims abstract description 49
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002096 quantum dot Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present application relates to an array substrate and a display panel, wherein, the array substrate includes: the liquid crystal display device at least comprises a first substrate, a first conductive layer, a first passivation layer, a second conductive layer, a second passivation layer, a first electrode layer, a liquid crystal layer, a second electrode layer and a second substrate which are arranged in sequence from bottom to top, wherein the first passivation layer covers a part of the first substrate; the second passivation layer covers a portion of the first passivation layer; the first electrode layer covers a part of the first conductive layer, the first passivation layer, the second conductive layer and the second passivation layer; the first conductive layer comprises a plurality of first wires extending along a first direction, the second conductive layer comprises a plurality of second wires extending along a second direction crossed with the first direction, and each first wire is connected with the plurality of second wires through the corresponding first electrode layer; each first wire is provided with a target area, and the target area comprises a cross-line area formed by the first wires and each second wire, so that the load of a gate driving circuit is reduced, and the panel power is reduced.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of array substrate and display panel.
Background technique
GOA (gate on array, gate drive circuit substrate) is an important technology in panel design, main excellent
Point is can to remove gate drive integrated circuit from, reduces product cost, and driver generates clock signal and is sent to gate driving electricity
Road, gate driving circuit provide clock signal by clock signal line and are given to each gate driving circuit with into line scans.
It is responsible for offer signal due to clock signal line and gives gate driving circuit, signal is not intended to make by these cablings certainly
At signal attenuation, general PSA (Polymer SustainedAlignment, polymerization macromolecule auxiliary orientation) mode and VA
Under (VerticalAlignment, perpendicular alignmnet) both of which, the signal resistance and signal capacitor of clock signal line all fall within master
How the wherein one or both ends of dynamic switch, solve the problems, such as gate driving circuit load excessive, become important topic.
Summary of the invention
In order to solve the problems, such as gate drive circuit load excessive, the object of the present invention is to provide a kind of array substrate,
Include:
First substrate；The first conductive layer being formed on first substrate；The first passivation layer being formed on the first conductive layer,
And the first passivation layer covering part first substrate；The second conductive layer being formed on the first passivation layer；It is formed in the second conductive layer
On the second passivation layer, and second the first passivation layer of passivation layer covering part；Formation and the first electrode layer on the second passivation layer,
The first conductive layer of first electrode layer covering part, the first passivation layer, the second conductive layer and the second passivation layer；It is formed in first electrode
Liquid crystal layer on layer；The second electrode lay being formed on liquid crystal layer；The second substrate being formed on the second electrode lay；
First conductive layer includes a plurality of the first cabling extended in a first direction, and the second conductive layer includes a plurality of edge and first
The second cabling that the second direction that direction intersects extends, wherein each first cabling is connected multiple by corresponding first electrode layer
Second cabling；
Target area is provided on each first cabling, target area includes the cross-line that the first cabling and each second cabling are formed
Region, target area are for reducing the region of capacitor between the first cabling and the second electrode lay.
Target area further includes the cross-connect field of the first cabling and the second cabling in one of the embodiments,.
The first passivation layer is in target area covering part first substrate in one of the embodiments,.
Target area is filled with non-conducting material in one of the embodiments,.
First kind conductive bridge hole, first electrode layer covering are formed on the first conductive layer in one of the embodiments,
In on the first conductive layer.
The second class conductive bridge hole is also formed on the second conductive layer in one of the embodiments, first electrode layer is covered
It is placed on the second conductive layer.
First kind conductive bridge hole at least two in one of the embodiments,.
Second class conductive bridge hole at least two in one of the embodiments,.
Liquid crystal layer has a medium coefficient in one of the embodiments, and medium coefficient includes the dielectric system of parallel vector
Several dielectric coefficients with vertical vector.
A kind of display panel, including colored filter substrate, driver and above-mentioned array substrate.
One or more embodiment provided by the invention at least has the advantages that provided in an embodiment of the present invention one
Kind array substrate successively includes first substrate, the first conductive layer, the first passivation layer, the second conductive layer, the second passivation from the bottom to top
Layer, first electrode layer, liquid crystal layer and the second electrode lay and the second substrate, wherein the first conductive layer includes a plurality of first cabling,
Second conductive layer includes a plurality of second cabling, and each first cabling is walked by the cabling connection multiple second of corresponding first electrode layer
Target area is arranged by the first cabling on the first conductive layer in line, and the second cabling is handed in the second cabling being correspondingly connected with
The projection of folded place on the first substrate is fallen in the projection of target area on the first substrate, to reduce the first conductive layer and second
Capacitor between electrode layer, to reduce circuit load.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of display panel in one embodiment；
Fig. 2 is capacitive load circuit schematic diagram in an example；
Fig. 3 is the structural schematic diagram of array substrate in one embodiment；
Fig. 4 is the cross-sectional view of array substrate in another embodiment.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing
Give preferred embodiment of the invention.But the invention can be realized in many different forms, however it is not limited to this paper institute
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
It should be noted that it can be directly to separately when an element is considered as " connection " another element
One element and it is in combination be integrated, or may be simultaneously present centering elements.Term as used herein " installation ", " one
End ", " other end " and similar statement are for illustrative purposes only.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the listed item of pass.
As shown in Figure 1, using GOA (gate on array, gate drive circuit substrate) technology there is gate array to drive
Dynamic display panel, including colored filter substrate 10, array substrate 20, driver 30 and gate driving circuit 40, by adopting
It is produced in array substrate 20 with gate driving circuit 40, instead of the driving chip made by external silicon chip to drive film brilliant
The on-off of body pipe.Since GOA (gate on array, gate drive circuit substrate) technology can be directly in the aobvious of display panel
Show setting gate driving circuit 40 around region, simplifies production process, the degree of integration of display panel is improved, so that display panel can
To realize ultrathin design.
When carrying out gate drive using gate driving circuit, capacitive load circuit is as shown in Fig. 2, the clock that driver is sent
Voltage signal 100 is sent to active switch through signal line, signal resistance 200 caused by signal line, signal capacitor 300 and parallel connection
Shunt capacitance 400 between the control terminal b of active switch and the first end a of active switch 500.Signal resistance 200, signal electricity
Appearance 300 and shunt capacitance 400 are all fallen on first end a and control terminal b, and circuit load is overweight, influences clock signal laser propagation effect.
In order to solve the above-mentioned technical problem, the embodiment of the invention provides a kind of array substrates, as shown in Figure 3 and Figure 4, battle array
Column substrate, comprising: first substrate 1；The first conductive layer 2 being formed on first substrate 1；Be formed on the first conductive layer 2
One passivation layer 3, and 3 covering part first substrate 1 of the first passivation layer；The second conductive layer 4 being formed on the first passivation layer 3；Shape
At in the second passivation layer 5 on the second conductive layer 4, and 5 the first passivation layer of covering part 3 of the second passivation layer；It is formed and second blunt
Change the first electrode layer 6 on layer 5,6 covering part the first conductive layer 2 of first electrode layer, the first passivation layer 3,4 and of the second conductive layer
Second passivation layer 5；The liquid crystal layer 7 being formed in first electrode layer 6；The second electrode lay 8 being formed on liquid crystal layer 7；It is formed in
The second substrate 9 on the second electrode lay 8；First conductive layer 2 includes a plurality of the first cabling 21 extended in a first direction, and second leads
Electric layer 4 includes the second cabling 41 that a plurality of edge extends with the second direction that first direction intersects, wherein is set on each first cabling 21
It is equipped with target area 91, target area 91 includes the cross-line region 911 that the first cabling 21 is formed with each second cabling 41, target area
Domain 91 is for reducing the region of capacitor between the first cabling 21 and the second electrode lay 8.
Wherein, the target area 91 of the first cabling 21 refers to for reducing between the first cabling 21 and the second electrode lay 8
The region of capacitor.The first cabling 21 in target area 91 can be hollow out state, and the first cabling 21 in target area 91 is also
It can be set filled with non-conducting material in fluted, groove, to reduce capacitor between plate.This part i.e. in target area 91
First cabling 21 (can be solid metal, the hollow-out part etc. being also possible on the first cabling 21) with pair the second electrode lay
The capacitor formed between this first cabling of part 21 and the second electrode lay 8 that the capacitor C1 formed between 8 is less than outside target area.
Specific implementation be not limited only to this place for two examples.Cross-line region 911 refers to that the first cabling and the second cabling intersect
Unconnected part.The embodiment of the present invention, which uses, is arranged target area in the cross-line region of the first cabling 21 and each second cabling 41
91, the capacitance of gate driving circuit cabling is effectively reduced, reduces gate driving circuit and walks linear load and reduce platen power.
In one of the embodiments, as shown in Figure 3 and Figure 4, target area 91 further includes that the first cabling 21 is walked with second
The cross-connect field 912 of line 41.Wherein, cross-connect field 912, which refers to, walks with the second cabling 41 in first be correspondingly connected with
Projection on line 21 has the region of intersection.912 borehole of region or filling at 41 interconnection of the first cabling 21 and the second cabling
The non-conducting materials such as resin reduce capacitor, to reduce the circuit load of gate driving circuit.
In one of the embodiments, as shown in Figure 3 and Figure 4, the first passivation layer 3 is in 91 covering part first of target area
Substrate 1.First passivation layer 3 has dug hole on 91 covering part first substrate 1 of target area, i.e. the first cabling 21, in the hole
Without conductive material, the first passivation layer 3 fills the partial region, and contacts with first substrate 1 at place, capacity plate antenna is reduced, to drop
The capacitance of low gate driving circuit cabling.
Target area 91 is filled with non-conducting material in one of the embodiments,.91 potting resin etc. in target area
Non-conducting material reduces capacitor between plate, to reduce the load of gate driving circuit cabling.
In one of the embodiments, as shown in Figure 3 and Figure 4, first kind conductive bridge is formed on the first conductive layer 2
Hole, first electrode layer 6 are covered on the first conductive layer 2.
In one of the embodiments, as shown in Figure 3 and Figure 4, the second class conductive bridge is also formed on the second conductive layer 4
Hole, first electrode layer 6 are covered on the second conductive layer 4.
In one of the embodiments, as shown in Figure 3 and Figure 4, first kind conductive bridge hole at least two.
In one of the embodiments, as shown in Figure 3 and Figure 4, the second class conductive bridge hole at least two.
Liquid crystal layer 7 has a medium coefficient in one of the embodiments, and medium coefficient includes the dielectric system of parallel vector
Several dielectric coefficients with vertical vector.First kind conductive bridge hole is formed on each first cabling 21, and simultaneously by first electrode
Layer 6 is covered on the first conductive layer 2, through conductive bridge hole transmission voltage signal in first electrode layer 6 and the second electrode lay 8,
Thus approaching the medium coefficient of liquid crystal layer 7 is that the dielectric coefficient of parallel vector (citing: is controlled by voltage signal size and is situated between
The gradient in electrostrictive coefficient direction), and effectively further decrease the capacitance of gate driving circuit cabling.Similarly, it is walked each second
The second class conductive bridge hole is formed on line 41, and the second electrode lay 8 is covered on the second conductive layer 4 simultaneously, through conducting bridge
Hole transmission voltage signal is connect in the second electrode lay 8 and the second electrode lay 8, thus approaches the medium coefficient of liquid crystal layer 7 and is
The dielectric coefficient (citing: by the gradient in voltage signal size control dielectric coefficient direction) of parallel vector, and effectively further
Reduce the capacitance of gate driving circuit cabling.
A kind of display panel, as Figure 1 and Figure 4, including colored filter substrate 10, driver 30 and above-mentioned array base
Plate 20.Display panel provided in an embodiment of the present invention, the clock signal that driver 30 generates are given to first in array substrate 20
Target is arranged on corresponding first cabling 21 of each second cabling 40 to drive thin film transistor (TFT) in cabling 21 and the second cabling 41
Region 91, so that second cabling 41 is fallen in the target area 91 in the projection on the first cabling 21, i.e., so that the second cabling
The capacitor at the overlapping place of 41 first cablings 21 connected to it minimizes, to reduce the capacitor of 40 cabling of gate driving circuit
Value reduces platen power.
A kind of array substrate manufacturing method, comprising:
First substrate is provided；The first conductive layer is formed on the first substrate；The first passivation layer is formed on the first conductive layer,
And make the first passivation layer covering part first substrate；The second conductive layer is formed on the first passivation layer；On the second conductive layer
The second passivation layer is formed, and makes second the first passivation layer of passivation layer covering part；First electrode is formed on the second passivation layer
Layer, and make the first conductive layer of first electrode layer covering part, the first passivation layer, the second conductive layer and the second passivation layer；?
Liquid crystal layer is formed on one electrode layer；The second electrode lay is formed on liquid crystal layer；The second substrate is formed on the second electrode layer；?
A plurality of first cabling is formed on one conductive layer, and a plurality of the second cabling corresponding with each first cabling is formed on the second conductive layer,
Wherein, each first cabling connects corresponding second cabling by the cabling of corresponding first electrode layer；It is formed on the first cabling
There is hole, the second cabling is located inside the region of hole in the projection on the first cabling.It should be noted that the name in the present embodiment
Word paraphrase is same with the above-mentioned embodiment, and working principle is also identical, and this will not be repeated here.
In some embodiments in this application, display panel may include liquid crystal display panel, and wherein liquid crystal display panel can wrap
Switching array substrate is included, colorized optical filtering laminar substrate and the liquid crystal layer being formed between two substrates, display panel can also be OLED
(Organic Light-Emitting Diode, Organic Electricity laser display) panel or QLED (Quantum Dot Light
Emitting Diodes, light emitting diode with quantum dots) panel.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of array substrate characterized by comprising
First substrate；
The first conductive layer being formed on the first substrate；
The first passivation layer being formed on first conductive layer, and first substrate described in the first passivation layer covering part；
The second conductive layer being formed on first passivation layer；
The second passivation layer being formed on second conductive layer, and the first passivation described in the second passivation layer covering part
Layer；
It is formed with the first electrode layer on second passivation layer, the first conductive layer described in the first electrode layer covering part,
First passivation layer, second conductive layer and second passivation layer；
The liquid crystal layer being formed in the first electrode layer；
The second electrode lay being formed on the liquid crystal layer；
The second substrate being formed on the second electrode lay；
First conductive layer includes a plurality of the first cabling extended in a first direction, second conductive layer include a plurality of edge with
The second cabling that the second direction that the first direction intersects extends, wherein each first cabling passes through corresponding first electricity
Pole layer connects multiple second cablings；
Target area is provided on each first cabling, the target area includes that first cabling is walked with each described second
The cross-line region that line is formed, the target area is for reducing the region of capacitor between the first cabling and the second electrode lay.
2. array substrate according to claim 1, which is characterized in that the target area further include first cabling with
The cross-connect field of second cabling.
3. array substrate according to claim 1 or 2, which is characterized in that first passivation layer is in the target area
First substrate described in covering part.
4. array substrate according to claim 3, which is characterized in that the target area is filled with non-conducting material.
5. array substrate according to claim 4, which is characterized in that be formed with first kind conduction on first conductive layer
Hole is bridged, the first electrode layer is covered on first conductive layer.
6. array substrate according to claim 5, which is characterized in that be also formed with the second class on second conductive layer and lead
Bridge hole, the first electrode layer are covered on second conductive layer.
7. array substrate according to claim 5, which is characterized in that first kind conductive bridge hole at least two.
8. array substrate according to claim 6, which is characterized in that the second class conductive bridge hole at least two.
9. according to array substrate described in any one of claim 4-8, which is characterized in that the liquid crystal layer has a medium system
Number, the medium coefficient includes the dielectric coefficient of parallel vector and the dielectric coefficient of vertical vector.
10. a kind of display panel, which is characterized in that including any one of colored filter substrate, driver and claim 1-9
The array substrate.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811447419.6A CN109298575A (en) | 2018-11-29 | 2018-11-29 | Array substrate and display panel |
| PCT/CN2019/071067 WO2020107663A1 (en) | 2018-11-29 | 2019-01-10 | Array substrate and display panel |
| US17/260,225 US11119369B1 (en) | 2018-11-29 | 2019-01-10 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811447419.6A CN109298575A (en) | 2018-11-29 | 2018-11-29 | Array substrate and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN109298575A true CN109298575A (en) | 2019-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811447419.6A Pending CN109298575A (en) | 2018-11-29 | 2018-11-29 | Array substrate and display panel |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491160A (en) * | 2018-11-29 | 2019-03-19 | 惠科股份有限公司 | Array substrate, display panel and array substrate manufacturing method |
| US11119369B1 (en) | 2018-11-29 | 2021-09-14 | HKC Corporation Limited | Array substrate and display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103472606A (en) * | 2013-09-27 | 2013-12-25 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display device |
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| CN109491160A (en) * | 2018-11-29 | 2019-03-19 | 惠科股份有限公司 | Array substrate, display panel and array substrate manufacturing method |
| US11119369B1 (en) | 2018-11-29 | 2021-09-14 | HKC Corporation Limited | Array substrate and display panel |
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Application publication date: 20190201 |