CN109491160A - Array substrate, display panel and array substrate manufacturing method - Google Patents
Array substrate, display panel and array substrate manufacturing method Download PDFInfo
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- CN109491160A CN109491160A CN201811445306.2A CN201811445306A CN109491160A CN 109491160 A CN109491160 A CN 109491160A CN 201811445306 A CN201811445306 A CN 201811445306A CN 109491160 A CN109491160 A CN 109491160A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
This application involves a kind of array substrate, display panel and array substrate manufacturing methods, wherein, array substrate includes: the first substrate at least set gradually under, the first conductive layer, the first passivation layer, the second conductive layer, the second passivation layer, first electrode layer, liquid crystal layer, the second electrode lay and the second substrate, the first passivation layer covering part first substrate；Second the first passivation layer of passivation layer covering part；The first conductive layer of first electrode layer covering part, the first passivation layer, the second conductive layer and the second passivation layer；First conductive layer includes a plurality of first cabling, and the second conductive layer includes a plurality of the second cabling corresponding with each first cabling, wherein each first cabling connects corresponding second cabling by the cabling of corresponding first electrode layer；Target area is provided on each first cabling, each second cabling is located inside corresponding target area in the projection on the first cabling being correspondingly connected with, and reduces capacitor between the load and plate of gate driving circuit.
Description
Technical field
The present invention relates to field of display technology, make more particularly to a kind of array substrate, display panel and array substrate
Method.
Background technique
GOA (gate on array, gate drive circuit substrate) is an important technology in panel design, main excellent
Point is can to remove gate drive integrated circuit from, reduces product cost, and driver generates clock signal and is sent to gate driving electricity
Road, gate driving circuit provide clock signal by clock signal line and are given to each gate driving circuit with into line scans.
It is responsible for offer signal due to clock signal line and gives gate driving circuit, signal is not intended to make by these cablings certainly
At signal attenuation, general PSA (Polymer Sustained Alignment, polymerization macromolecule auxiliary orientation) mode and VA
Under (Vertical Alignment, perpendicular alignmnet) both of which, the signal resistance and signal capacitor of clock signal line are all fallen within
How the wherein one or both ends of active switch solve the problems, such as gate driving circuit load excessive, become important topic.
Summary of the invention
In order to solve the problems, such as gate drive circuit load excessive, the object of the present invention is to provide a kind of array substrate,
Display panel and array substrate manufacturing method.
On the one hand, the embodiment of the invention provides a kind of array substrates, comprising:
First substrate；The first conductive layer being formed on first substrate；The first passivation layer being formed on the first conductive layer,
And the first passivation layer covering part first substrate；The second conductive layer being formed on the first passivation layer；It is formed in the second conductive layer
On the second passivation layer, and second the first passivation layer of passivation layer covering part；Formation and the first electrode layer on the second passivation layer,
The first conductive layer of first electrode layer covering part, the first passivation layer, the second conductive layer and the second passivation layer；It is formed in first electrode
Liquid crystal layer on layer；The second electrode lay being formed on liquid crystal layer；The second substrate being formed on the second electrode lay；
First conductive layer includes a plurality of first cabling, and the second conductive layer includes a plurality of corresponding with each first cabling second walking
Line, wherein each first cabling connects corresponding second cabling by the cabling of corresponding first electrode layer；
Target area is provided on each first cabling, projection of each second cabling on the first cabling being correspondingly connected with is located at
Inside corresponding target area, target area is for reducing the region of capacitor between the first cabling and the second electrode lay, target
Region is for reducing the region of capacitor between the first cabling and the second electrode lay.
The first passivation layer is in target area covering part first substrate in one of the embodiments,.
Target area is filled with non-conducting material in one of the embodiments,.
First kind conductive bridge hole, first electrode layer covering are formed on the first conductive layer in one of the embodiments,
In on the first conductive layer.
The second class conductive bridge hole is also formed on the second conductive layer in one of the embodiments, first electrode layer is covered
It is placed on the second conductive layer.
First kind conductive bridge hole at least two in one of the embodiments,.
Second class conductive bridge hole at least two in one of the embodiments,.
Liquid crystal layer has a medium coefficient in one of the embodiments, and medium coefficient includes the dielectric system of parallel vector
Several dielectric coefficients with vertical vector.
A kind of display panel, including colored filter substrate, driver and above-mentioned array substrate.
A kind of array substrate manufacturing method, comprising:
First substrate is provided；The first conductive layer is formed on the first substrate；The first passivation layer is formed on the first conductive layer,
And make the first passivation layer covering part first substrate；The second conductive layer is formed on the first passivation layer；On the second conductive layer
The second passivation layer is formed, and makes second the first passivation layer of passivation layer covering part；First electrode is formed on the second passivation layer
Layer, and make the first conductive layer of first electrode layer covering part, the first passivation layer, the second conductive layer and the second passivation layer；?
Liquid crystal layer is formed on one electrode layer；The second electrode lay is formed on liquid crystal layer；The second substrate is formed on the second electrode layer；
A plurality of first cabling is formed on the first conductive layer, is formed on the second conductive layer a plurality of corresponding with each first cabling
The second cabling, wherein each first cabling connects corresponding second cabling by the cabling of corresponding first electrode layer；
Hole is formed on the first cabling, the second cabling is located inside the region of hole in the projection on the first cabling.
One or more embodiment provided by the invention at least has the advantages that wherein the embodiment of the present invention mentions
A kind of array substrate supplied successively includes first substrate, the first conductive layer, the first passivation layer, the second conductive layer, the from the bottom to top
Two passivation layers, first electrode layer, layer of non-conductive material, liquid crystal layer and the second electrode lay and the second substrate, wherein first is conductive
Layer includes a plurality of first cabling, and the second conductive layer includes a plurality of the second cabling corresponding with each first cabling, wherein each first walks
Line connects corresponding second cabling by the cabling of corresponding first electrode layer；It is provided with target area on each first cabling, respectively
Second cabling is located inside corresponding target area in the projection on the first cabling being correspondingly connected with.By on the first cabling and
Corresponding second cabling bridging overlapping place's setting target area, reduces the capacitor between the first conductive layer and the second electrode lay, from
And reduce circuit load.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of display panel in one embodiment；
Fig. 2 is capacitive load circuit schematic diagram in an example；
Fig. 3 is the structural schematic diagram of array substrate in one embodiment；
Fig. 4 is the cross-sectional view of array substrate in another embodiment.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing
Give preferred embodiment of the invention.But the invention can be realized in many different forms, however it is not limited to this paper institute
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
It should be noted that it can be directly to separately when an element is considered as " connection " another element
One element and it is in combination be integrated, or may be simultaneously present centering elements.Term as used herein " installation ", " one
End ", " other end " and similar statement are for illustrative purposes only.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the listed item of pass.
As shown in Figure 1, using GOA (gate on array, gate drive circuit substrate) technology there is gate array to drive
Dynamic display panel, including colored filter substrate 10, array substrate 20, driver 30 and gate driving circuit 40, by adopting
It is produced in array substrate 20 with gate driving circuit 40, instead of the driving chip made by external silicon chip to drive film brilliant
The on-off of body pipe.Since GOA (gate on array, gate drive circuit substrate) technology can be directly in the aobvious of display panel
Show setting gate driving circuit 40 around region, simplifies production process, the degree of integration of display panel is improved, so that display panel can
To realize ultrathin design.
When carrying out gate drive using gate driving circuit, capacitive load circuit is as shown in Fig. 2, the clock that driver is sent
Voltage signal 100 is sent to active switch through signal line, signal resistance 200 caused by signal line, signal capacitor 300 and parallel connection
Shunt capacitance 400 between the control terminal b of active switch and the first end a of active switch 500.Signal resistance 200, signal electricity
Appearance 300 and shunt capacitance 400 are all fallen on first end a and control terminal b, and circuit load is overweight, influences clock signal laser propagation effect.
In order to solve the above-mentioned technical problem, the embodiment of the invention provides a kind of array substrates, as shown in Figure 3 and Figure 4, battle array
Column substrate, comprising: first substrate 1；The first conductive layer 2 being formed on first substrate 1；Be formed on the first conductive layer 2
One passivation layer 3, and 3 covering part first substrate 1 of the first passivation layer；The second conductive layer 4 being formed on the first passivation layer 3；Shape
At in the second passivation layer 5 on the second conductive layer 4, and 5 the first passivation layer of covering part 3 of the second passivation layer；It is formed and second blunt
Change the first electrode layer 6 on layer 5,6 covering part the first conductive layer 2 of first electrode layer, the first passivation layer 3,4 and of the second conductive layer
Second passivation layer 5；The liquid crystal layer 7 being formed in first electrode layer 6；The second electrode lay 8 being formed on liquid crystal layer 7；It is formed in
The second substrate 9 on the second electrode lay 8；First conductive layer 2 include a plurality of first cabling 21, the second conductive layer 4 include it is a plurality of with
Corresponding second cabling 41 of each first cabling 21, wherein each first cabling 21 is connected by the cabling of corresponding first electrode layer 6
Corresponding second cabling 41；Target area 91 is provided on each first cabling 21, each second cabling 41 is in first be correspondingly connected with
Projection on cabling 21 is located at corresponding 91 the inside of target area, and target area 91 is for reducing the first cabling 21 and the second electricity
The region of capacitor between pole layer 8.
Wherein, the target area 91 of the first cabling 21 refers to for reducing between the first cabling 21 and the second electrode lay 8
The region of capacitor.The first cabling 21 in target area 91 can be hollow out state, and the first cabling 21 in target area 91 is also
It can be set filled with non-conducting material in fluted, groove, to reduce capacitor between plate.This part i.e. in target area 91
First cabling 21 (can be solid metal, the hollow-out part etc. being also possible on the first cabling 21) with pair the second electrode lay
The capacitor formed between this first cabling of part 21 and the second electrode lay 8 that the capacitor C1 formed between 8 is less than outside target area.
Specific implementation be not limited only to this place for two examples.The embodiment of the present invention uses corresponding in the first cabling 21
Target area 91 is arranged in the overlapping region of second cabling 41, and the capacitance of gate driving circuit cabling is effectively reduced, and reduces gate
Driving circuit walks linear load and reduces platen power.
In one of the embodiments, as shown in Figure 3 and Figure 4, the first passivation layer 3 is in 91 covering part first of target area
Substrate 1.First passivation layer 3 has dug hole on 91 covering part first substrate 1 of target area, i.e. the first cabling 21, in the hole
Without conductive material, the first passivation layer 3 fills the partial region, and contacts with first substrate 1 at place, capacity plate antenna is reduced, to drop
The capacitance of low gate driving circuit cabling.
Target area 91 is filled with non-conducting material in one of the embodiments,.91 potting resin etc. in target area
Non-conducting material reduces capacitor between plate, to reduce the load of gate driving circuit cabling.
In one of the embodiments, as shown in Figure 3 and Figure 4, first kind conductive bridge is formed on the first conductive layer 2
Hole, first electrode layer 6 are covered on the first conductive layer 2.
In one of the embodiments, as shown in Figure 3 and Figure 4, the second class conductive bridge is also formed on the second conductive layer 4
Hole, first electrode layer 6 are covered on the second conductive layer 4.
In one of the embodiments, as shown in Figure 3 and Figure 4, first kind conductive bridge hole at least two.
In one of the embodiments, as shown in Figure 3 and Figure 4, the second class conductive bridge hole at least two.
Liquid crystal layer 7 has a medium coefficient in one of the embodiments, and medium coefficient includes the dielectric system of parallel vector
Several dielectric coefficients with vertical vector.First kind conductive bridge hole is formed on each first cabling 21, and simultaneously by first electrode
Layer 6 is covered on the first conductive layer 2, through conductive bridge hole transmission voltage signal in first electrode layer 6 and the second electrode lay 8,
Thus approaching the medium coefficient of liquid crystal layer 7 is that the dielectric coefficient of parallel vector (citing: is controlled by voltage signal size and is situated between
The gradient in electrostrictive coefficient direction), and effectively further decrease the capacitance of gate driving circuit cabling.Similarly, it is walked each second
The second class conductive bridge hole is formed on line 41, and the second electrode lay 8 is covered on the second conductive layer 4 simultaneously, through conducting bridge
Hole transmission voltage signal is connect in the second electrode lay 8 and the second electrode lay 8, thus approaches the medium coefficient of liquid crystal layer 7 and is
The dielectric coefficient (citing: by the gradient in voltage signal size control dielectric coefficient direction) of parallel vector, and effectively further
Reduce the capacitance of gate driving circuit cabling.
A kind of display panel, as Figure 1 and Figure 4, including colored filter substrate 10, driver 30 and above-mentioned array base
Plate 20.Display panel provided in an embodiment of the present invention, the clock signal that driver 30 generates are given to first in array substrate 20
Target is arranged on corresponding first cabling 21 of each second cabling 40 to drive thin film transistor (TFT) in cabling 21 and the second cabling 41
Region 91, so that second cabling 41 is fallen in the target area 91 in the projection on the first cabling 21, i.e., so that the second cabling
The capacitor at the overlapping place of 41 first cablings 21 connected to it minimizes, to reduce the capacitor of 40 cabling of gate driving circuit
Value reduces platen power.
A kind of array substrate manufacturing method, comprising:
First substrate is provided；The first conductive layer is formed on the first substrate；The first passivation layer is formed on the first conductive layer,
And make the first passivation layer covering part first substrate；The second conductive layer is formed on the first passivation layer；On the second conductive layer
The second passivation layer is formed, and makes second the first passivation layer of passivation layer covering part；First electrode is formed on the second passivation layer
Layer, and make the first conductive layer of first electrode layer covering part, the first passivation layer, the second conductive layer and the second passivation layer；?
Liquid crystal layer is formed on one electrode layer；The second electrode lay is formed on liquid crystal layer；The second substrate is formed on the second electrode layer；?
A plurality of first cabling is formed on one conductive layer, and a plurality of the second cabling corresponding with each first cabling is formed on the second conductive layer,
Wherein, each first cabling connects corresponding second cabling by the cabling of corresponding first electrode layer；It is formed on the first cabling
There is hole, the second cabling is located inside the region of hole in the projection on the first cabling.It should be noted that the name in the present embodiment
Word paraphrase is same with the above-mentioned embodiment, and working principle is also identical, and this will not be repeated here.
In some embodiments in this application, display panel may include liquid crystal display panel, and wherein liquid crystal display panel can wrap
Switching array substrate is included, colorized optical filtering laminar substrate and the liquid crystal layer being formed between two substrates, display panel can also be OLED
(Organic Light-Emitting Diode, Organic Electricity laser display) panel or QLED (Quantum Dot Light
Emitting Diodes, light emitting diode with quantum dots) panel.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of array substrate characterized by comprising
First substrate；
The first conductive layer being formed on the first substrate；
The first passivation layer being formed on first conductive layer, and first substrate described in the first passivation layer covering part；
The second conductive layer being formed on first passivation layer；
The second passivation layer being formed on second conductive layer, and the first passivation described in the second passivation layer covering part
Layer；
It is formed with the first electrode layer on second passivation layer, the first conductive layer described in the first electrode layer covering part,
First passivation layer, second conductive layer and second passivation layer；
The liquid crystal layer being formed in the first electrode layer；
The second electrode lay being formed on the liquid crystal layer；
The second substrate being formed on the second electrode lay；
First conductive layer includes a plurality of first cabling, and second conductive layer includes a plurality of corresponding with each first cabling
The second cabling, wherein each first cabling connects corresponding second cabling by the cabling of corresponding first electrode layer；
Target area is provided on each first cabling, each second cabling is on first cabling being correspondingly connected with
Projection is located inside the corresponding target area, and the target area is for reducing between the first cabling and the second electrode lay
The region of capacitor.
2. array substrate according to claim 1, which is characterized in that first passivation layer is covered in the target area
The part first substrate.
3. array substrate according to claim 1, which is characterized in that the target area is filled with non-conducting material.
4. array substrate according to any one of claim 1-3, which is characterized in that be formed on first conductive layer
First kind conductive bridge hole, the first electrode layer are covered on first conductive layer.
5. array substrate according to claim 4, which is characterized in that be also formed with the second class on second conductive layer and lead
Bridge hole, the first electrode layer are covered on second conductive layer.
6. array substrate according to claim 4, which is characterized in that first kind conductive bridge hole at least two.
7. array substrate according to claim 5, which is characterized in that the second class conductive bridge hole at least two.
8. according to array substrate described in any one of claim 5-7, which is characterized in that the liquid crystal layer has a medium system
Number, the medium coefficient includes the dielectric coefficient of parallel vector and the dielectric coefficient of vertical vector.
9. a kind of display panel, which is characterized in that including any one of colored filter substrate, driver and claim 1-8
The array substrate.
10. a kind of array substrate manufacturing method characterized by comprising
First substrate is provided；The first conductive layer is formed on the first substrate；It is blunt that first is formed on first conductive layer
Change layer, and makes first substrate described in the first passivation layer covering part；It is conductive that second is formed on first passivation layer
Layer；The second passivation layer is formed on the second conductive layer, and makes the first passivation described in the second passivation layer covering part
Layer；First electrode layer is formed on second passivation layer, and makes the first conduction described in the first electrode layer covering part
Layer, first passivation layer, second conductive layer and second passivation layer；Liquid crystal is formed in the first electrode layer
Layer；The second electrode lay is formed on the liquid crystal layer；The second substrate is formed on the second electrode lay；
A plurality of first cabling is formed on first conductive layer, is formed on the second conductive layer a plurality of with each described first
Corresponding second cabling of cabling, wherein each first cabling connects corresponding the by the cabling of corresponding first electrode layer
Two cablings；
Hole is formed on first cabling, second cabling is where the projection on first cabling is located at the hole
Inside region.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811445306.2A CN109491160A (en) | 2018-11-29 | 2018-11-29 | Array substrate, display panel and array substrate manufacturing method |
| PCT/CN2019/071067 WO2020107663A1 (en) | 2018-11-29 | 2019-01-10 | Array substrate and display panel |
| US17/260,225 US11119369B1 (en) | 2018-11-29 | 2019-01-10 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811445306.2A CN109491160A (en) | 2018-11-29 | 2018-11-29 | Array substrate, display panel and array substrate manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109491160A true CN109491160A (en) | 2019-03-19 |
Family
ID=65698668
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811445306.2A Pending CN109491160A (en) | 2018-11-29 | 2018-11-29 | Array substrate, display panel and array substrate manufacturing method |
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| CN (1) | CN109491160A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103472606A (en) * | 2013-09-27 | 2013-12-25 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display device |
| CN108363248A (en) * | 2018-03-08 | 2018-08-03 | 惠科股份有限公司 | Display panel and its method for reducing capacitive load |
| CN109298575A (en) * | 2018-11-29 | 2019-02-01 | 惠科股份有限公司 | Array substrate and display panel |
-
2018
- 2018-11-29 CN CN201811445306.2A patent/CN109491160A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103472606A (en) * | 2013-09-27 | 2013-12-25 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display device |
| CN108363248A (en) * | 2018-03-08 | 2018-08-03 | 惠科股份有限公司 | Display panel and its method for reducing capacitive load |
| CN109298575A (en) * | 2018-11-29 | 2019-02-01 | 惠科股份有限公司 | Array substrate and display panel |
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Application publication date: 20190319 |