CN109427568A - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN109427568A CN109427568A CN201710757481.4A CN201710757481A CN109427568A CN 109427568 A CN109427568 A CN 109427568A CN 201710757481 A CN201710757481 A CN 201710757481A CN 109427568 A CN109427568 A CN 109427568A
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- workfunction layers
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 53
- 238000000576 coating method Methods 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 29
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 239000004411 aluminium Substances 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 145
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 12
- 239000013078 crystal Substances 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 10
- 230000006870 function Effects 0.000 description 10
- 239000012212 insulator Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 229910052593 corundum Inorganic materials 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 description 4
- -1 Nitrogen ion Chemical class 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910017121 AlSiO Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910004490 TaAl Inorganic materials 0.000 description 2
- 229910010252 TiO3 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, which comprises provides semiconductor substrate；High k dielectric layer is formed on the semiconductor substrate；Coating or workfunction layers are formed in the high k dielectric layer；Ion implanting is executed to the coating or workfunction layers；Metal gates are formed on the coating or workfunction layers.The production method of the semiconductor devices provided according to the present invention, by executing ion implanting after forming coating or workfunction layers, it is spread to avoid the metallic atom in the metal gates being subsequently formed, to improve the effective work function of semiconductor devices, and then improve the performance and reliability of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof.
Background technique
Main devices in integrated circuit (IC) especially super large-scale integration are metal oxide semiconductcor field effects
Transistor (MOS) is answered, with the maturation of semiconductor integrated circuit industrial technology increasingly, the rapid hair of ultra-large integrated circuit
Exhibition, with higher performance and the bigger component density of more powerful integrated circuit requirement, and between all parts, element or
Size, size and the space of each element itself are also required to further reduce.
For the CMOS with more advanced technology node, metal gates (high-k and metal after rear high k/
Gate last) technology has been widely used in cmos device, the damage to avoid high-temperature processing technology to device.In mesh
After preceding rear high k/ in metal gate technique, including boundary layer (IL) and high k (HK) dielectric layer is formed, then in high k dielectric layer
Upper deposition forms workfunction layers (WF) and metal gates (MG).
However, the material of metal gates is usually aluminium, therefore in existing rear high k dielectric layer/rear metal gate process
Aluminium atom diffusion easily occurs, aluminium atom is diffused into workfunction layers even high k dielectric layer, reduces the effective work function of device
(eWF), and then to influence the performance and reliability of device it is therefore prevented that the atom of metal gates spread be raising semiconductor device
The key of part performance.
Therefore, it is necessary to the production method for proposing a kind of new semiconductor devices, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of production method of semiconductor devices, comprising the following steps:
Semiconductor substrate is provided；
High k dielectric layer is formed on the semiconductor substrate；
Coating or workfunction layers are formed in the high k dielectric layer；
Ion implanting is executed to the coating or workfunction layers；
Metal gates are formed on the coating or workfunction layers.
Further, the ion of the ion implanting injection includes nitrogen or oxygen.
Further, the source gas of the ion implanting includes N2、N2O or NO, the energy of injection are 1keV-100keV, injection
Dosage be 1E11atom/cm2-1E15atom/cm2。
Further, the material of the metal gates includes aluminium.
Further, the coating or the material of workfunction layers include TiN.
The invention also includes a kind of semiconductor devices, comprising:
Semiconductor substrate；
High k dielectric layer is formed in the semiconductor substrate；
Coating or workfunction layers are formed in the high k dielectric layer, in the coating or workfunction layers
Doped with Doped ions；
Metal gates are formed in the coating or workfunction layers.
Further, the Doped ions include nitrogen or oxygen.
Further, the material of the metal gates includes aluminium.
Further, the coating or the material of workfunction layers include TiN.
The production method of the semiconductor devices provided according to the present invention, by formed coating or workfunction layers it
After execute ion implanting, spread to avoid the metallic atom in the metal gates being subsequently formed, to improve semiconductor
The effective work function of device, and then improve the performance and reliability of semiconductor devices.
Detailed description of the invention
The embodiment of the present invention is described in more detail in conjunction with the accompanying drawings, the above and other purposes of the present invention,
Feature and advantage will be apparent.Attached drawing is used to provide to further understand the embodiment of the present invention, and constitutes explanation
A part of book, is used to explain the present invention together with the embodiment of the present invention, is not construed as limiting the invention.In the accompanying drawings,
Identical reference label typically represents same parts or step.
In attached drawing:
Figure 1A -1E is the schematic cross section of the device obtained respectively the step of successively implementation according to the method for the present invention
Figure；
Fig. 2 is the schematic flow chart of the production method of semiconductor device according to the invention；
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiments.
For the CMOS with more advanced technology node, metal gates (high-k and metal after rear high k/
Gate last) technology has been widely used in cmos device, the damage to avoid high-temperature processing technology to device.In mesh
After preceding rear high k/ in metal gate technique, including boundary layer (IL) and high k (HK) dielectric layer is formed, then in high k dielectric layer
Upper deposition forms workfunction layers (WF) and metal gates (MG).
However, the material of metal gates is usually aluminium, therefore in existing rear high k dielectric layer/rear metal gate process
Aluminium atom diffusion easily occurs, aluminium atom is diffused into workfunction layers even high k dielectric layer, reduces the effective work function of device
(eWF), and then to influence the performance and reliability of device it is therefore prevented that the atom of metal gates spread be raising semiconductor device
The key of part performance.
Therefore, it is necessary to the production method for proposing a kind of new semiconductor devices, to solve the above problems.
In view of the above-mentioned problems, the present invention provides a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided；
High k dielectric layer is formed on the semiconductor substrate；
Coating or workfunction layers are formed in the high k dielectric layer；
Ion implanting is executed to the coating or workfunction layers；
Metal gates are formed on the coating or workfunction layers.
Wherein, the ion of the ion implanting injection includes nitrogen or oxygen；The source gas of the ion implanting includes N2、N2O or
NO, the energy of injection are 1keV-100keV, and the dosage of injection is 1E11atom/cm2-1E15atom/cm2；The metal gates
Material include aluminium；The coating or the material of workfunction layers include TiN.
The production method of the semiconductor devices provided according to the present invention, by formed coating or workfunction layers it
After execute ion implanting, spread to avoid the metallic atom in the metal gates being subsequently formed, to improve semiconductor
The effective work function of device, and then improve the performance and reliability of semiconductor devices.
It is described in detail below with reference to preparation method of Figure 1A -1E and Fig. 2 to semiconductor devices of the present invention.Its
In, the schematic cross sectional view for the device that the step of Figure 1A -1E is successively implemented for method according to the present invention obtains respectively；Fig. 2
It is the schematic flow chart of the production method of semiconductor device according to the invention.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Fig. 2, the key step packet of the preparation method
It includes:
S201: semiconductor substrate is provided；
S202: high k dielectric layer is formed on the semiconductor substrate；
S203: coating or workfunction layers are formed in the high k dielectric layer；
S204: ion implanting is executed to the coating or workfunction layers；
S205: metal gates are formed on the coating or workfunction layers.
In the following, being described in detail to the specific embodiment of the production method of semiconductor devices of the invention.
Firstly, executing step S201 provides semiconductor substrate 100 as shown in Figure 1A.
Illustratively, in the present invention the semiconductor substrate 100 can be in the following material being previously mentioned at least one
Kind: monocrystalline silicon, silicon-on-insulator (SOI), be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Isolation junction is also formed in semiconductor substrate 100
Structure, the isolation structure are shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure, and isolation structure will
Semiconductor substrate 100 is divided for different active areas, can form various semiconductor devices, such as NMOS and PMOS in active area
Deng.Various traps (well) structure is also formed in semiconductor substrate 100, to put it more simply, being omitted in diagram.
Next, step S202 is executed, as shown in Figure 1, forming high k dielectric layer 102 in the semiconductor substrate 100.
Illustratively, boundary can also be formed in the semiconductor substrate 100 before forming the high k dielectric layer 102
Surface layer 101.Boundary layer (IL) can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or other suitable film layers.
Boundary layer 101 can be formed using CVD, ALD or PVD etc. suitable technique.The thickness range of boundary layer 101 is 5 angstroms to 10
Angstrom.
Illustratively, deposition forms high k (HK) dielectric layer 102 on the boundary layer 101.The material of high k dielectric layer 102
Including but not limited to LaO, BaZrO, AlO, HfO2、HfZrO、HfZrON、HfLaO、HfSiON、HfSiO、LaSiO、AlSiO、
HfTaO, HfTiO, (Ba, Sr) TiO3(BST)、Al2O3、Si3N4, nitrogen oxides or other suitable materials, in the present invention,
The high k dielectric layer 102 can be HfO2Layer.High k dielectric layer can be formed using the suitable technique such as CVD, ALD or PVD
102.The thickness range of high k dielectric layer 102 is 10 angstroms to 30 angstroms.
Next, executing step S203, as shown in Figure 1A, coating 103 is formed in the high k dielectric layer 102.
Illustratively, deposition forms coating 103 in high k dielectric layer 102, and the material of coating 103 includes but unlimited
In La2O3、Al2O3、Ga2O3、In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TixN1-xOr other suitable films
Layer, in the present invention, the coating 103 are TiN layer.Covering can be formed using CVD, ALD or PVD etc. suitable technique
Layer 103.The thickness range of coating 103 is 5 angstroms to 20 angstroms.
Next, executing step S204, as shown in Figure 1B, the first ion implanting is executed to the coating 103.
Illustratively, the ion for executing the injection of the first ion implanting includes nitrogen or oxygen.In the present invention, the ion of injection is
Nitrogen ion, the source gas of N~+ implantation are N2, N2O or NO, the energy of the N~+ implantation are 1keV-100keV, dosage
For 1E11atom/cm2-1E15atom/cm2。
First ion implanting is executed to coating 103, the ion of injection is gathered in 102 boundary of coating 103 and high k dielectric layer
Near face, to prevent the metallic atom in the metal gates being subsequently formed from spreading to high k dielectric layer 102.In addition, above-mentioned steps
The TiN formed in S203 has columnar crystal structure, and the aluminium atom in metal gates being subsequently formed easily passes through columnar
Gap between crystal structure enters in the high k dielectric layer 102 below TiN layer, so as to cause the drop of the effective work function of device
Low, the ion of the above-mentioned first ion implanting injection of the present invention can also destroy the crystal structure of TiN in coating 103, mix simultaneously
Gap of the miscellaneous ion between the columnar crystal structure, to effectively avoid the downward diffusion of aluminium atom.
Then, step S203 is executed, as shown in Figure 1 C, forms workfunction layers 105 in the high k dielectric layer 102.
Illustratively, barrier layer 104 can also be formed on coating 103 before forming workfunction layers 105, is hindered
The material of barrier 104 includes but is not limited to TaN, Ta, TaAl or other suitable film layers.Can using CVD, ALD or
PVD etc. suitable technique forms barrier layer 104.The thickness range on barrier layer 104 is 5 angstroms to 20 angstroms.
Illustratively, deposition forms workfunction layers 105 on barrier layer 104, and workfunction layers 105 include p-type
Workfunction layers (PWF).The material of workfunction layers 105 includes but is not limited to TixN1-x, TaC, MoN, TaN or other
Suitable film layer, in the present invention, the workfunction layers 105 are TiN layer.It can be suitable using CVD, ALD or PVD etc.
The technique of conjunction forms workfunction layers 105.The thickness range of workfunction layers 105 is 10 angstroms to 580 angstroms.
Next, executing step S204, as shown in figure iD, the second ion implanting is executed to the workfunction layers 105.
Illustratively, the ion for executing the injection of the second ion implanting includes nitrogen or oxygen.In the present invention, the ion of injection is
Nitrogen ion, the source gas of N~+ implantation are N2, N2O or NO, the energy of the N~+ implantation are 1keV-100keV, dosage
For 1E11atom/cm2-1E15atom/cm2。
Second ion implanting is executed to workfunction layers 105, the ion of injection is gathered in workfunction layers 105 and resistance
Near 104 interface of barrier, to prevent the metallic atom in the metal gates being subsequently formed from spreading to barrier layer 104.In addition, above-mentioned
The TiN formed in step S203 has columnar crystal structure, and the aluminium atom in metal gates being subsequently formed easily passes through column
Gap between the crystal structure of shape enters in the barrier layer 104 below TiN layer, so as to cause the drop of the effective work function of device
Low, the ion of the above-mentioned second ion implanting injection of the present invention can also destroy the crystal structure of TiN in workfunction layers 105,
Gap of the ion of doping between the columnar crystal structure simultaneously, to effectively avoid the downward diffusion of aluminium atom.
It should be noted that in the present invention, executing the first ion implanting to coating 103 and to workfunction layers
The step of 105 the second ion implanting of execution, can select an execution or all execute, that is, in the present invention, including to coating 103
The step of executing the first ion implanting and/or the second ion implanting executed to workfunction layers 105.
It is formed on the coating 103 or workfunction layers 105 as referring to figure 1E next, executing step S205
Metal gates 106.
Illustratively, separation layer (not shown) can also be formed before forming metal gates 106.The material of separation layer
Including but not limited to TaN, TiN, Ti or other suitable film layers.The technique that can be suitble to using CVD, ALD or PVD etc.
Form separation layer.
Illustratively, metal gates 106 are formed on the coating 103 or workfunction layers 105, metal gates
Material includes but is not limited to Al, W or other suitable film layers, and in the present invention, the metal gates are Al layers.It can adopt
Metal gates 106 are formed with the technique that CVD, ALD or PVD etc. are suitble to.
The present invention also provides a kind of semiconductor devices, 1E with reference to the accompanying drawing, to semiconductor devices provided by the invention
Structure is described.The semiconductor devices includes semiconductor substrate 100, high k dielectric layer 102, the covering doped with Doped ions
Layer 103 or workfunction layers 105, metal gate grade 106.Wherein:
Semiconductor substrate 100 can be following at least one of the material being previously mentioned: monocrystalline silicon, silicon-on-insulator
(SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..Isolation structure, the isolation structure are also formed in semiconductor substrate 100
Semiconductor substrate 100 is divided for shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure, isolation structure
For different active areas, various semiconductor devices, such as NMOS and PMOS etc. can be formed in active area.In semiconductor substrate
Various traps (well) structure is also formed in 100, to put it more simply, being omitted in diagram.
High k dielectric layer 102 is formed in the semiconductor substrate 100.
Illustratively, interfacial TCO layer can also be formed between the semiconductor substrate 100 and the high k dielectric layer 102
101.Boundary layer (IL) can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or other suitable film layers.
Illustratively, the material of high k dielectric layer 102 includes but is not limited to LaO, BaZrO, AlO, HfO2、HfZrO、
HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3(BST)、Al2O3、Si3N4、
Nitrogen oxides or other suitable materials, in the present invention, the high k dielectric layer 102 can be HfO2Layer.
Coating 103 or workfunction layers 105, the coating 103 or function are formed in the high k dielectric layer 102
Doped with Doped ions in function metal 105.
Illustratively, the material of coating 103 includes but is not limited to La2O3、Al2O3、Ga2O3、In2O3、MoO、Pt、Ru、
TaCNO、Ir、TaC、MoN、WN、TixN1-xOr other suitable film layers, in the present invention, the coating 103 is TiN
Layer.
Illustratively, can also form barrier layer 104 on the coating 103, the material on the barrier layer 104 include but
It is not limited to TaN, Ta, TaAl or other suitable film layers.
Illustratively, workfunction layers 105 are p-type workfunction layers (PWF), the material of workfunction layers 105
Including but not limited to TixN1-x, TaC, MoN, TaN or other suitable film layers.In the present invention, the workfunction metal
Layer 105 is TiN layer.
Illustratively, doped with Doped ions, the Doped ions in the coating 103 or workfunction layers 105
Including nitrogen or oxygen, in the present invention, Doped ions include nitrogen.Doped ions are gathered in coating 103 or workfunction layers 105
Near the interface of lower section film layer, to prevent the metallic atom in the metal gates being subsequently formed, film layer is spread downwards.In addition,
TiN before above-mentioned doping has columnar crystal structure, and the aluminium atom in metal gates 106 easily passes through columnar crystal structure
Between gap enter in the lower section film layer below TiN layer, so as to cause the reduction of the effective work function of device, the present invention is above-mentioned
Between Doped ions can also destroy the crystal structure of TiN, while the ion adulterated is between the columnar crystal structure
Gap, to effectively avoid the downward diffusion of aluminium atom.
Metal gates 106 are formed in the coating 103 or workfunction layers 105.
Illustratively, can also be formed between metal gates 106 and coating 103 or workfunction layers 105 every
Absciss layer (not shown).The material of separation layer includes but is not limited to TaN, TiN, Ti or other suitable film layers.
Illustratively, the material of metal gates 106 includes but is not limited to Al, W or other suitable film layers, in this hair
In bright, the material of the metal gates is aluminium.
The production method of the semiconductor devices provided according to the present invention, by formed coating or workfunction layers it
After execute ion implanting, spread to avoid the metallic atom in the metal gates being subsequently formed, to improve semiconductor
The effective work function of device, and then improve the performance and reliability of semiconductor devices.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of production method of semiconductor devices, which comprises the following steps:
Semiconductor substrate is provided；
High k dielectric layer is formed on the semiconductor substrate；
Coating or workfunction layers are formed in the high k dielectric layer；
Ion implanting is executed to the coating or workfunction layers；
Metal gates are formed on the coating or workfunction layers.
2. the method according to claim 1, wherein the ion of ion implanting injection includes nitrogen or oxygen.
3. the method according to claim 1, wherein the source gas of the ion implanting includes N2、N2O or NO, note
The energy entered is 1keV-100keV, and the dosage of injection is 1E11atom/cm2-1E15atom/cm2。
4. the method according to claim 1, wherein the material of the metal gates includes aluminium.
5. the method according to claim 1, wherein the coating or the material of workfunction layers include
TiN。
6. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
High k dielectric layer is formed in the semiconductor substrate；
It is formed with coating or workfunction layers in the high k dielectric layer, is adulterated in the coating or workfunction layers
There are Doped ions；
Metal gates are formed in the coating or workfunction layers.
7. semiconductor devices according to claim 6, which is characterized in that the Doped ions include nitrogen or oxygen.
8. semiconductor devices according to claim 6, which is characterized in that the material of the metal gates includes aluminium.
9. semiconductor devices according to claim 6, which is characterized in that the material of the coating or workfunction layers
Including TiN.
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