CN109413851B - Optimization method for preparing printed circuit board - Google Patents
Optimization method for preparing printed circuit board Download PDFInfo
- Publication number
- CN109413851B CN109413851B CN201811573565.3A CN201811573565A CN109413851B CN 109413851 B CN109413851 B CN 109413851B CN 201811573565 A CN201811573565 A CN 201811573565A CN 109413851 B CN109413851 B CN 109413851B
- Authority
- CN
- China
- Prior art keywords
- printed circuit
- line width
- circuit board
- outer film
- condition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09281—Layout details of a single conductor
Abstract
The invention provides an optimization method for preparing a printed circuit board, which optimizes the printed circuit board with low qualification rate by obtaining the preparation qualification rate of the printed circuit boards with different line lengths and intervals, and comprises the following steps: aiming at a printed circuit board with the circuit length of more than 20 mm, the spacing of less than 0.15mm and the finished copper thickness of 0.8 ounce to 1.2 ounces, under the condition that the line width of an outer film is less than 0.15mm, the line width is not subjected to pre-large compensation; reducing the line width of the circuit by 4-6% under the condition that the line width of the outer film is 0.2-0.3 mm; and reducing the line width of the circuit by 10-15% under the condition that the line width of the outer layer film is greater than 0.3 mm. The optimization method can optimize the preparation quality of the long circuit board, can improve the qualification rate of the long circuit board by more than 20 percent, reduce the rejection rate by more than 10 percent, and can save the cost by at least 60 yuan for each square meter of the long circuit board.
Description
Technical Field
The invention relates to the field of printed circuit board preparation, in particular to an optimization method for preparing a printed circuit board.
Background
The problems of difficult manufacture, low qualification rate, high rejection rate and the like exist in the outer layer circuit and electroplating process of the conventional printed circuit board with long circuit and fine spacing.
Disclosure of Invention
In view of the deficiencies in the prior art, it is an object of the present invention to address one or more of the problems in the prior art as set forth above. For example, an object of the present invention is to provide a printed circuit board optimization method that can improve the yield of printed circuit boards.
In order to achieve the above object, the present invention provides an optimization method for manufacturing a printed circuit board, which may include optimizing a printed circuit board with a low yield by obtaining yields of printed circuit boards with different line lengths and pitches, and specifically, the optimization method may further include the steps of: aiming at the printed circuit board with the circuit length of more than 20 mm, the spacing of less than 0.15mm and the finished copper thickness of 0.8 ounce to 1.2 ounces, under the condition that the outer film line width is less than 0.15mm, the line width of the printed circuit board with low qualification rate can not be subjected to pre-large compensation; under the condition that the line width of the outer film is 0.2-0.3 mm, the line width of the printed circuit board with low qualification rate can be reduced by 4-6%; and under the condition that the line width of the outer layer film is greater than 0.3mm, the line width of the printed circuit board with low qualification rate can be reduced by 10-15%.
In one exemplary embodiment of the optimized method for manufacturing a printed circuit board of the present invention, the printed circuit board may be a printed circuit board having a wire length of 20 mm to 40 mm, a pitch of 0.08 mm to 0.14 mm, and a finished copper thickness of 0.9 ounce to 1.15 ounces.
In an exemplary embodiment of the optimized method for manufacturing a printed circuit board of the present invention, the line width may not be compensated for a large amount in the case where the outer film line width is 0.07 mm to 0.13 mm.
In an exemplary embodiment of the optimized method for manufacturing a printed circuit board of the present invention, the line width of the line may be reduced by 10% to 15% in a case where the outer film line width is 0.4 mm to 0.9 mm.
In an exemplary embodiment of the optimized method for manufacturing a printed circuit board, the line width of the circuit can be reduced by 4.8% to 5.6% in the case that the line width of the outer film is 0.2mm to 0.3mm, and further, the line width can be reduced by 5.0%.
In an exemplary embodiment of the optimized method for manufacturing a printed circuit board of the present invention, in the case that the outer film line width is greater than 0.3mm, the line width may be reduced by 11.5% to 13%.
Compared with the prior art, the optimization method can optimize the preparation quality of the long-circuit printed circuit board, can improve the qualification rate of the long-circuit printed circuit board by more than 20 percent, reduce the rejection rate by more than 10 percent, and can save the cost of the long-circuit printed circuit board per square meter by at least 60 yuan.
Detailed Description
Hereinafter, an optimized method for manufacturing a printed wiring board according to the present invention will be described in detail with reference to exemplary embodiments.
The present invention provides an optimization method for manufacturing a printed wiring board, which, in one exemplary embodiment of the optimization method for manufacturing a printed wiring board of the present invention, may include the steps of:
and S01, for the printed circuit boards with different circuit lengths and different matching distances, counting the qualified rate of the printed circuit boards prepared by different parameters.
In this embodiment, the yield of the printed circuit board can be obtained by using the DOE experiment. The parameters used by the printed circuit board with higher qualification rate can be reused, and the repeatability of the printed circuit board can be verified in small batches. And optimizing the preparation parameters of the printed circuit board with lower qualification rate. And optimizing the preparation parameters of the printed circuit board with the qualification rate of below 60%.
S02, changing the preparation parameters and optimizing the preparation process of the low-yield printed circuit board in the step S01.
In this embodiment, when the quality of the printed circuit board with the circuit length greater than 20 mm and the pitch less than 0.15mm is poor, a large amount of diffusion plating, a dry film short circuit due to scratching, and the like may exist on the printed circuit board at this time. Therefore, it is necessary to optimize the manufacturing process of the printed wiring board of the above specifications.
For the printed circuit board with the circuit length of more than 20 mm, the spacing of less than 0.15mm and the finished copper thickness of 0.8 ounce to 1.2 ounce, when the line width of the outer film is less than 0.15mm, the line width of the long-circuit printed circuit board is not greatly compensated, so that the maximum spacing between the long-circuit printed circuit boards can be ensured, and the dry film adhesive force is best; when the line width of the outer film is between 0.2mm and 0.3mm, the line width of the long-circuit printed circuit board can be reduced by 4 to 6 percent on the basis of the original printed circuit board, so that the distance between the circuits can be increased by 4 to 6 percent on the basis of the original printed circuit board, the maximum distance between the long-circuit printed circuit boards can be ensured, and the dry film adhesive force is best; when the line width of the outer film is more than 0.3mm, the line width of the long-circuit printed circuit board can be reduced by 10% -15%, the distance between the circuits can be increased by 10% -15% on the original basis, and the distance between the long circuits can be ensured to be within 20% larger than original data given by a customer, so that the quality requirement of the customer is met, the production data is optimized, the adhesive force of a dry film is improved, and the reject ratio and the rejection rate of products are reduced.
In this embodiment, further, when the line width of the outer film is 0.2mm to 0.3mm, the line width may be reduced by 4.8% to 5.6%, and further, the line width may be reduced by 5%.
In this embodiment, further, in the case that the line width of the outer film is greater than 0.3mm, the line width may be reduced by 11.5% to 13%.
In this embodiment, the printed circuit board may be a printed circuit board with a circuit length of 20 mm to 40 mm, a pitch of 0.08 mm to 0.14 mm, and a finished copper thickness of 0.9 ounce to 1.15 ounce.
In this embodiment, further, the line width may not be compensated for a large amount in the case that the outer film line width is 0.07 mm to 0.13 mm.
In this embodiment, further, the line width of the circuit may be reduced by 10% to 15% when the outer film line width is 0.4 mm to 0.9 mm.
In conclusion, the optimization method can optimize the preparation quality of the long-circuit printed circuit board, can improve the qualification rate of the long-circuit printed circuit board by more than 20 percent, can reduce the rejection rate by more than 10 percent, and can save the cost by at least 60 yuan for each square meter of the long circuit board.
Although the present invention has been described above in connection with exemplary embodiments, it will be apparent to those skilled in the art that various modifications and changes may be made to the exemplary embodiments of the present invention without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (7)
1. An optimization method for preparing a printed circuit board optimizes the printed circuit board with low qualification rate by obtaining the preparation qualification rate of the printed circuit board with different circuit lengths and intervals, and is characterized by comprising the following steps:
aiming at the printed circuit board with the circuit length of more than 20 mm, the spacing of less than 0.15mm and the finished product copper thickness of 0.8 ounce to 1.2 ounce,
under the condition that the line width of the outer film is less than 0.15mm, the line width is not subjected to pre-large compensation;
under the condition that the line width of the outer film is 0.2-0.3 mm, the line width of the printed circuit board with low qualification rate is reduced by 4-6%;
and under the condition that the line width of the outer layer film is greater than 0.3mm, reducing the line width of the printed circuit board with low qualification rate by 10-15%.
2. The optimized method for manufacturing a printed wiring board according to claim 1, wherein the printed wiring board has a circuit length of 20 mm to 40 mm, a pitch of 0.08 mm to 0.14 mm, and a finished copper thickness of 0.9 ounce to 1.15 ounces.
3. The optimized method for manufacturing a printed circuit board according to claim 1, wherein the line width of the circuit is not greatly compensated for when the line width of the outer film is 0.07 mm to 0.13 mm.
4. The optimized method for manufacturing printed circuit boards according to claim 1, wherein the line width of the printed circuit board with low yield is reduced by 10% to 15% under the condition that the line width of the outer film is 0.4 mm to 0.9 mm.
5. The optimized method for manufacturing printed circuit boards according to claim 1, wherein the line width of the printed circuit board with low yield is reduced by 4.8-5.6% under the condition that the line width of the outer film is 0.2-0.3 mm.
6. The optimized method for manufacturing printed circuit boards according to claim 1, wherein the line width of the printed circuit board with low yield is reduced by 5% under the condition that the line width of the outer film is 0.2mm to 0.3 mm.
7. The optimized method for manufacturing a printed circuit board according to claim 1, wherein the line width of the printed circuit board with low qualification rate is reduced by 11.5-13% when the line width of the outer film is greater than 0.3 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811573565.3A CN109413851B (en) | 2018-12-21 | 2018-12-21 | Optimization method for preparing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811573565.3A CN109413851B (en) | 2018-12-21 | 2018-12-21 | Optimization method for preparing printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109413851A CN109413851A (en) | 2019-03-01 |
| CN109413851B true CN109413851B (en) | 2021-09-03 |
Family
ID=65460481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811573565.3A Active CN109413851B (en) | 2018-12-21 | 2018-12-21 | Optimization method for preparing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109413851B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106255325A (en) * | 2016-08-24 | 2016-12-21 | 山东蓝色电子科技有限公司 | A kind of special-shaped compensation method of the circuit pads considering etching factor |
| CN108024454A (en) * | 2017-12-14 | 2018-05-11 | 悦虎电路(苏州)有限公司 | A kind of line build-out method based on 1.5mil wiring boards |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4867904B2 (en) * | 2007-12-10 | 2012-02-01 | セイコーエプソン株式会社 | Conductor pattern forming ink, conductor pattern, conductor pattern forming method, and wiring board |
| KR101458854B1 (en) * | 2008-06-12 | 2014-11-07 | 삼성디스플레이 주식회사 | Flexible printed circuit board, method for manufacturing the same and display apparatus having the same |
-
2018
- 2018-12-21 CN CN201811573565.3A patent/CN109413851B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106255325A (en) * | 2016-08-24 | 2016-12-21 | 山东蓝色电子科技有限公司 | A kind of special-shaped compensation method of the circuit pads considering etching factor |
| CN108024454A (en) * | 2017-12-14 | 2018-05-11 | 悦虎电路(苏州)有限公司 | A kind of line build-out method based on 1.5mil wiring boards |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109413851A (en) | 2019-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102573309A (en) | Method for improving graphic precision of substractive process printed circuit board (PCB) by adopting dynamic etching compensation method | |
| CN103619125B (en) | A kind of PCB electro-plating method for improving electroplating evenness | |
| US20120111613A1 (en) | Copper foil with resistance layer, method of production of the same and laminated board | |
| KR102191545B1 (en) | How to obtain pattern plating parameters | |
| CN109413851B (en) | Optimization method for preparing printed circuit board | |
| US20240015885A1 (en) | Metal foil, metal foil with carrier comprising same, and printed circuit board comprising same | |
| CN110557886B (en) | Compensation method of Printed Circuit Board (PCB) cursor point, application of compensation method and PCB production process | |
| CN110418509B (en) | Circuit compensation method for meeting specific etching factor requirement of PCB | |
| CN110516199B (en) | Influence degree calculation method for influence factors of characteristic impedance and circuit board | |
| CN109496080B (en) | Circuit board electroplating process method | |
| US20120123574A1 (en) | Plating method of substrate and manufacturing method of circuit board using the same | |
| CN104105354A (en) | Method of manufacturing high-aperture ratio fine printed circuit board | |
| CN108200728A (en) | A kind of secondary dry film engraving method of PCB isolation patterns | |
| CN112654169A (en) | Manufacturing method of flexible circuit board with bending requirement | |
| CN102873974A (en) | Method for producing collapsible steel mesh | |
| CN103068176A (en) | Electroplating method for circuit board of precise circuit | |
| CN112654159A (en) | Method for automatically supplementing and correcting film | |
| CN109413871A (en) | A kind of production method on improved wet film circuit printed line road | |
| CN117460181B (en) | PCB manufacturing process with high copper plating uniformity | |
| CN112234025A (en) | Manufacturing method suitable for thick copper foil precision circuit | |
| KR20120035611A (en) | Laminated structure for a printed circuit board being prevented the formation of crack and manufacturing method the same | |
| CN111629520B (en) | Processing method for reducing thermal expansion of BGA area of printed circuit board | |
| CN108200729A (en) | A kind of PCB isolation patterns paving copper shunting second etch method | |
| CN111598383B (en) | Method, system and storage medium for predicting qualification rate influence degree of PCB order | |
| CN103203964A (en) | A production process for an electroformed stencil |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |