CN109411450B - 半导体封装装置和其制造方法 - Google Patents

半导体封装装置和其制造方法 Download PDF

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CN109411450B
CN109411450B CN201810132635.5A CN201810132635A CN109411450B CN 109411450 B CN109411450 B CN 109411450B CN 201810132635 A CN201810132635 A CN 201810132635A CN 109411450 B CN109411450 B CN 109411450B
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金锡奉
朴璿姝
陈亨俊
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Advanced Semiconductor Engineering Korea Inc
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Abstract

一种半导体封装装置，其包括衬底、裸片、囊封物和天线层。所述衬底具有顶表面和与所述顶表面相对的底表面。所述裸片安置在所述衬底的所述顶表面上。所述囊封物安置在所述衬底的所述顶表面上且环绕所述裸片。所述囊封物具有顶表面且界定所述囊封物的所述顶表面上的凹部。所述天线层安置在所述囊封物的所述顶表面上且在所述囊封物的所述顶表面上的所述凹部内延伸。

Description

半导体封装装置和其制造方法
技术领域
本公开涉及一种半导体封装装置和其制造方法，且更确切地说，涉及一种包含天线的半导体封装装置和其制造方法。
背景技术
例如手机等无线通信装置通常包含用于发射和接收射频(RF)信号的天线。在相当的做法中，无线通信装置包含各自安置在电路板的不同部分上的天线和通信模块。根据相当的做法，单独地制造天线和通信模块，且在将天线和通信模块放置在电路板上之后将其电连接到一起。因此，两个组件可能带来单独的制造成本。此外，可能难以减小无线通信设备的大小以达成合适紧凑型产品设计。此外，在一些类型的天线(例如，金属冲压天线)中，天线的形状易于变形，这是由于天线不够坚硬以承受模制化合物形成期间的压力。
发明内容
根据本公开的一些实施例，半导体封装装置包括衬底、裸片、囊封物和天线层。衬底具有顶表面和与顶表面相对的底表面。裸片安置在衬底的顶表面上。囊封物安置在衬底的顶表面上且环绕裸片。囊封物具有顶表面且界定囊封物的顶表面上的凹部。天线层安置在囊封物的顶表面上且在囊封物的顶表面上的凹部内延伸。
根据本公开的一些实施例，半导体封装装置包括衬底、裸片、封装体和天线层。衬底具有顶表面和与顶表面相对的底表面。裸片安置在衬底的顶表面上。封装体安置在衬底的顶表面上且环绕裸片。天线层安置在封装体的顶表面上，其中天线层界定凹部。
根据本公开的一些实施例，制造半导体封装装置的方法包括：(a)提供衬底条；(b)将裸片安置在衬底条上；(c)在衬底条上形成封装体以环绕裸片，(d)在封装体的顶表面上形成至少一个凹部；(e)切穿封装体和衬底条以将衬底条分离成个别衬底；以及(f)在封装体上形成天线层且使所述天线层在封装体的凹部内延伸。
附图说明
图1A说明根据本公开的一些实施例的半导体封装装置的截面视图。
图1B说明根据本公开的一些实施例的半导体封装装置的截面视图。
图2A说明根据本公开的一些实施例的半导体封装装置的截面视图。
图2B说明根据本公开的一些实施例的半导体封装装置的截面视图。
图2C说明根据本公开的一些实施例的半导体封装装置的截面视图。
图2D说明根据本公开的一些实施例的半导体封装装置的侧视图。
图2E说明根据本公开的一些实施例的半导体封装装置的侧视图。
图2F说明根据本公开的一些实施例的半导体封装装置的俯视图。
图3A、图3B、图3C和图3D说明根据本公开的一些实施例的半导体制造方法。
图4A和图4B说明根据本公开的一些实施例的半导体制造方法。
图5A和图5B说明根据本公开的一些实施例的半导体制造方法。
图6A、图6B、图6C、图6D和图6E说明根据本公开的一些实施例的半导体制造方法。
贯穿图式和详细描述使用共同参考标号来指示相同或类似组件。根据以下结合附图作出的详细描述，本公开将更显而易见。
具体实施方式
图1A说明根据本公开的一些实施例的半导体封装装置1A的截面视图。半导体封装装置1A包含衬底10、电子组件11a、11b、封装体12和金属层13。
衬底10可以是例如印刷电路板，例如纸质铜箔层合物、复合铜箔层合物，或聚合物浸渍的玻璃纤维类铜箔层合物。衬底10可包含相对表面101、102和在表面101、102之间延伸的侧表面103。在一些实施例中，衬底10的表面101被称作顶表面或第一表面，且衬底10的表面102被称作底表面或第二表面。衬底10可包含互连结构(例如，电连接)，例如重布层(RDL)10t或接地元件10g(或接地段)。
电子组件11a、11b安置在衬底10的顶表面101上。电子组件11a可以是有源组件，例如集成电路(IC)芯片或裸片。电子组件11b可为无源组件，例如电容器、电阻器或电感器。每个电子组件11a、11b可电连接到另一电子组件11a、11b中的一或多个且到衬底10(例如，到RDL 10t)，且可借助于倒装芯片或导线接合技术达成电连接。
封装体12(或囊封物)安置在衬底10的顶表面101上。封装体12具有或界定空腔12c，以容纳电子组件11a、11b。举例来说，封装体12界定电子组件11a、11b与封装体12之间的气隙。在一些实施例中，封装体12的侧表面123不与衬底10的侧表面103对准或共面。也就是说，距离形成于封装体12的侧表面123与衬底10的侧表面103之间，且封装体12的侧表面123从衬底10的侧表面103朝内凹入。在一些实施例中，封装体12的侧表面123基本上垂直于封装体12的顶表面。在一些实施例中，封装体12包含：包含填料的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或酚类材料、其中分散有硅酮的材料，或其两种或多于两种的组合。
金属层13安置在衬底10的顶表面101和封装体12的外表面上。金属层13安置在衬底10的顶表面101上的电接触件10c(例如，传导垫)上。在一些实施例中，如果金属层13充当天线，那么金属层13(或天线层)通过衬底10内的RDL 10t电连接到电子组件11a或11b。与衬底10上的电接触件10c连接的金属层13的部分界定金属层13的馈线部分。在其它实施例中，如果金属层13充当屏蔽层，那么金属层13电连接到衬底10内的接地元件10g。在一些实施例中，金属层13的侧表面133与衬底10的侧表面103基本上共面。金属层13包含传导材料，例如，金属或金属合金。传导材料的实例包含金(Au)、银(Ag)、铝(Al)、铜(Cu)或其两种或多于两种的合金。
在集成有天线的相当的半导体封装装置中，天线和电子组件并列安置在衬底上，这将增加半导体封装装置的总面积(例如，X-Y尺寸)。根据如图1A中所展示的一些实施例，金属层13形成或安置在封装体12上，且因此可减小半导体封装装置1A的总面积。此外，金属层13直接接触衬底10上的电接触件10c，这将减少信号损耗且改善半导体封装装置1A的性能。
图1B说明根据本公开的一些实施例的半导体封装装置1B的截面视图。半导体封装装置1B类似于图1A中所展示的半导体封装装置1A，例外为半导体封装装置1B的天线13'不安置在封装体12的所有侧表面上。举例来说，至少一个侧表面(例如，侧表面124)从金属层13'露出。
图2A说明根据本公开的一些实施例的半导体封装装置2A的截面视图。半导体封装装置2A类似于图1A中所展示的半导体封装装置1A，例外为半导体封装装置2A的封装体22具有或界定至少一个凹部22h(或孔口)。凹部22h形成于封装体22的顶表面221上，而不穿过封装体22。也就是说，凹部22h的深度小于封装体22的顶表面221处的封装体22的厚度；举例来说，凹部22h的深度可以是封装体22的厚度的至多约90％、至多约80％、至多约70％、至多约60％或至多约50％的非零值。凹部22h的形状和数目可基于不同设计规格选择或确定。在一些实施例中，凹部22h经成形为圆柱体、立方体或圆锥体。金属层23安置在封装体22的外表面上且在封装体22的凹部22h内延伸，以便填充凹部22h。
图2B说明根据本公开的一些实施例的半导体封装装置2B的截面视图。半导体封装装置2B类似于图2A中所展示的半导体封装装置2A，例外为半导体封装装置2B的金属层23'具有或界定至少一个凹部23h(或孔口)。凹部23h形成于金属层23'的顶表面231上，而不穿过金属层23'。也就是说，凹部23h的深度小于金属层23'的顶表面231处的金属层23'的厚度；举例来说，凹部23h的深度可以是金属层23'的厚度的至多约90％、至多约80％、至多约70％、至多约60％或至多约50％的非零值。凹部23h的形状和数目可基于不同设计规格选择或确定。在一些实施例中，凹部23h经成形为圆柱体、立方体或圆锥体。
图2C说明根据本公开的一些实施例的半导体封装装置2C的截面视图。半导体封装装置2C类似于图2B中所展示的半导体封装装置2B，例外为半导体封装装置2C的封装体22'基本上完全覆盖或囊封电子组件11a、11b。举例来说，封装体22'与电子组件11a、11b之间不存在气隙或空腔，且封装体22'接触电子组件11a、11b。
如图2A、图2B和图2C中所展示，通过在封装体22或22'上形成凹部22h且将金属层23或23'延伸到凹部22h中，可以相对较便宜且效率更高的方式实现三维天线。在一些实施例中，如分别展示半导体封装装置2C的从一侧的侧视图、半导体封装装置2C的从另一侧的侧视图和半导体封装装置2C的俯视图的图2D、图2E和图2F中所展示，金属层23'的凹部23h的形状和位置相对于封装体22'的凹部22h的位置可用以实现阻抗匹配。举例来说，凹部23h可与凹部22h侧向间隔开。
图3A、图3B、图3C和图3D说明根据本公开的一些实施例的半导体制造方法。
参看图3A，提供包含多个衬底30的衬底条，且多个衬底30的提供允许同时制造多个半导体封装装置。衬底30可以是例如印刷电路板，例如纸质铜箔层合物、复合铜箔层合物，或聚合物浸渍的玻璃纤维类铜箔层合物。衬底30可包含互连结构，例如RDL或接地元件。在一些实施例中，衬底30与如图1A中所展示的衬底10相同或类似。
至少一个电子组件31形成或安置在每一衬底30上。电子组件31可以是例如IC或裸片的有源电子组件，或例如电容器、电阻器或电感器的无源电子组件。电子组件31可借助于倒装芯片或导线接合技术电连接到衬底30(例如，到RDL)。
参看图3B，封装体32形成于每一衬底31上。封装体32具有或界定空腔32c以容纳电子组件31。举例来说，封装体32界定电子组件31与封装体32之间的气隙。在一些实施例中，封装体32包含：包含填料的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或酚类材料、其中分散有硅酮的材料，或其两种或多于两种的组合。封装体32可通过例如转移模制或压缩成型等模制技术或冲压技术形成。
参看图3C，金属层33安置在或形成于衬底30和封装体32的外表面上。金属层33包含例如金属或金属合金的传导材料。传导材料的实例包含Au、Ag、Al、Cu或其两种或多于两种的合金。在一些实施例中，金属层33可通过溅镀或其它合适的沉积过程形成。在一些实施例中，可通过在封装体32上形成天线方向图(例如，图案化光刻胶层)且根据天线方向图形成金属层33来形成金属层33。
参看图3D，可执行单一化以分离出个别半导体封装装置。也就是说，通过金属层33、封装体32和包含衬底30的衬底条执行单一化。举例来说，可通过使用划片机、激光或其它适当切割技术来执行单一化。在一些实施例中，图3D中所展示的所得半导体封装装置类似于图1A中所展示的半导体封装装置1A。
图4A和图4B说明根据本公开的一些实施例的半导体制造方法。图4A中所展示的操作在图3A中所展示的操作之后。
参看图4A，形成罩44(或盖)。罩44包含封装体42(或塑料盖)和覆盖封装体42的金属层43。在一些实施例中，罩44可通过激光直接构造(LDS)技术形成。
参看图4B，罩44放置在每一衬底30上以覆盖电子组件31。罩44具有或界定空腔以容纳电子组件31。举例来说，罩44界定电子组件31与罩44之间的气隙。接着，可执行单一化以分离出个别半导体封装装置，如图3D中所展示。
图5A和图5B说明根据本公开的一些实施例的半导体制造方法。图5A中所展示的操作在图3A中所展示的操作之后。图5A和图5B中所展示的操作类似于图4A和图4B中所展示的那些操作，例外为在图5A中，至少一个凹部52h形成于封装体52(或塑料盖)中且至少一个凹部53h形成于金属层53中。在一些实施例中，凹部52h和53h可通过激光钻孔、冲孔、蚀刻或其它合适的过程形成。
参看图5B，将在图5A中形成的罩54放置在每一衬底30上以覆盖电子组件31。罩54具有或界定空腔以容纳电子组件31。举例来说，罩44界定电子组件31与罩54之间的气隙。接着，可执行单一化以分离出个别半导体封装装置，如图3D中所展示。在一些实施例中，所得分离的半导体封装装置类似于图2B中所展示的半导体封装装置2B。
图6A、图6B、图6C、图6D和图6E说明根据本公开的一些实施例的半导体制造方法。
参看图6A，提供包含多个衬底30的衬底条，且多个衬底30的提供允许同时制造多个半导体封装装置。衬底30可以是例如印刷电路板，例如纸质铜箔层合物、复合铜箔层合物，或聚合物浸渍的玻璃纤维类铜箔层合物。衬底30可包含互连结构，例如RDL或接地元件。在一些实施例中，衬底30与如图1A中所展示的衬底10相同或类似。
至少一个电子组件31形成或安置在每一衬底30上。电子组件31可以是例如IC或裸片的有源电子组件，或例如电容器、电阻器或电感器的无源电子组件。电子组件31可借助于倒装芯片或导线接合技术电连接到衬底30(例如，到RDL)。
封装体62形成于衬底30条上以覆盖或囊封每一电子组件31。在一些实施例中，封装体62包含：包含填料的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或酚类材料、其中分散有硅酮的材料，或其两种或多于两种的组合。封装体62可通过例如转移模制或压缩模制等模制技术形成。
参看图6B，多个凹部62h形成于封装体62中。在一些实施例中，凹部62h可通过例如激光刻槽、冲孔、蚀刻、铣切或其它合适的过程形成。
参看图6C，可执行单一化以分离出个别半导体封装装置。也就是说，通过封装体62和包含衬底30的衬底条执行单一化。举例来说，可通过使用划片机、激光或其它适当切割技术来执行单一化。
参看图6D，金属层63安置在或形成于衬底30的侧表面和封装体62的外表面(包含顶表面和侧表面)上。金属层63延伸到封装体62的凹部62h中。金属层63包含例如金属或金属合金的传导材料。传导材料的实例包含Au、Ag、Al、Cu或其两种或多于两种的合金。在一些实施例中，金属层63可通过溅镀或其它合适的沉积过程形成。
参看图6E，至少一个凹部63h形成于金属层63中，以形成半导体封装装置6。在一些实施例中，半导体封装装置6类似于图2C中所展示的半导体封装装置2C，例外为金属层63覆盖衬底30的侧表面，且金属层63的底端与衬底30的底表面基本上共面。在一些实施例中，凹部63h可通过例如激光刻槽、冲孔、蚀刻、铣切或其它合适的过程形成。
如本文中所使用，术语“基本上”、“基本”、“近似地”和“约”用以指代和说明小的变化。举例来说，当结合数值使用时，术语可指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。作为另一实例，膜或层的厚度“基本上均匀”可指膜或层的平均厚度的小于或等于±10％的标准偏差，例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。术语“基本上共面”可指两个表面在数微米内处于沿同一平面，例如在40μm内、30μm内、20μm内、10μm内或1μm内处于沿同一平面。如果两个表面或组件之间的角为例如90°±10°，例如，±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°，那么两个表面或组件可被认为“基本上垂直”。如果两个表面或组件之间的角为例如0°±10°，例如，±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°，那么两个表面或组件可被认为“基本上平行”。当结合事件或情况使用时，术语“基本上”、“基本”、“近似地”和“约”可指其中事件或情况精确出现的例子，以及其中事件或情况非常近似出现的例子。
在一些实施例的描述中，提供于另一组件“上”的组件可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个中间组件位于前一组件与后一组件之间的情况。
另外，有时在本文中以范围格式呈现量、比率和其它数值。应理解，此类范围格式是出于便利和简洁目的而使用，且应灵活地理解，不仅包含明确地指定为范围极限的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围一般。
尽管已参考本公开的特定实施例描述和说明本公开，但这些描述和说明并不限制本公开。所属领域的技术人员可明确地理解，在不脱离如由所附权利要求书界定的本公开的真实精神和范围的情况下，可进行各种改变，且可在实施例内替换等效元件。图式可能未必按比例绘制。归因于制造过程中的变化和此些原因，本公开中的艺术再现与实际设备之间可存在区别。可存在并未具体说明的本公开的其它实施例。应将本说明书和图式视为说明性的而非限定性的。可进行修改，以使特定情形、材料、物质组成、方法或过程适应于本公开的目标、精神和范围。所有此类修改既定在此所附权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述本文中所公开的方法，但应理解，可在不脱离本公开的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本公开的限制。

Claims (10)

1.一种半导体封装装置，其包括
衬底，其具有顶表面和与所述顶表面相对的底表面； 裸片，其安置在所述衬底的所述顶表面上；
封装体，其安置在所述衬底的所述顶表面上且环绕所述裸片；以及
天线层，其安置在所述封装体的顶表面上，其中所述天线层界定第一凹部，
其中直接在所述第一凹部下方的所述封装体的顶表面不具有凹部，以及
其中所述封装体界定在所述封装体的所述顶表面上的第二凹部，所述第二凹部与所述第一凹部侧向间隔开以实现阻抗匹配，且其中所述封装体的所述第二凹部填充有所述天线层。
2.根据权利要求 1 所述的半导体封装装置，其中所述衬底包含所述衬底的所述顶表面上的传导垫，且所述天线层接触所述衬底的所述顶表面上的所述传导垫。
3.根据权利要求 1 所述的半导体封装装置，其中经所述天线层界定的所述第一凹部的深度小于所述天线层的厚度。
4.根据权利要求 1 所述的半导体封装装置，其中所述封装体和所述衬底界定空间以容纳所述裸片。
5.根据权利要求 1 所述的半导体封装装置，其中所述封装体接触所述裸片。
6.根据权利要求 1 所述的半导体封装装置，其中所述第一凹部通过激光钻孔、冲孔、或蚀刻形成。
7.根据权利要求 1 所述的半导体封装装置，其中经所述封装体界定的所述第二凹部的深度小于所述封装体的厚度。
8.根据权利要求 1 所述的半导体封装装置，其中所述衬底具有在所述衬底的所述顶表面与所述底表面之间延伸的侧表面；
所述封装体具有基本上垂直于所述封装体的所述顶表面的侧表面；且所述衬底的所述侧表面不与所述封装体的所述侧表面对准。
9.根据权利要求 8 所述的半导体封装装置，其中所述天线层具有安置在所述封装体的所述顶表面上的顶表面，和安置在所述封装体的所述侧表面上的侧表面；且
所述天线层的所述侧表面与所述衬底的所述侧表面基本上共面。
10.根据权利要求 2 所述的半导体封装装置，其中所述天线层包括与所述衬底连接的馈线部分，与所述衬底上的所述传导垫连接的所述天线层的部分界定所述馈线部分，且所述馈线部分露出所述封装体的侧表面。
CN201810132635.5A 2017-08-18 2018-02-09 半导体封装装置和其制造方法 Active CN109411450B (zh)

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