CN109411432B - Semiconductor packaging rewiring layer structure - Google Patents

Semiconductor packaging rewiring layer structure Download PDF

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Publication number
CN109411432B
CN109411432B CN201711399770.8A CN201711399770A CN109411432B CN 109411432 B CN109411432 B CN 109411432B CN 201711399770 A CN201711399770 A CN 201711399770A CN 109411432 B CN109411432 B CN 109411432B
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width
conductive line
cross
dielectric layer
upper conductive
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CN109411432A (en
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林玠模
郭书玮
郑惟元
杨镇在
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Industrial Technology Research Institute ITRI
Intellectual Property Innovation Corp
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Industrial Technology Research Institute ITRI
Intellectual Property Innovation Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention discloses a semiconductor packaging rewiring layer structure. Includes a dielectric layer, an upper conductive line, a lower conductive line and a plurality of through holes. The dielectric layer has a thickness, the upper conductive line is located above the dielectric layer, and the lower conductive line is located below the dielectric layer. The plurality of through holes penetrate through the dielectric layer and are connected with the upper conducting wire and the lower conducting wire, each through hole is provided with a cross section on the first conducting wire and has a third width, wherein the ratio of the third width of the cross sections to the thickness of the dielectric layer is smaller than or equal to 1, and the ratio of the interval between the cross sections of the through holes to the third width of the through holes is at least more than 0.5.

Description

Semiconductor packaging rewiring layer structure
Technical Field
The present invention relates to semiconductor packaging technology, and more particularly, to a Redistribution Layer (RDL) structure of a semiconductor package.
Background
As semiconductor package manufacturing technology advances, microelectronic components become smaller and the circuitry within these components becomes more and more dense. In order to make the size of the microelectronic assembly smaller, the packaging and assembly of the various elements in the microelectronic assembly must become more compact in circuit design, and in order to meet the requirements of smaller space and higher density, all components on the electronic assembly must be optimally designed.
In a redistribution layer (RDL) of a semiconductor package, vias are usually used in conjunction with the RDL to electrically connect layers. The cross-sectional shape of the through-hole is usually circular and has an area larger than the width of the conductive line, so as to obtain better electrical transmission.
Disclosure of Invention
Embodiments of the present invention provide a redistribution layer structure for semiconductor package, which has a plurality of smaller via areas, a better spacing ratio between the vias, and a better aspect ratio at the vias.
An embodiment of the invention provides a redistribution layer structure of a semiconductor package, which includes a dielectric layer, an upper conductive line, a lower conductive line and a plurality of through holes. The dielectric layer has a thickness and comprises a first surface and a second surface opposite to the first surface; the upper conducting wire is positioned on the first surface of the dielectric layer and has a first width; the lower conducting wire is positioned on the second surface of the dielectric layer and has a second width, wherein the upper conducting wire and the lower conducting wire are isolated by the dielectric layer; the plurality of through holes penetrate through the dielectric layer and are connected with the upper conducting wire and the lower conducting wire, each through hole is provided with a cross section and a third width, wherein the ratio of the third width to the thickness of the dielectric layer is smaller than or equal to 1, and the ratio of the interval between the cross sections of the through holes to the third width is at least more than 0.5.
An embodiment of the invention provides a redistribution layer structure of a semiconductor package, which includes a dielectric layer, an upper conductive line, a lower conductive line and a plurality of through holes. The dielectric layer has a thickness and comprises a first surface and a second surface opposite to the first surface; the upper conducting wire is positioned on the first surface of the dielectric layer and has a first width; the lower conducting wire is positioned on the second surface of the dielectric layer and has a second width, wherein the upper conducting wire and the lower conducting wire are isolated by the dielectric layer; a plurality of through holes penetrating the dielectric layer and connected to the upper conductive line and the lower conductive line, each through hole having a cross section on the upper conductive line, having a fourth width and a fifth width, wherein the fourth width and the fifth width are perpendicular to each other, wherein a ratio of the fourth width or the fifth width to a thickness of the dielectric layer is less than or equal to 1, a ratio of a distance between cross sections of each through hole to the fourth width or the fifth width of the cross sections is at least 0.5 or more, and wherein a ratio of the fourth width to the fifth width of the cross sections or a ratio of the fifth width to the fourth width of the cross sections is at least 1.2 or more.
An embodiment of the invention provides a redistribution layer structure of a semiconductor package, which includes a dielectric layer, an upper conductive line, a lower conductive line and a single via. The dielectric layer has a thickness and comprises a first surface and a second surface opposite to the first surface; the upper conducting wire is positioned on the first surface of the dielectric layer and has a first width; the lower conductive line is located on the second surface of the dielectric layer and has a second width, wherein the upper conductive line and the lower conductive line are isolated by the dielectric layer, the single through hole penetrates through the dielectric layer and is connected with the upper conductive line and the lower conductive line, the single through hole has a cross section on the upper conductive line and has a third width, and the ratio of the third width of the cross section to the thickness of the dielectric layer is smaller than or equal to 1.
In view of the above, in the redistribution layer of the semiconductor package according to the embodiment of the present invention, on one hand, there are a plurality of through holes, and on the other hand, the width of the through holes does not exceed the width of the conductive lines. Therefore, the redistribution layer structure of the semiconductor package of the embodiment of the invention can improve the utilization rate of wire routing and improve the conductive capability of the upper and lower wires. Therefore, the redistribution layer in the embodiment of the invention can improve the measurement accuracy.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic top view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention;
fig. 2 is a schematic perspective view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention;
fig. 3 is a schematic perspective view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention;
FIG. 4 is a cross-sectional view of a redistribution layer structure of a semiconductor package according to an embodiment of the present invention;
FIG. 5 is a schematic top view of a redistribution layer structure of a semiconductor package according to an embodiment of the present invention;
fig. 6 is a schematic perspective view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention;
fig. 7a, 7b and 7c are schematic top views of a via of a redistribution layer of a semiconductor package according to an embodiment of the invention;
fig. 8 is a schematic perspective view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention.
Description of the symbols
110. 210, 310, 410: dielectric layer
120. 220, 320, 520: upper lead
140. 240, 340, 440, 540: through hole
211: first surface
212: second surface
230. 330: lower conducting wire
50: integrated circuit with a plurality of transistors
D1: first width
D2: second width
D3: third width
D4: fourth width
D5: fifth width
P1: distance between each other
R1: a first direction
R2: second direction
T: thickness of dielectric layer
Detailed Description
Fig. 1 is a schematic top view of a redistribution layer of a semiconductor package according to an embodiment of the present invention, and a redistribution layer structure of the semiconductor package in each embodiment is briefly described as a redistribution layer, referring to fig. 1, the present embodiment is a circuit diagram of a portion of the redistribution layer, and includes a dielectric layer 110, an upper conductive line 120, wherein the upper conductive line 120 has a width D1, and a plurality of vias 140, and an end of each upper conductive line 120 has a via 140, but the number of the vias 140 on each upper conductive line 120 is different, but at least one via 140 is included so that the upper conductive line 120 can be electrically connected to a lower conductive line (not shown) through the vias 140 penetrating through the dielectric layer 110.
Fig. 2 is a schematic perspective view of a redistribution layer structure of a redistribution layer of a semiconductor package according to an embodiment of the invention. For clarity, fig. 2 schematically shows only some of the redistribution layers, i.e., only two layers of conductive lines in the redistribution layers and the dielectric layer and the through holes therebetween. Referring to fig. 2, the redistribution layer of the present embodiment includes a dielectric layer 210 having a thickness T, the dielectric layer having a first surface 211 and a second surface 212 opposite to the first surface, and an upper conductive line 220 located on the first surface 211 of the dielectric layer 210 and having a first width D1; and a lower conductive line 230 on the second surface 212 of the dielectric layer 210 and having a second width D2, wherein the upper conductive line 220 and the lower conductive line 230 are isolated by the dielectric layer 210; and a plurality of vias 240 penetrating the dielectric layer 210 and connecting the upper conductive lines 220 and the lower conductive lines 230, the vias 240 and the upper conductive lines 210 and the lower conductive lines 230 each having a cross-section, wherein the cross-section of the upper conductive lines 220 has a third width D3, and in the present embodiment, the cross-section formed by the vias 240 and the upper conductive lines 220 is circular.
In the embodiment shown in fig. 2 and later, the upper conductive lines 220 and the lower conductive lines 230 are not shown to have a thickness, but may be conductive lines having a thickness. The cross-section formed by the upper conductive line 220 and the through hole 240 may also have a geometric shape such as an ellipse, a polygon, etc. The cross-section formed by the lower conductive line 230 and the through hole 240 may also have a geometric shape such as an ellipse, a polygon, etc. The present invention is not limited to the shape of the cross section.
In order to reduce the damage to the through holes caused by the stress generated during the removal of the redistribution layer after the semiconductor package is manufactured, in the present embodiment, the cross-sectional shape formed by the through holes 240 and the upper conductive lines 220 is circular, and has a third width D3, where the third width D3 refers to the diameter of the circle, and the ratio of the third width D3578 to the thickness T of the dielectric layer 210 in the redistribution layer is less than or equal to 1, and in the present embodiment, the ratio of the pitch P1 between the cross-sections of two adjacent through holes 240 in the upper conductive lines 220 to the third width D3 of the through holes 240 in the same upper conductive line 220 is at least 0.5.
In the redistribution layer of the present embodiment, the vias 240 may be filled with a conductive material to electrically connect the upper conductive lines 220 and the lower conductive lines 230. The conductive material filled in the plurality of through holes 240 is, for example, a metal, and the metal includes, but is not limited to, titanium, copper, nickel, gold, or any combination thereof, or other suitable materials. The upper conductive lines 220 and the lower conductive lines 230 are made of conductive material, such as metal, including but not limited to titanium, copper, nickel, gold, or other suitable materials. The dielectric layer 210 is, for example, an organic material, and the organic material may be Polyimide (PI), Polybenzoxazole (PBO), benzocyclobutene polymer (BCB), or any combination thereof, or other suitable materials, but is not limited thereto.
As shown in FIG. 2, in the redistribution layer of the present embodiment, the vias 240 of each of the upper conductors 220 have a third width D3, and the vias 240 have a circular cross-sectional shape, so that each via 240 has an area of π × (third width D3/2)2i.e., 0.25 π x (third width D3)2Where pi is the circumferential ratio in mathematics, and pi in the following embodiments all represent the circumferential ratio in mathematics.
in the redistribution layer in this example, the third width D3 of the vias 240 in all of the upper conductors 220 is not greater than the first width D1 of the upper conductors 220, in other words, the maximum third width D3 of all of the vias 240 will be equal to the first width D1 of the upper conductors 220 in the redistribution layer, so the cross-sectional area of all of the vias 240 will be less than or equal to 0.25 π × (first width D1)2。
in the redistribution layer of the present embodiment, each upper conductive line 220 has a plurality of vias 240 therein, and each upper conductive line 220 includes a plurality of vias 240 having a total cross-sectional area of 0.25-2.0 π × (first width D1)2So that the same upper conductive line 220 can provide a sufficient effective area to be electrically connected with the lower conductive line 230.
Fig. 3 is a schematic perspective view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention. Fig. 3 schematically shows only some of the components of the redistribution layer, i.e., only two layers of conductive lines in the redistribution layer and the dielectric layer and the via between them. As shown in fig. 3, in the redistribution layer in this example, each via 340 penetrating through the dielectric layer 310 is perpendicular to the direction of the upper conductive line 320, and the cross section formed by each via 340 and the upper conductive line 320 is circular. The cross-sections of vias 340, whether on the same upper line 320 or on other lines throughout a redistribution layer, may be equal or unequal in area. In the present embodiment, the cross-sectional areas of the lower conductive lines 330 and the through holes 340 may be equal or different, and the cross-sectional areas of the upper conductive lines 320 and the lower conductive lines 330 connected by the same through hole 340 may be equal or different. In addition, the number of cross sections formed by each different upper conductive line 320 (or lower conductive line 330) and via 340 may be the same or different.
In the redistribution layer in this embodiment, the cross sections of the upper conductive lines 320 and the corresponding through holes 340 may have different area sizes, the through holes 340 may be arranged regularly or in a random order according to the area sizes of the cross sections of the through holes 340, and the cross sections of the through holes 340 and the lower conductive lines 330 may also have different area sizes, and the cross sections may also be arranged regularly or in a random order according to the area sizes of the cross sections.
In the redistribution layer in this embodiment, the materials of the via 340, the upper conductive line 320 and the lower conductive line 330 are described with reference to the embodiment of fig. 2, and will not be repeated here.
Fig. 4 is a cross-sectional view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention. Fig. 4 schematically shows only some of the components of the redistribution layer, i.e., only two layers of conductive lines in the redistribution layer and the dielectric layer and the via between them. As shown in fig. 4, in the present embodiment, in order to reduce the damage to the vias caused by the stress generated during the removal process in the redistribution layer after the semiconductor package is manufactured, in the redistribution layer, the cross-sectional widths of the vias 440 and the thickness of the dielectric layer 410 between two layers of wires have a specific ratio, the vias 440 have a third width D3 in the cross-section of the upper conductive line (not shown), the dielectric layer 410 between the upper conductive line and the lower conductive line has a thickness T, and the ratio of the third width D3 to the thickness T is less than or equal to 1, thereby improving the reliability of the electrical connection. In addition, the ratio of the pitch P1 between the through holes in the same upper lead to the third width D3 of the through holes in the same upper lead is at least 0.5 or more.
In the redistribution layer in this embodiment, the materials of the via 440, the upper conductive line and the lower conductive line are described with reference to the via 240, the upper conductive line 220 and the lower conductive line 230 in the embodiment of fig. 2, and will not be repeated here.
in another embodiment, if the top trace is designed for functional purposes, a single via (not shown) may be provided, the single via having a cross-section at the top trace that is circular in cross-sectional shape and has a third width D3, similar to the embodiment of FIG. 2, and the maximum value of the third width D3 will be equal to the first width D1 of the top trace, so that the area of the cross-section of the single via will be equal to 0.25 π × (first width D1)2Since the embodiment has only a single via, the relationship between the spacing between the vias and the width of the upper conductive line as defined in the previous embodiments is not present.
Fig. 5 is a schematic top view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention. When the semiconductor element is manufactured, a redistribution layer is formed on the carrier plate, then the chip is arranged on the redistribution layer, and the carrier plate is removed and the ball is planted after the chip is packaged by the packaging colloid. Referring to fig. 5, in the fabrication of the semiconductor package, a plurality of semiconductor units including Integrated Circuits (ICs) 50 and a plurality of conductive wires 520 (including through holes) are formed around the periphery of each IC 50, and when the final package is completed, the carrier is mechanically removed (i.e., removed) along a first direction R1 or a second direction R2, wherein the first direction R1 and the second direction R2 are substantially perpendicular to each other.
Fig. 6 is a schematic perspective view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention. Fig. 6 schematically shows only some of the components of the redistribution layer, i.e., only two layers of conductive lines in the redistribution layer and the dielectric layer and the via between them. As shown in fig. 6, in the present embodiment, the cross-sections of the through holes 240 in the upper conductive lines 220 in the redistribution layer are non-circular, and the circular cross-sections are already disclosed in the embodiment of fig. 2 and are not repeated herein. A non-circular portion, which may comprise an ellipse, a polygon, or a combination thereof. In the embodiment, the redistribution layer includes a dielectric layer 210 having a thickness T, the dielectric layer 210 includes a first surface 211 and a second surface 212 opposite to the first surface; an upper conductive line 220 on the first surface 211 of the dielectric layer and having a first width D1; a lower conductive line 230 having a second width D2 on the second surface 212 of the dielectric layer, wherein the upper conductive line 220 and the lower conductive line 230 are isolated by the dielectric layer 210; and a plurality of vias 240 penetrating the dielectric layer and connecting the upper conductive line and the lower conductive line, the vias 240 each having a cross section at the upper conductive line 220 and the lower conductive line 230, wherein the cross section at the upper conductive line 220 has a fourth width D4 and a fifth width D5, wherein the fourth width D4 and the fifth width D5 are perpendicular to each other, wherein a ratio of the fourth width D4 or the fifth width D5 of the cross section at the plurality of vias 240 to the thickness T of the dielectric layer 210 is less than or equal to 1, a ratio of a pitch P1 between the cross sections at the plurality of vias 240 to the fourth width D4 or the fifth width D5 of the cross section at the plurality of vias is at least 0.5 or more, and a ratio of the fourth width D4 of the cross section at the via in the first direction R1 parallel to the take-down direction to the fifth width D5 of the cross section at the via parallel to the second direction R2 is at least 1.2 or more.
In the redistribution layer in this embodiment, the materials of the via 240, the upper conductive line 220 and the lower conductive line 230 are described with reference to the embodiment of fig. 2, and will not be repeated here.
Fig. 7a, 7b and 7c are schematic top views of through holes of a redistribution layer of a semiconductor package according to an embodiment of the invention. Referring to fig. 6 and 7a, the cross-sectional shape of the through hole 240 of the upper conductive line 220 is an ellipse, and has a fourth width D4 and a fifth width D5, wherein the fourth width D4 is perpendicular to the fifth width D5, the fourth width D4 of the first direction R1 parallel to the removing direction is longer, and the shorter fifth width D5 does not exceed the first width D1 of the upper conductive line 220, meanwhile, the ratio of the fourth width D4 or the fifth width D5 to the thickness T of the dielectric layer 210 is less than or equal to 1, and the ratio of the fourth width D4 parallel to the first direction R1 to the fifth width D5 parallel to the second direction R2 is at least 1.2.
Referring to fig. 6 and 7b, the cross-sectional shape of the via 240 on the upper conductive line 220 is hexagonal, and has a fourth width D4 and a fifth width D5, wherein the fourth width D4 is perpendicular to the fifth width D5, the fourth width D4 of the first direction R1 parallel to the removing direction is longer, and the shorter fifth width D5 does not exceed the first width D1 of the upper conductive line 220, meanwhile, the ratio of the fourth width D4 or the fifth width D5 to the thickness T of the dielectric layer 210 is less than or equal to 1, and the ratio of the fourth width D4 parallel to the first direction R1 to the fifth width D5 parallel to the second direction R2 is at least 1.2.
Referring to fig. 6 and 7c, the cross-sectional shape of the via 240 on the upper conductive line 220 is octagonal, and has a fourth width D4 and a fifth width D5, wherein the fourth width D4 is perpendicular to the fifth width D5, the fourth width D4 of the first direction R1 in the parallel-to-take-down direction is longer, and the shorter fifth width D5 does not exceed the width D1 of the upper conductive line 220, the thickness ratio of the fourth width D4 or the fifth width D5 to the dielectric layer 210 is less than or equal to 1, and the ratio of the fourth width D4 parallel to the first direction R1 to the fifth width D5 parallel to the second direction R2 is at least 1.2.
In the above embodiments, the removing direction is parallel to the fourth width D4 of the cross section of the through hole, so the fourth width D4 of the cross section of the through hole is greater than the fifth width D5, and in another embodiment, when the removing direction is parallel to the fifth width D5 of the cross section of the through hole, the fifth width D5 of the cross section of the through hole is greater than the fourth width D4 (not shown), but the invention is not limited thereto.
referring to the embodiment of fig. 6 and fig. 7a, 7b, and 7c, no matter the oval or polygonal through hole 240, since the ratio of the fourth width D4 to the fifth width D5 of the cross section of the through hole 240 is more than 1.2, and thus the through hole has an equivalent area like a circle, similarly to the embodiment shown in fig. 2, in short, the shorter fifth width D5 of the cross section of the through hole is not greater than the first width D1 of the upper conductive line 220, so the maximum value of the fifth width D5 is equal to the first width D1 of the upper conductive line 220 in the redistribution layer, and the maximum value of the area of the cross section of the oval or polygonal through hole 240 is less than or equal to 0.25 pi × (the first width D1)2. In another embodiment, when the first direction of the removal is parallel to the fifth width D5, wherein the shorter of the fourth widths D4 is not greater than the first width D1 of the upper conductive line 220, the maximum value of the fourth width D4 will be equal to the first width D1 of the upper conductive line 220 in the redistribution layerthe width D1, the maximum area of the cross-section of the oval or polygonal through-holes 240 will still be less than or equal to 0.25 π × (first width D1)2。
in the redistribution layer of the present embodiment, each upper conductive line 220 may have a plurality of vias 240 therein, and the sum of the cross-sectional equivalent areas of the vias 240 included in the upper conductive line 220 is 0.25-2.0 π × (first width D1)2So that the same upper conductive line 220 can provide a sufficient effective electrical conduction area to be electrically connected with the lower conductive line 230.
in another embodiment, if the top trace is designed for functional purposes, a single via (not shown) may be provided, the cross-section of the single via is oval or polygonal, has a fourth width D4 and a fifth width D5, similar to that shown in the embodiment of FIG. 6, wherein the difference is the difference between the single via and the plurality of vias, and thus all have circular equivalent areas, and the cross-sectional shape of the single via has an area less than or equal to 0.25 π × (first width D1)2Since the embodiment has only a single via, the relationship between the spacing between the vias and the width of the upper conductive line as defined in the previous embodiments is not present.
Fig. 8 is a schematic perspective view of a redistribution layer structure of a semiconductor package according to an embodiment of the invention. Fig. 8 schematically shows only a part of the redistribution layer, that is, only two layers of wires in the redistribution layer and the dielectric layer and the via between them. Referring to fig. 8, the redistribution layer is substantially the same as the redistribution layer of fig. 3, and each of the through holes 340 penetrating through the dielectric layer 310 is perpendicular to the direction of the upper conductive lines 320, which is mainly different in that the redistribution layer, the through holes 340 and the upper conductive lines 320 in this embodiment form an oval, polygonal or combination thereof cross section. The area of vias 340, whether on the same upper line 320 or on other lines throughout the redistribution layer, may be equal or unequal. In one embodiment, the cross-sectional areas of the lower conductive lines 330 and the through holes 340 may be equal or different, and the cross-sectional areas of the upper conductive lines 320 and the lower conductive lines 330 connected by the same through hole 340 may be equal or different. In addition, the number of cross sections formed by each different upper conductive line 320 (or lower conductive line 330) and via 340 may be the same or different.
In the redistribution layer in this embodiment, the cross sections of the upper conductive lines 320 and the corresponding through holes 340 may have different area sizes, the through holes 340 may be arranged regularly or in a random order according to the area sizes of the cross-sectional shapes of the through holes 340, and the cross sections of the through holes 340 intersecting the lower conductive lines 330 may also have different area sizes, and the cross sections may also be arranged regularly or in a random order according to the area sizes of the cross sections.
In the redistribution layer in this embodiment, the materials of the via 340, the upper conductive line 320 and the lower conductive line 330 are described with reference to the via 240, the upper conductive line 220 and the lower conductive line 230 in the embodiment of fig. 2, and will not be repeated here.
In summary, the redistribution layer of the semiconductor package according to the embodiment of the invention has a plurality of through holes on one hand, and on the other hand, the cross-sectional widths of the through holes do not exceed the width of the conductive line. Therefore, the redistribution layer of the semiconductor package of the embodiment of the invention can improve the utilization rate of the wire routing and improve the conductive capability of the upper wire and the lower wire.
In the redistribution layer of the semiconductor package according to the embodiment of the present invention, each of the wires has a cross-sectional shape of a via having a width of a certain ratio. Therefore, the redistribution layer of the semiconductor package in the embodiment of the invention has better stress resistance performance, so that the reliability of the semiconductor package can be improved when the semiconductor package is taken down.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims (17)

1. A redistribution layer structure for a semiconductor package, comprising:
a dielectric layer having a thickness and including a first surface and a second surface opposite to the first surface;
an upper conductive line having a first width on the first surface of the dielectric layer;
a lower conductive line having a second width and located on the second surface of the dielectric layer, wherein the upper conductive line and the lower conductive line are isolated by the dielectric layer;
a plurality of through holes penetrating the dielectric layer and connected to the upper conductive line and the lower conductive line, each of the through holes having a cross section at the upper conductive line and a third width, wherein a ratio of the third width to the thickness of the dielectric layer is less than or equal to 1, and a ratio of a pitch between the cross sections of each of the through holes to the third width is at least 0.5 or more;
wherein the third width of the cross-sections of the vias is not greater than the first width of the upper conductive line; and
wherein each of the through holes does not deviate from each other at the center of the section of the upper conductive line and at the center of the other section of the lower conductive line.
2. the redistribution layer structure of claim 1, wherein the cross-sectional areas of the vias are less than or equal to 0.25 pi × (the first width)2Where pi is the circumferential ratio in mathematics.
3. The redistribution layer structure of claim 1, wherein the cross-sections of the vias are circular.
4. The redistribution layer structure of claim 1, wherein the cross-sections of the vias have equal or unequal areas.
5. The redistribution layer structure of claim 1, wherein the cross-sections of the through-holes are arranged in a regular or random order according to the area of the cross-sections of the through-holes.
6. The redistribution layer structure of claim 1, wherein the vias are filled with a conductive material comprising titanium, copper, nickel, gold, or any combination thereof.
7. the redistribution layer structure of claim 1, wherein the total cross-sectional area of the vias of the upper conductive line is between 0.25 pi × (the first width)22.0 π × (this first width)2Where pi is the circumferential ratio in mathematics.
8. The redistribution layer structure of claim 1, wherein the cross-section of the upper conductive line and the cross-section of the lower conductive line connected by each of the vias may be equal or different.
9. A redistribution layer structure for a semiconductor package, comprising:
a dielectric layer having a thickness and including a first surface and a second surface opposite to the first surface;
an upper conductive line having a first width on the first surface of the dielectric layer;
a lower conductive line having a second width and located on the second surface of the dielectric layer, wherein the upper conductive line and the lower conductive line are isolated by the dielectric layer;
a plurality of vias penetrating the dielectric layer and connecting the upper conductive line and the lower conductive line, each of the vias having a cross section at the upper conductive line, the vias having a fourth width and a fifth width, wherein the fourth width is perpendicular to the fifth width, wherein a ratio of the fourth width or the fifth width to the thickness of the dielectric layer is less than or equal to 1, a ratio of a pitch between cross sections of each of the vias to the fourth width or the fifth width of the cross sections is at least 0.5 or more, and wherein a ratio of the fourth width to the fifth width of the cross sections or a ratio of the fifth width to the fourth width of the cross sections is at least 1.2 or more; and
wherein a maximum value of the fourth widths or the fifth widths of the cross-sectional shapes of the through-holes is the first width of the upper conductive line.
10. the redistribution layer structure of claim 9, wherein the cross-sectional areas of the vias are less than or equal to 0.25 pi × (the first width)2Where pi is the circumferential ratio in mathematics.
11. The redistribution layer structure of claim 9, wherein the cross-sectional shapes of the vias are oval, polygonal, or a combination thereof.
12. The redistribution layer structure of claim 9, wherein the cross-sectional shapes of the vias have equal or unequal areas.
13. The redistribution layer structure of claim 9, wherein the arrangement of the cross-sectional shapes of the through-holes is regular or random according to the area size of the cross-sections of the through-holes.
14. The redistribution layer structure of claim 9, wherein the vias are filled with a conductive material comprising titanium, copper, nickel, gold, or any combination thereof.
15. A redistribution layer structure for a semiconductor package, comprising:
a dielectric layer having a thickness and including a first surface and a second surface opposite to the first surface;
an upper conductive line having a first width on the first surface of the dielectric layer;
a lower conductive line having a second width and located on the second surface of the dielectric layer, wherein the upper conductive line and the lower conductive line are isolated by the dielectric layer;
a single via penetrating the dielectric layer and connecting the upper conductive line and the lower conductive line, the single via having a cross-sectional shape at the upper conductive line and having a third width, wherein a ratio of the third width of the cross-sectional shape to the thickness of the dielectric layer is less than or equal to 1;
wherein the third width of the cross-sectional shape of the single via is not greater than the first width of the upper conductive line; and
wherein the single via hole is not offset from each other at a center of the cross-sectional shape of the upper conductive line and at a center of the other cross-sectional shape of the lower conductive line.
16. the redistribution layer structure of claim 15, wherein the area of the cross-section of the single via is less than or equal to 0.25 π x (the first width)2Where pi is the circumferential ratio in mathematics.
17. The redistribution layer structure of claim 15, wherein the cross-sectional shape of the single via is circular, elliptical, or polygonal.
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