CN109410999B

CN109410999B - Nonvolatile memory device and method of operating the same

Info

Publication number: CN109410999B
Application number: CN201810325034.6A
Authority: CN
Inventors: 全秀昶; 高贵汉; 郭东勋; 金真怜
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2017-08-17
Filing date: 2018-04-12
Publication date: 2023-12-01
Anticipated expiration: 2038-04-12
Also published as: KR102631353B1; US20190057742A1; CN109410999A; US10692578B2; KR20190019364A

Abstract

A method performed by a non-volatile memory device is provided, which may include: initiating a first programming operation corresponding to a first programming cycle among a plurality of programming cycles; receiving a pause command of an emergency read operation during a first program operation; determining a restoration time from one of a first time instant at the same time as receiving the pause command and a second time instant after the completion of the first programming operation based on the pause command; and initiating a restore at the determined restore time by applying a restore voltage to the selected word line.

Description

Nonvolatile memory device and method of operating the same

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2017-0104140 filed in the korean intellectual property office on day 8 and 17 of 2017, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Some example embodiments provide a nonvolatile memory device that efficiently performs a received urgent read request during a program operation and a method of operating the nonvolatile memory device.

Background

Some example embodiments relate to memory devices and methods of operating the same, and more particularly, to nonvolatile memory devices and methods of operating the same that make an emergency read request during a program operation.

A semiconductor memory device is a memory device realized by using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor memory devices are generally classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices.

The nonvolatile memory device is a memory device in which stored data does not disappear even when power supply is cut off. Nonvolatile memory devices can include Read Only Memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), flash memory devices, phase change Random Access Memory (RAM) (PRAM), magnetoresistive RAM (MRAM), and Ferroelectric RAM (FRAM). Flash memory devices may be broadly classified into NOR type and NAND type.

Disclosure of Invention

According to some example embodiments, methods performed by a non-volatile memory device are provided. The method includes initiating a first programming operation corresponding to a first programming cycle among a plurality of programming cycles. The method also includes receiving a pause command for an emergency read during the first programming operation. The method further includes determining, based on the pause command, a resume time from one of a first time at the same time as receiving the pause command and a second time after completion of the first programming operation. Further, the method includes initiating a restore at the determined restore time by applying a restore voltage to the selected word line.

According to some example embodiments, methods performed by a non-volatile memory device are provided. The method includes increasing a voltage level of a selected word line corresponding to a program command by sequentially applying a plurality of stepwise increasing supply voltages to the selected word line. The method also includes receiving a pause command for the emergency read operation during the incrementing. The method also includes determining a resume mode in response to a resume time based on the pause command. In addition, the method includes restoring according to the determined restoration mode; and performing an emergency read operation in response to the read command, wherein the restore mode is one of a cancel mode in which restoration is performed simultaneously with receiving the pause command and a loop mode in which restoration is performed after increasing the voltage level of the selected word line to the target voltage.

According to some example embodiments, a non-volatile memory device is provided that includes at least one processor executing computer readable instructions stored in a non-transitory computer readable storage, the processor configured to apply a program voltage to a selected word line in response to a program command to increase a voltage level of the selected word line to perform a program operation, apply a restore voltage to the selected word line according to a restore mode in response to receiving a pause command for an emergency read operation during the program operation, and determine a restore mode based on the received pause command, wherein the restore mode is one of a cancel mode in which the restore voltage is applied before a first program cycle corresponding to the program command is completed and a loop mode in which the restore voltage is applied after the first program cycle is completed.

Drawings

Some example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating a non-volatile memory system according to some example embodiments;

FIG. 2 is a block diagram illustrating a non-volatile memory device according to some example embodiments;

FIG. 3 is a flowchart illustrating operation of a nonvolatile memory device determining a restore mode and performing a restore operation in accordance with some demonstrative embodiments;

FIG. 4A is a flowchart illustrating operation of a nonvolatile memory device performing a restore operation in a cancel mode in accordance with some example embodiments;

FIG. 4B is a flowchart illustrating operation of a nonvolatile memory device performing a restore operation in a round robin mode according to some exemplary embodiments;

FIG. 5 is a circuit diagram illustrating a single level memory block included in a memory cell array according to some example embodiments;

FIG. 6 is a circuit diagram illustrating a multi-level memory block included in a memory cell array according to some example embodiments;

FIG. 7 is a perspective view of the memory block of FIG. 6;

FIG. 8 is a graph illustrating voltage levels of selected word lines during a series of programming operations of a non-volatile memory device according to some example embodiments;

FIG. 9 is a graph illustrating voltage levels of selected word lines during a program operation of a nonvolatile memory device responsive to a restore operation in a cancel mode and a loop mode, according to some example embodiments;

FIG. 10 is a block diagram illustrating a recovery pattern manager in accordance with some demonstrative embodiments;

FIG. 11A is a flowchart illustrating operation of a recovery mode manager using a pause command counter to determine a recovery mode in accordance with some demonstrative embodiments;

FIG. 11B is a graph illustrating voltage levels of selected word lines during a series of operations of a recovery mode manager using a pause command counter to determine a recovery mode, according to some example embodiments;

FIG. 12A is a flowchart illustrating operation of a recovery mode manager using a supply voltage determiner to determine a recovery mode according to some example embodiments;

FIG. 12B is a graph illustrating voltage levels of selected word lines during operation of a recovery mode manager using a supply voltage determiner to determine a recovery mode according to some example embodiments;

FIG. 13A is a flowchart illustrating operation of a recovery mode manager using a word line voltage level determiner to determine a recovery mode according to some example embodiments;

FIG. 13B is a graph illustrating voltage levels of selected word lines during operation of a recovery mode manager using a word line voltage level determiner to determine a recovery mode, according to some example embodiments;

FIG. 14A is a flowchart illustrating operation of a recovery mode manager using a pause time counter to determine a recovery mode in accordance with some demonstrative embodiments;

FIG. 14B is a graph illustrating voltage levels of selected word lines during operation of a recovery mode manager using a pause time counter to determine a recovery mode, according to some example embodiments;

FIG. 15 is a flowchart illustrating operation of a recovery mode manager using two or more of a pause command counter, a supply voltage determiner, a word line voltage level determiner to determine a recovery mode according to some example embodiments; and

fig. 16 is a block diagram of an example in which a non-volatile memory device is applied to a Solid State Drive (SSD) system, according to some example embodiments.

Detailed Description

FIG. 1 is a block diagram illustrating a non-volatile memory system according to some example embodiments.

Referring to fig. 1, a nonvolatile memory system 1 may be provided within a computing system such as a workstation, a netbook (netbook), a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless telephone, a mobile telephone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game device, a navigation device, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a digital recorder, a digital image recorder, a digital picture player, a digital video recorder, and a digital video player.

The nonvolatile memory system 1 may include a memory controller 20 and a nonvolatile memory device 10. In some example embodiments, each of the HOST, the memory controller 20, and the nonvolatile memory device 10 may be provided as one chip, one package, one module, and the like. Alternatively, the memory controller 20 and the nonvolatile memory device 10 may be mounted in packages such as a stacked package (PoP), ball Grid Array (BGA), chip Scale Package (CSP), plastic Leaded Chip Carrier (PLCC), plastic dual in-line package (PDIP), die in die form, chip On Board (COB), ceramic dual in-line package (CERDIP), plastic Metric Quad Flat Package (MQFP), thin Quad Flat Package (TQFP), small Outline Integrated Circuit (SOIC), shrink Small Outline Package (SSOP), thin Small Outline Package (TSOP), system In Package (SIP), multi-chip package (MCP), wafer level fabrication package (WFP), and wafer level process stack package (WSP).

Memory controller 20 may control non-volatile memory device 10 in response to write requests or read requests received from HOST. For example, the memory controller 20 may transmit a write command cmd_w or a read command cmd_r to the nonvolatile memory device 10 in response to a write request or a read request received from the HOST. In addition, the memory controller 20 may transmit a suspend command cmd_spd, a resume command cmd_rsm, and/or an address ADDR. The address ADDR sent by the memory controller 20 to the nonvolatile memory device 10 may be a physical address in the nonvolatile memory device 10. The memory controller 20 may exchange DATA with the nonvolatile memory device 10. In addition, the memory controller 20 may receive a ready/busy signal RnB from the nonvolatile memory device 10.

The nonvolatile memory device 10 may operate in response to signals received from the memory controller 20, such as a write operation, a read operation, and an erase operation. In some example embodiments, the nonvolatile memory device 10 may send a ready/busy signal RnB to the memory controller 20. The ready/busy signal RnB may be a signal indicating whether the nonvolatile memory device 10 is operating. For example, the ready/busy signal RnB may be in a busy state (e.g., logic low) when the nonvolatile memory device 10 is performing a program operation. The ready/busy signal RnB may be in a ready state (e.g., logic high) when the nonvolatile memory device 10 is not performing operations such as a write operation, a read operation, and an erase operation.

The memory controller 20 may transmit a suspend command cmd_spd to the nonvolatile memory device 10 in response to the ready/busy signal RnB and a write request or a read request received from the HOST.

Memory controller 20 may receive a read request with a high priority from HOST. In this specification, a read request having a high priority may be referred to as an urgent read request. The memory controller 20 may transmit a suspend command cmd_spd to the nonvolatile memory device 10 in response to the received urgent read request. In other words, when the ready/busy signal RnB is in a busy state, the memory controller 20 may transmit the suspend command cmd_spd to the nonvolatile memory device 10 in response to a received read request having a high priority. The nonvolatile memory device 10 may perform a restore operation on a selected word line to be programmed in response to the suspend command cmd_spd.

After the restoration operation is completed, the nonvolatile memory device 10 may perform a read operation in response to the urgent read request. The nonvolatile memory device 10 may output the ready/busy signal RnB in a ready state after the completion of the read operation in response to the urgent read request, and the memory controller 20 may resume the program operation by outputting a resume command cmd_rsm to the nonvolatile memory device 10 accordingly.

The nonvolatile memory device 10 may include a memory cell array 110, a control logic means 120, and a recovery mode manager 130. The memory cell array 110 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, some exemplary embodiments will be described for a case in which a plurality of memory cells are NAND flash memory cells. However, some example embodiments are not limited thereto. In some example embodiments, the plurality of memory cells may be resistive memory cells, such as resistive read only memory (RAM) (RRAM), phase change RAM (PRAM), and Magnetoresistive RAM (MRAM).

According to some example embodiments, the operations described herein as being performed by any or all of the control logic device 120 and the recovery mode manager 130 may be performed by at least one processor executing program code containing instructions corresponding to the operations. The instructions may be stored in a memory. The term "processor" as used in this disclosure may refer to a data processing apparatus, e.g., a hardware implementation, having circuitry physically configured to perform desired operations, including operations represented, e.g., by code and/or instructions contained in a program. In at least some example embodiments, the hardware-implemented data processing apparatus described above may include, but is not limited to, microprocessors, central Processing Units (CPUs), processor cores, multi-core processors, multiprocessors, application Specific Integrated Circuits (ASICs), and Field Programmable Gate Arrays (FPGAs).

The memory cell array 110 may be a three-dimensional (3D) memory array. The 3D memory array may be monolithically formed on at least one physical level of a memory cell array comprising an active region on a silicon substrate, and circuitry associated with the operation of the memory cells on or within the silicon substrate. The term "monolithic" may mean that the layers making up each level of the memory cell array are stacked directly over the layers of each lower level of the memory cell array. The 3D memory array may include cell strings arranged in a vertical direction such that at least one memory cell is placed on another memory cell. At least one memory cell may include a charge trapping layer. However, some example embodiments are not limited thereto. In some example embodiments, the memory cell array 110 may be a two-dimensional (2D) memory cell array.

In some exemplary embodiments, each memory cell included in the memory cell array 110 may be a multi-level cell (MLC) that stores two or more bits of data. For example, the memory cell may be an MLC that stores 2 bits of data. As another example, the memory cell may be a Three Level Cell (TLC) that stores 3 bits of data. However, some example embodiments are not limited thereto. In some example embodiments, some memory cells included in the memory cell array 110 may be Single Level Cells (SLCs) storing 1 bit of data, and some other memory cells may be MLCs.

The control logic device 120 may generally control various operations in the nonvolatile memory device 10 based on the DATA, the address ADDR, and the commands cmd_w, cmd_r, cmd_spd, and cmd_rsm received from the memory controller 20. For example, the control logic device 120 may output various control signals to write DATA to the memory cell array 110 or read DATA from the memory cell array 110. In addition, the control logic device 120 may output a control signal to perform a reset on the selected word line.

The recovery mode manager 130 may determine the recovery mode based on the suspend command cmd_spd. Depending on the restoration timing, the restoration mode may include a cancel mode in which restoration is performed immediately or simultaneously after receiving the suspension command cmd_spd, and a loop mode in which restoration is performed after a program loop included in a program operation has been performed. In some exemplary embodiments, the recovery mode manager 130 may determine the recovery mode differently depending on the reception timing of the pause command cmd_spd. In some exemplary embodiments, the recovery mode manager 130 may determine the recovery mode differently depending on the number of received pause commands cmd_spd. Because the cancel mode is restored simultaneously, the cancel mode may have the advantage of responding simultaneously to an urgent read request, but may have the disadvantage of delay in the programming operation. On the other hand, since the loop mode first completes the program operation and then responds to the urgent read request, the program operation may not be delayed, but there may be a disadvantage of delay in responding to the urgent read request. According to some example embodiments, the recovery mode manager 130 may determine the recovery mode to be one of two different modes based on the pause command cmd_spd, thereby alleviating or preventing write starvation (write state) in which a program request is delayed, and performing an efficient emergency read operation.

In this specification, a case where an urgent read request is received during a program operation is explained, but it should be understood that analogy can be applied even when an urgent read request is received during an erase operation.

Fig. 2 is a block diagram illustrating a non-volatile memory device 10 according to some example embodiments. The repetitive description that has been given above with reference to fig. 1 will be omitted.

Referring to fig. 2, the nonvolatile memory device 10 may include a memory cell array 110, a control logic device 120, a recovery mode manager 130, a voltage generator 140, a row decoder 150, and an input/output (I/O) circuit 160. According to some example embodiments, the operations described herein as being performed by any or all of voltage generator 140, row decoder 150, and I/O circuit 160 may be performed by at least one processor executing program code containing instructions corresponding to the operations. The instructions may be stored in a memory.

Based on various commands cmd_w, cmd_r, cmd_spd, and cmd_rsm received from the memory controller (20 in fig. 1), and the address ADDR, the control logic device 120 may output various control signals to write DATA to the memory cell array 110 or read DATA from the memory cell array 110. Further, when the nonvolatile memory device 10 receives the suspend command cmd_spd, the restoration mode manager 130 may accordingly determine the restoration mode RM and output the determined restoration mode RM to the control logic device 120. The restoration mode RM may include a cancel mode CM in which restoration is performed immediately or simultaneously after receiving the suspension command cmd_spd, and a loop mode LM in which restoration is performed after a program operation corresponding to a program loop has been performed. Based on RM, the control logic device 120 may output various control signals for performing a restore operation to the memory cell array 110. The cancel mode CM and the loop mode LM are described below with reference to fig. 9.

Based on the voltage control signal ctrl_vol, the voltage generator 140 may generate various types of voltages for performing read, write, and erase operations in the memory cell array 110. The voltage generator 140 may generate a word line voltage VWL (e.g., a program voltage or a write voltage), a read voltage, a pass voltage (or an unselected word line voltage), a verify voltage, a restore voltage, etc.

The row decoder 150 may select some word lines WL in response to the row address X-ADDR. The row decoder 150 may transmit the word line voltage VWL to the word line WL. In a program operation, the row decoder 150 may apply a program voltage and a verify voltage to a selected word line, and a program inhibit voltage to unselected word lines. In a read operation, the row decoder 150 may apply a read voltage to a selected word line and a read inhibit voltage to unselected word lines. In the restore operation, the row decoder 150 may apply a restore voltage to the selected word line. Further, the row decoder 150 may select some string select lines or some ground select lines in response to the row address X-ADDR.

The I/O circuit 160 may receive DATA from the outside (e.g., the memory controller 20) and store the input DATA in the memory cell array 110. Further, the I/O circuit 160 may read the DATA from the memory cell array 110 and output the read DATA to the outside. The I/O circuit 160 may include a page buffer (not shown) corresponding to the bit line BL. The page buffer may be connected to the memory cell array 110 via bit lines BL, and some of the bit lines BL may be selected in response to a column address Y-ADDR received from the control logic device 120. In a program operation, the page buffer may operate as a write driver, and the DATA may be programmed to be stored in the memory cell array 110.

Fig. 3 is a flowchart illustrating operation of the non-volatile memory device 10 according to some example embodiments.

Referring to fig. 2 and 3, the nonvolatile memory device 10 may perform a program operation corresponding to a first program cycle of a plurality of program cycles (S110). During the first programming cycle, the nonvolatile memory device 10 may receive a suspend command cmd_spd for emergency reading from the memory controller 20 (S120). The nonvolatile memory device 10 may determine the restore mode RM based on the suspend command cmd_spd (S130). When the determined restoration mode RM is the cancellation mode CM (yes at S140), the nonvolatile memory device 10 may perform a restoration operation in the cancellation mode CM (S150). Otherwise, when the determined restoration mode RM is not the cancellation mode CM (no at S140), the nonvolatile memory device 10 may perform a restoration operation in the loop mode LM (S160). Although fig. 3 illustrates some exemplary embodiments for determining whether the recovery pattern RM is CM, some exemplary embodiments may include determining whether the recovery pattern RM is LM.

Fig. 4A is a flowchart illustrating operation of the non-volatile memory device 10 according to some example embodiments. In detail, fig. 4A is a flowchart showing the operation of the nonvolatile memory device 10 restored in the cancel mode CM according to operation S150 in fig. 3.

Referring to fig. 2 and 4A, the nonvolatile memory device 10 may determine the recovery mode RM as CM and accordingly perform a recovery operation by applying a recovery voltage to the selected word line WL immediately or simultaneously (S151). In other words, the nonvolatile memory device 10 may perform the restore operation immediately or simultaneously in response to receiving the suspend command cmd_spd in the CM. After the restoration operation is completed, the nonvolatile memory device 10 may perform an emergency read operation in response to the read command cmd_r (S152). Although not shown, in some exemplary embodiments, after the restoration operation is completed, the nonvolatile memory device 10 may output a ready signal as a ready/busy signal RnB, and the memory controller (20 in fig. 1) may output a read command cmd_r accordingly.

After the emergency reading operation is completed, the nonvolatile memory device 10 may receive a recovery command cmd_rsm (S153). Although not shown, in some exemplary embodiments, after the completion of the emergency read operation, the nonvolatile memory device 10 may output a ready signal as the ready/busy signal RnB, and the memory controller (20 in fig. 1) may output a recovery command cmd_rsm accordingly. The nonvolatile memory device 10 may perform the program operation corresponding to the first program loop again in response to the recovery command cmd_rsm (S154).

Fig. 4B is a flowchart illustrating operation of the non-volatile memory device 10 according to some example embodiments. In detail, fig. 4B is a flowchart showing the operation of the nonvolatile memory device 10 restored in the loop mode LM according to operation S160 in fig. 3.

Referring to fig. 2 and 4B, the nonvolatile memory device 10 may determine the restoration mode RM as the loop mode LM, and accordingly perform a program operation corresponding to the first program loop (S161). In other words, the nonvolatile memory device 10 may continue the program operation corresponding to the first program loop regardless of whether the pause command cmd_spd is received in the LM. In some example embodiments, the program operation corresponding to the first program cycle may include a verify operation. After the programming operation corresponding to the first programming cycle is completed, the nonvolatile memory device 10 may perform a restore operation by applying a restore voltage to the selected word line (S162).

After the restoration operation is completed, the nonvolatile memory device 10 may perform an emergency read operation in response to the read command cmd_r (S163). Although not shown, in some exemplary embodiments, after the restoration operation is completed, the nonvolatile memory device 10 may output a ready signal as a ready/busy signal RnB, and the memory controller (20 in fig. 1) may output a read command cmd_r accordingly. After the completion of the emergency reading operation, the nonvolatile memory device 10 may receive a recovery command cmd_rsm (S164). Although not shown, in some exemplary embodiments, after the completion of the emergency read operation, the nonvolatile memory device 10 may output a ready signal as the ready/busy signal RnB, and the memory controller (20 in fig. 1) may output a recovery command cmd_rsm accordingly. Since the program operation of the first program loop has been completed, the nonvolatile memory device 10 may perform a program operation corresponding to a second program loop, which is the next loop of the first program loop, in response to the recovery command cmd_rsm (S165).

Fig. 5 is a circuit diagram illustrating a single-level memory block BLKa included in a memory cell array according to some exemplary embodiments.

Referring to fig. 5, a memory cell array (e.g., 110 in fig. 2) may be a memory cell array of a horizontal NAND flash memory, and may include a plurality of memory blocks BLKa. Each memory block BLKa may include m (m is an integer of 2 or more) cell strings STR in which a plurality of memory cells MC are connected in series in a direction from a bit line BL0 to a bit line BLm-1. Each memory block BLKa may further include a ground selection line GSL, a common source line CSL, a string selection transistor SST, and a ground selection transistor GST. As an example, fig. 5 shows a case in which each cell string STR contains eight memory cells MC.

The NAND flash memory device having the structure as shown in fig. 5 can be erased block by block and programmed in units of pages corresponding to the word lines WL0 to WL7, respectively. Fig. 5 shows an example in which n (n is an integer) pages for n word lines (WL 1 to WLn) are provided in one block. In addition, the nonvolatile memory device 10 in fig. 1 and 2 may further include a plurality of memory cell arrays that perform the same operation in the same structure as the above-described memory cell array 110.

Fig. 6 is a circuit diagram illustrating a multi-level memory block BLK0 included in a memory cell array according to some exemplary embodiments.

Referring to fig. 6, a memory cell array (e.g., 110 in fig. 2) may be a memory cell array of a vertical NAND flash memory, and include a plurality of memory blocks BLK0. Each memory block BLK0 may include a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. According to some exemplary embodiments, the number of NAND strings, word lines, bit lines, ground select lines, and string select lines may vary differently.

The NAND strings NS11, NS21 and NS31 may be arranged between the first bit line BL1 and a common source line CSL. The NAND strings NS12, NS22 and NS32 may be arranged between a second bit line BL2 and a common source line CSL. The NAND strings NS13, NS23 and NS33 may be arranged between the third bit line BL3 and the common source line CSL. Each of the NAND strings (e.g., NS 11) may include a string selection transistor SST, first to eighth memory cells MC1 to MC8, and a ground selection transistor GST, which are connected in series.

Strings commonly connected to one bit line may form one column. For example, strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 may correspond to a first column, strings NS12, NS22, and NS32 commonly connected to the second bit line BL2 may correspond to a second column, and strings N13, N23, and N33 commonly connected to the third bit line BL3 may correspond to a third column.

Strings connected to one string selection line may form rows. For example, strings NS11, NS12, and NS13 connected to the first string selection line SSL1 may correspond to a first row, strings NS21, NS22, and NS3 connected to the second string selection line SSL2 may correspond to a second row, and strings N31, N32, and NS33 connected to the third string selection line SSL3 may correspond to a third row.

The string selection transistors SST may be connected to corresponding string selection lines SSL1 to SSL3. Each of the first to eighth memory cells MC1 to MC8 may be connected to a corresponding word line WL1 to WL8. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1 to BL3, and the ground selection transistor GST may be connected to the common source line CSL.

Word lines (e.g., WL 1) on the same level may be commonly connected to each other, while string selection lines SSL1 through SSL3 may be spaced apart from each other, and ground selection lines GSL1 through GSL3 may be spaced apart from each other. For example, when the memory cells connected to the first word line WL1 and belonging to the strings N11, N12, and N13 are programmed, the first word line WL1 and the first string selection line SSL1 may be selected. The ground selection lines GSL1 to GSL3 may be commonly connected to each other.

Fig. 7 is a perspective view of the memory block BLK0 of fig. 6.

Referring to fig. 7, each memory block BLK0 included in a memory cell array (e.g., 110 in fig. 2) may be formed in a vertical direction with respect to the substrate SUB. In fig. 7, the memory block BLK0 is shown to contain two selection lines GSL and SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3, but the number thereof may be actually greater or less than these.

The substrate SUB may be of a first conductivity type (e.g., p-type), and may provide a common source line CSL extending therein in a first direction (e.g., Y-direction) and of a second conductivity type (e.g., n-type). The plurality of insulating layers IL extending in the first direction may be sequentially provided on a region of the substrate SUB between two adjacent common source lines CSL in a third direction (e.g., Z direction), and the plurality of insulating layers IL may be separated from each other by a distance in the third direction. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

A plurality of pillars P may be formed, which are sequentially arranged in the first direction on a region between two adjacent common source lines CSL of the substrate SUB, and penetrate the plurality of insulating layers IL in the third direction. For example, the plurality of pillars P may penetrate the plurality of insulating layers IL and contact the substrate SUB. In detail, the surface layer S of each pillar P may contain a first type of silicon material and may function as a channel region. The inner layer I of each pillar P may comprise an insulating material such as silicon oxide or an air gap.

The charge storage layer CS may be provided along the insulating layer IL, the pillars P, and the exposed surface of the substrate SUB in a region between two adjacent common source lines CSL. The charge storage layer CS may include a gate insulating layer (or "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, the gate electrode GE including the selection lines GSL and SSL and the word lines WL1 to WL8 may be provided on the exposed surface of the charge storage layer CS in a region between two adjacent common source lines CSL.

The drain or drain contact DR may be provided on the plurality of pillars P, respectively. For example, the drain electrode DR may include a silicon material doped with an impurity of the second conductivity type. Bit lines BL1 to BL3 extending in a second direction (e.g., X direction) and separated from each other by a distance in the first direction may be provided on the drain DR.

Fig. 8 is a graph illustrating voltage levels of selected word lines during a series of programming operations of the non-volatile memory device 10 according to some example embodiments. In the graph shown in fig. 8, the x-axis may represent time and the y-axis may represent voltage level. For convenience of description, it is assumed that the nonvolatile memory device (10 in fig. 1) performs a program operation on a page basis. However, some exemplary embodiments are not limited thereto, and the programming method of the nonvolatile memory device (10 in fig. 1) may be variously changed and applied.

Referring to fig. 2 and 8, the nonvolatile memory device 10 may perform a program operation based on an Incremental Step Pulse Programming (ISPP) method. In other words, the nonvolatile memory device 10 may perform a Program operation through a plurality of Program loops Program Loop 1 to Program Loop n (n is an integer of 1 or more). Each of the Program operations corresponding to the plurality of Program loops Program Loop 1 to Program Loop n may be configured to include a Program voltage applying operation in which Program voltages vpgm_1 to vpgm_n (n is an integer of 1 or more) are applied and a verifying operation in which a verifying voltage Vvfy is verified. As the number of program loops increases, the applied program voltage Vpgm may increase by a program voltage increment Δvpgm. Memory cells that have been programmed through in a verify operation may be program inhibited in the next program cycle.

Fig. 9 is a graph illustrating voltage levels of selected word lines during a program operation of the nonvolatile memory device 10 in response to a restore operation in a cancel mode and a loop mode according to some example embodiments. In detail, fig. 9 is an enlarged view of the first Program Loop 1 in part (a) in fig. 8. In the graph shown in fig. 9, the x-axis may represent time and the y-axis may represent voltage level.

Referring to fig. 1 and 9, the voltage level of a selected word line to be programmed in the nonvolatile memory device 10 may be gradually increased until the voltage level reaches the first program voltage Vpgm1. The nonvolatile memory device 10 may receive the suspend command cmd_spd at the first time ta. In the CM, the nonvolatile memory device 10 may perform a restore operation immediately or simultaneously by applying a restore voltage to the selected word line at the first time ta when the suspend command cmd_spd is received. Accordingly, at the first time ta, the voltage level of the selected word line may drop to the reset voltage. After the emergency reading operation has been performed, the nonvolatile memory device 10 may perform the first Program Loop1, which has been suspended, in response to the first resume command cmd_rsm1.

In the LM, the nonvolatile memory device 10 may perform a Program operation corresponding to the first Program Loop1, although the suspend command cmd_spd is received. Although not shown, in some example embodiments, the nonvolatile memory device 10 may simultaneously perform the verifying operation included in the first Program Loop 1. At the second time tb when the first Program Loop1 is completed, the nonvolatile memory device 10 may perform a restore operation by applying a restore voltage to the selected word line. Accordingly, at the second time tb, the voltage level of the selected word line may drop to the restore voltage. After the emergency reading operation has been performed, the nonvolatile memory device 10 may perform a second Program Loop 2 in response to the second recovery command cmd_rsm2, the second Program Loop 2 being a sequence subsequent to the first Program Loop 1.

In the CM, since restoration is performed immediately or simultaneously at the first time ta when the pause command cmd_spd is received, the Program operation may be delayed, and the Program operation corresponding to the first Program Loop 1 may be completed after the part (a), but immediately or simultaneously responds to the urgent read request. In the LM, since the program operation is first completed and then an urgent read request corresponding to the suspend command cmd_spd is responded to, the program operation may not be delayed, but there may be a delay corresponding to the urgent read request. According to some exemplary embodiments, by differently determining the recovery pattern RM based on the suspend command cmd_spd, write starvation (write state) in which a program request is delayed may be alleviated or prevented, and an efficient emergency read operation may be performed.

Fig. 10 is a block diagram illustrating a recovery pattern manager 130 according to some example embodiments. The repetitive description that has been given above with reference to fig. 1 will be omitted.

Referring to fig. 10, the recovery mode manager 130 may include a pause command counter 131, a supply voltage determiner 132, a word line voltage level determiner 133, and a pause time counter 134. As described above with reference to fig. 1, the restoration mode manager 130 may determine the restoration mode RM based on the suspension command cmd_spd received from the memory controller (20 in fig. 1) and output the determined restoration mode RM to the control logic device (120 in fig. 1). According to some example embodiments, the operations described herein as being performed by any or all of the pause command counter 131, the supply voltage determiner 132, the word line voltage level determiner 133, and the pause time counter 134 may be performed by at least one processor executing program code containing instructions corresponding to the operations. The instructions may be stored in a memory.

The suspend command counter 131 may count the suspend command cmd_spd received from the memory controller (20 of fig. 1) and determine the resume mode RM by comparing the suspend command count generated as a result thereof with the reference count. In some example embodiments, a reference count may be determined. In some exemplary embodiments, the pause command counter 131 may determine the restoration mode RM as the cancel mode CM when the pause command count is less than the reference count, and may determine the restoration mode RM as the loop mode LM when the pause command count is equal to or greater than the reference count. In some exemplary embodiments, the pause command counter 131 may include at least one counter or trigger (flip-flop) for pause command counting. This will be described below with reference to fig. 11A and 11B.

By receiving information of a supply voltage level of a supply voltage supplied to the selected word line upon receiving a suspend command cmd_spd from the control logic device (120 in fig. 1), and by comparing the received supply voltage level with a reference voltage, the supply voltage determiner 132 can determine the restoration mode RM. In a programming operation, the nonvolatile memory device (10 in fig. 1) may apply a supply voltage having a stepped-up voltage level to a selected word line to increase the voltage level of the selected word line. In some exemplary embodiments, a reference voltage may be determined. In some exemplary embodiments, the supply voltage determiner 132 may determine the restoration mode RM as the cancel mode CM when the supply voltage level is lower than the reference voltage level, and the supply voltage determiner 132 may determine the restoration mode RM as the loop mode LM when the supply voltage level is equal to or higher than the reference voltage level. This will be described below with reference to fig. 12A and 12B.

In some exemplary embodiments, the nonvolatile memory device (10 in fig. 1) may apply different supply voltages to the selected word line through a plurality of operations. In some example embodiments, the control logic device (120 in fig. 1) may generate the ladder information according to the supply voltage level, and the supply voltage determiner 132 may determine the restoration pattern RM based on the ladder information received from the control logic device (120 in fig. 1).

At the instant when the suspend command cmd_spd is received from the memory cell array (110 of fig. 1), the word line voltage level determiner 133 may receive information about the voltage level of the selected word line and determine the restore mode RM by comparing the received selected word line voltage level with the reference voltage. In some exemplary embodiments, a reference voltage may be determined. In some exemplary embodiments, the word line voltage level determiner 133 may determine the recovery mode RM as the cancel mode CM when the selected word line voltage level is lower than the reference voltage level, and the word line voltage level determiner 133 may determine the recovery mode RM as the loop mode LM when the selected word line voltage level is equal to or higher than the reference voltage level. This will be described below with reference to fig. 13A and 13B.

The suspension time counter 134 may count a time from a moment when the voltage level of the selected word line is increased for the program operation starting from the nonvolatile memory device (10 in fig. 1) to a moment when the suspension command cmd_spd is received, and the reset mode RM may be determined by comparing the suspension time count with the reference time. In some exemplary embodiments, a reference time may be determined. In some exemplary embodiments, the pause time counter 134 may determine the restoration mode RM as the cancel mode CM when the pause time is shorter than the reference time, and the pause command counter may determine the restoration mode RM as the loop mode LM when the pause time is equal to or longer than the reference time. This will be described below with reference to fig. 14A and 14B.

In fig. 10, the recovery mode manager 130 may include a pause command counter 131, a supply voltage determiner 132, a word line voltage level determiner 133, and a pause time counter 134, but some exemplary embodiments are not limited thereto. The recovery pattern manager 130 may include at least one of a pause command counter 131, a supply voltage determiner 132, a word line voltage level determiner 133, and a pause time counter 134, and may determine the recovery pattern RM by using components included therein.

Fig. 11A is a flowchart illustrating the operation of the recovery pattern manager 130 according to some example embodiments. In detail, fig. 11A illustrates some exemplary embodiments in which the restoration pattern manager 130 determines the restoration pattern RM by using the pause command counter 131.

Referring to fig. 2 and 11A, the recovery mode manager 130 may receive a suspension command cmd_spd for emergency reading from the memory controller (20 of fig. 1) (S211). The recovery mode manager 130 may generate a pause command count Nspd by counting the received pause command cmd_spd during a first Program Loop 1 among the plurality of Program loops Program Loop 1 through Program Loop n (S212). The recovery pattern manager 130 may compare the pause command count Nspd with the reference count Nth (S213). When the suspension command count Nspd is smaller than the reference count Nth, the restoration mode manager 130 may output the cancellation mode CM as the restoration mode RM to the control logic device 120 (S214). Otherwise, when the pause command count Nspd is not less than the reference count Nth, the restoration mode manager 130 may output the loop mode LM to the control logic device 120 as the restoration mode RM (S215).

Fig. 11B is a graph illustrating voltage levels of selected word lines during a series of operations of the recovery mode manager 130 according to some example embodiments. In detail, fig. 11B illustrates some exemplary embodiments in which the restoration pattern manager 130 determines the restoration pattern RM by using the pause command counter 131. Further, fig. 11B shows an example in which the reference count Nth is "4".

Referring to fig. 2, 11A and 11B, while the nonvolatile memory device 10 performs the first Program Loop 1, the recovery mode manager 130 may receive the first pause command cmd_spd1 at the first time t1 and count the pause command count Nspd to "1" accordingly. The restoration mode manager 130 may output the cancellation mode CM to the control logic device 120 as the restoration mode RM because the "suspend command count Nspd or" 1 "is smaller than the reference count Nth or" 4 ". In response to the received CM, the control logic device 120 may perform a restore operation immediately or simultaneously by reducing the voltage level of the selected word line to the restore voltage Vrcv. Although not shown, after the restore operation has been completed, the nonvolatile memory device 10 may perform an emergency read operation between the first time t1 and the second time t 2. After the completion of the emergency reading operation, at the second time t2, the nonvolatile memory device 10 may perform the first Program Loop 1 again in response to the recovery command cmd_rsm.

At a third time t3, the recovery pattern manager 130 may receive the second pause command cmd_spd2 and count the pause command count Npsd to "2" accordingly. Since the suspension command count Nspd or "2" is smaller than the reference count Nth or "4", the restoration mode manager 130 may output the cancellation mode CM to the control logic device 120 as the restoration mode RM. In response to the received CM, the control logic device 120 may perform a restore operation immediately or simultaneously by reducing the voltage level of the selected word line to the restore voltage Vrcv. Although not shown, after the restore operation has been completed, the nonvolatile memory device 10 may perform an emergency read operation between the third time t3 and the fourth time t 4. After the completion of the emergency reading operation, the nonvolatile memory device 10 may perform the first Program Loop 1 again in response to the recovery command cmd_rsm at the fourth time t 4.

At a fifth time t5, the recovery pattern manager 130 may receive the third pause command cmd_spd3 and count the pause command count Npsd to "3" accordingly. Since the suspension command count Nspd or "3" is smaller than the reference count Nth or "4", the restoration mode manager 130 may output the cancellation mode CM to the control logic device 120 as the restoration mode RM. In response to the received CM, the control logic device 120 may perform a restore operation immediately or simultaneously by reducing the voltage level of the selected word line to the restore voltage Vrcv. Although not shown, after the restore operation has been completed, the nonvolatile memory device 10 may perform an emergency read operation between the fifth time t5 and the sixth time t 6. After the completion of the emergency reading operation, the nonvolatile memory device 10 may perform the first Program Loop 1 again in response to the recovery command cmd_rsm at a sixth time t 6.

At a seventh time t7, the recovery pattern manager 130 may receive the fourth pause command cmd_spd4 and count the pause command count Npsd to "4" accordingly. Since the pause command count Nspd or "4" is not less than the reference count Nth or "4", the restoration mode manager 130 may output the loop mode LM to the control logic device 120 as the restoration mode RM. In response to the received LM, the control logic device 120 can complete the first Program Loop 1 by increasing the voltage level of the selected word line to the first Program voltage Vpgm1 without performing a restore operation immediately or simultaneously. At an eighth time t8 when the first Program Loop 1 is completed, the nonvolatile memory device 10 may perform a restore operation. Although not shown, after the restore operation has been completed, the nonvolatile memory device 10 may perform an emergency read operation between the eighth time t8 and the ninth time t 9. After the emergency reading operation is completed, at a ninth time t9, the nonvolatile memory device 10 may perform a second Program Loop 2 in response to the recovery command cmd_rsm, the second Program Loop 2 being a sequence subsequent to the first Program Loop 1.

Fig. 12A is a flowchart illustrating the operation of the recovery pattern manager 130 according to some example embodiments. In detail, fig. 12A illustrates some exemplary embodiments in which the recovery pattern manager 130 determines the recovery pattern RM by using the supply voltage determiner 132.

Referring to fig. 2 and 12A, the recovery mode manager 130 may receive a suspend command cmd_spd of an urgent read from the memory controller (20 in fig. 1) (S221). Upon receiving the suspend command cmd_spd from the control logic device 120, the recovery mode manager 130 may receive supply voltage information (S222). The recovery mode manager 130 may compare the supply voltage Vspl with the reference voltage Vth (S223). When the supply voltage Vspl is lower than the reference voltage Vth, the recovery mode manager 130 may output the cancel mode CM as the recovery mode RM to the control logic device 120 (S224). Otherwise, when the supply voltage Vspl is not lower than the reference voltage Vth, the recovery mode manager 130 may output the loop mode LM as the recovery mode RM to the control logic device 120 (S225).

As described above with reference to fig. 10, in some exemplary embodiments, the recovery pattern manager 130 may determine the recovery pattern RM according to ladder information based on the supply voltage level from the control logic device 120. In some exemplary embodiments, the restoration mode manager 130 may output the cancellation mode CM as the restoration mode RM to the control logic device 120 when the ladder information is before the reference ladder, and the restoration mode manager 130 may output the loop mode LM as the restoration mode RM to the control logic device 120 when the ladder information is not before the reference ladder.

Fig. 12B is a graph illustrating voltage levels of selected word lines during operation of the recovery mode manager 130 according to some example embodiments. In detail, fig. 12B illustrates some exemplary embodiments in which the recovery pattern manager 130 determines the recovery pattern RM by using the supply voltage determiner 132.

Referring to fig. 2, 12A and 12B, to increase the voltage level of the selected word line to the first program voltage Vpgm1, the nonvolatile memory device 10 may apply the first supply voltage Vspl1 at the first Step1, the second supply voltage Vspl2 at the second Step2, the third supply voltage Vspl3 at the third Step3, and the first program voltage Vpgm1 at the fourth Step 4. In some exemplary embodiments of fig. 12B, the voltage level of the reference voltage Vth may be higher than the second supply voltage Vspl2 and may be lower than the third supply voltage Vspl3.

In example (a), while the nonvolatile memory device 10 performs the first Program Loop 1, the recovery mode manager 130 may receive the first pause command cmd_spd1 at the first time t 1. In addition, the recovery mode manager 130 may receive information about the second supply voltage Vspl2 from the control logic device 120 at the first time t 1. Since the second supply voltage Vspl2 is lower than the reference voltage Vth, the recovery mode manager 130 may output the cancel mode CM as the recovery mode RM to the control logic device 120. In response to the received CM, the control logic device 120 may perform a restore operation immediately or simultaneously by lowering the voltage level of the selected word line (depicted as "Sel WL voltage level") to the restore voltage Vrcv. Although not shown, the nonvolatile memory device 10 may perform an emergency read operation after the restoration operation is completed. Further, after the completion of the emergency read operation, the nonvolatile memory device 10 may perform the first Program Loop 1 again in response to the recovery command cmd_rsm.

In example (b), while the nonvolatile memory device 10 performs the first Program Loop 1, the recovery mode manager 130 may receive the second pause command cmd_spd2 at the second time t 2. Further, the recovery mode manager 130 may receive information about the third supply voltage Vspl3 from the control logic device 120 at the second time t 2. Since the third supply voltage Vspl3 is not lower than the reference voltage Vth, the recovery mode manager 130 may output the circulation mode LM as the recovery mode RM to the control logic device 120. In response to the received LM, the control logic device 120 can complete the first Program Loop 1 by increasing the voltage level of the selected word line to the first Program voltage Vpgm1 without performing a restore operation immediately or simultaneously. At a third time t3 when the first Program Loop 1 is completed, the nonvolatile memory device 10 may perform a restore operation. Although not shown, the nonvolatile memory device 10 may perform an emergency read operation after the restoration operation is completed. Further, after the completion of the emergency reading operation, the nonvolatile memory device 10 may perform a second Program Loop 2 in response to the recovery command cmd_rsm, the second Program Loop 2 being a sequence subsequent to the first Program Loop 1.

The recovery pattern manager 130 may determine the recovery pattern RM by using the reference ladder. In some exemplary embodiments, in which the reference ladder is the third ladder Step3, at a first time t1, the recovery mode manager 130 may receive information from the control logic device 120 regarding the second ladder Step2, the second ladder Step2 being a ladder corresponding to the supply voltage level. Since the second Step2 precedes the third Step3 or the reference Step, the restoration mode manager 130 may output the cancellation mode CM as the restoration mode RM to the control logic device 120. On the other hand, at the second time t2, the recovery pattern manager 130 may receive information about a third Step3, the third Step3 being a Step corresponding to the supply voltage level. Since the third Step3 is not prior to the reference Step or the third Step3, the recovery pattern manager 130 may output the loop pattern LM as the recovery pattern RM to the control logic device 120.

Fig. 13A is a flowchart illustrating the operation of the recovery pattern manager 130 according to some example embodiments. In detail, fig. 13A illustrates some exemplary embodiments in which the recovery pattern manager 130 determines the recovery pattern RM by using the word line voltage level determiner 133.

Referring to fig. 2 and 13A, the recovery mode manager 130 may receive a suspend command cmd_spd of an urgent read from the memory controller (20 of fig. 1) (S231). Upon receiving the suspend command cmd_spd from the control logic device 120 or the memory cell array 110, the reset mode manager 130 may receive information about the voltage level Vswl of the selected word line (S232). The recovery mode manager 130 may compare the voltage level Vswl of the selected word line with the reference voltage Vth (S233). When the voltage level Vswl of the selected word line is lower than the reference voltage Vth, the recovery mode manager 130 may output the cancel mode CM as the recovery mode RM to the control logic device 120 (S234). Otherwise, when the voltage level Vswl of the selected word line is not lower than the reference voltage Vth, the recovery mode manager 130 may output the loop mode LM to the control logic device 120 as the recovery mode RM (S235).

Fig. 13B is a graph illustrating voltage levels of selected word lines during operation of the recovery mode manager 130 according to some example embodiments. In detail, fig. 13B illustrates some exemplary embodiments in which the recovery pattern manager 130 determines the recovery pattern RM by using the word line voltage level determiner 133.

Referring to fig. 2, 13A and 13B, in example (a), while the nonvolatile memory device 10 performs the first Program Loop 1, the recovery mode manager 130 may receive the first pause command cmd_spd1 at the first time t 1. Since the first voltage level Vswl1 of the selected word line is lower than the reference voltage Vth at the first time t1, the recovery mode manager 130 may output the cancel mode CM as the recovery mode RM to the control logic device 120. In response to the received CM, the control logic device 120 may perform a restore operation immediately or simultaneously by reducing the voltage level of the selected word line to the restore voltage Vrcv. Although not shown, the nonvolatile memory device 10 may perform an emergency read operation after the restoration operation is completed. Further, after the completion of the emergency read operation, the nonvolatile memory device 10 may perform the first Program Loop 1 again in response to the recovery command cmd_rsm.

In example (b), while the nonvolatile memory device 10 performs the first Program Loop 1, the recovery mode manager 130 may receive the second pause command cmd_spd2 at the second time t 2. Since the second voltage level Vswl2 of the selected word line is not lower than the reference voltage Vth at the second time t2, the recovery mode manager 130 may output the loop mode LM as the recovery mode RM to the control logic device 120. In response to the received LM, the control logic device 120 can complete the first Program Loop 1 by increasing the voltage level of the selected word line to the first Program voltage Vpgm1 without performing a restore operation immediately or simultaneously. At a third time t3 when the first Program Loop 1 is completed, the nonvolatile memory device 10 may perform a restore operation. Although not shown, the nonvolatile memory device 10 may perform an emergency read operation after the restoration operation is completed. Further, after the completion of the emergency reading operation, the nonvolatile memory device 10 may perform a second Program Loop 2 in response to the recovery command cmd_rsm, the second Program Loop 2 being a sequence subsequent to the first Program Loop 1.

Fig. 14A is a flowchart illustrating the operation of the recovery pattern manager 130 according to some example embodiments. In detail, fig. 14A illustrates some exemplary embodiments in which the recovery pattern manager 130 determines the recovery pattern RM by using the pause time counter 134.

Referring to fig. 2 and 14A, the recovery mode manager 130 may start counting the pause time Tspd at a moment when the voltage level of the selected word line starts to increase in response to the first Program Loop 1 (S241). The recovery mode manager 130 may receive a suspend command cmd_spd of an emergency read from the memory controller (20 of fig. 1) and calculate a suspension time from a time when the voltage level of the selected word line increases to a time when the suspend command cmd_spd is received (S242). The restoration mode manager 130 may compare the suspension time Tspd with the reference time Tth (S243). When the suspension time Tspd is shorter than the reference time Tth, the restoration mode manager 130 may output the cancellation mode CM as the restoration mode RM to the control logic device 120 (S244). When the suspension time Tspd is not shorter than the reference time Tth, the restoration mode manager 130 may output the loop mode LM to the control logic device 120 as the restoration mode RM (S245).

Fig. 14B is a graph illustrating voltage levels of selected word lines during a series of operations of the recovery mode manager 130 according to some example embodiments. In detail, fig. 14B illustrates some exemplary embodiments in which the recovery pattern manager 130 determines the recovery pattern RM by using the pause time counter 134. Further, fig. 14B shows some exemplary embodiments in which the reference time Tth is "04".

Referring to fig. 2, 14A and 14B, the recovery mode manager 130 may count the pause time Tspd from a moment when the voltage level of the selected word line starts to increase. In example (a), while the nonvolatile memory device 10 performs the first Program Loop 1, the recovery mode manager 130 may receive the first pause command cmd_spd1 at the first time t 1. At the first time t1, the restoration mode manager 130 may generate the suspension time Tspd as "03", and since the generated suspension time Tspd is less than the reference time Tth or "04", the restoration mode manager 130 may output the cancellation mode CM as the restoration mode RM to the control logic device 120. In response to the received CM, the control logic device 120 may perform a restore operation immediately or simultaneously by reducing the voltage level of the selected word line to the restore voltage Vrcv. Although not shown, the nonvolatile memory device 10 may perform an emergency read operation after the restoration operation is completed. Further, after the completion of the emergency read operation, the nonvolatile memory device 10 may perform the first Program Loop 1 again in response to the recovery command cmd_rsm.

In example (b), while the nonvolatile memory device 10 performs the first Program Loop1, the recovery mode manager 130 may receive the second pause command cmd_spd2 at the second time t 2. At the second time t2, the restoration mode manager 130 may generate the suspension time Tspd as "06", and since the generated suspension time Tspd is not less than the reference time Tth or "04", the restoration mode manager 130 may output the loop mode LM to the control logic device 120 as the restoration mode RM. In response to the received LM, the control logic device 120 can complete the first Program Loop1 by increasing the voltage level of the selected word line to the first Program voltage Vpgm1 without performing a restore operation immediately or simultaneously. At a third time t3 when the first Program Loop1 is completed, the nonvolatile memory device 10 may perform a restore operation. Although not shown, the nonvolatile memory device 10 may perform an emergency read operation after the restoration operation is completed. Further, after the completion of the emergency reading operation, the nonvolatile memory device 10 may perform a second Program Loop 2 in response to the recovery command cmd_rsm, the second Program Loop 2 being a sequence subsequent to the first Program Loop 1.

Fig. 15 is a flowchart illustrating the operation of the recovery pattern manager 130 according to some example embodiments.

Referring to fig. 2, 10, and 15, the recovery pattern manager 130 may determine the recovery pattern RM by using the condition of two or more of the pause command counter 131, the supply voltage determiner 132, and the word line voltage level determiner 133.

The recovery pattern manager 130 may receive a suspend command cmd_spd of an urgent read from the memory controller (20 in fig. 1) (S251). The recovery mode manager 130 may generate a pause command count Nspd by counting the received pause command cmd_spd during a first Program Loop 1 among the plurality of Program loops Program Loop 1 through Program Loop n (S252). The restoration mode manager 130 may compare the pause command count Nspd with the reference count Nth (S253). When the pause command count Nspd is not less than the reference count Nth, the restoration mode manager 130 may output the loop mode LM to the control logic device 120 as the restoration mode RM (S256). Otherwise, when the pause command count Nspd is less than the reference count Nth, the recovery mode manager 130 may compare the supply voltage Vspl received from the control logic device 120 with the reference voltage Vth (S254). When the supply voltage Vspl is lower than the reference voltage Vth, the recovery mode manager 130 may output the cancel mode CM as the recovery mode RM to the control logic device 120 (S255). When the supply voltage Vspl is not lower than the reference voltage Vth, the recovery mode manager 130 may output the loop mode LM as the recovery mode RM to the control logic device 120 (S256).

Fig. 15 illustrates some exemplary embodiments in which the recovery pattern manager 130 determines the recovery pattern RM by using the pause command counter 131 and the supply voltage determiner 132, but some exemplary embodiments are not limited thereto. It should be appreciated that in some exemplary embodiments, the recovery pattern RM is determined by using two or more different conditions.

Fig. 16 is a block diagram of an example in which a non-volatile memory device is applied to a Solid State Drive (SSD) system 1000, according to some example embodiments.

Referring to fig. 16, SSD system 1000 may include HOST1100 and SSD1200.SSD1200 may exchange signal SGL with HOST via a signal connector and receive power PWR via a power connector. SSD1200 may include SSD controller 1210, auxiliary power supply 1220, flash memory devices 1230, 1240, and 1250.SSD1200 can communicate with flash memory devices 1230, 1240, and 1250 over corresponding communication channels Ch1 through Chn. In this case, SSD1200 may be implemented by using some of the exemplary embodiments shown in fig. 1 to 15.

In detail, the nonvolatile memory device 10 in fig. 2 may be applied to at least one of the flash memory devices 1230, 1240, and 1250. Accordingly, when a suspend command cmd_spd of an emergency read is received during a program operation, at least one of the flash memory devices 1230, 1240, and 1250 may determine a restore mode RM based on the suspend command cmd_spd and perform a restore operation at different times depending on the determined RM. Thus, write starvation (write state) in which a program request is delayed can be alleviated or prevented, and an efficient emergency read operation can be performed.

The nonvolatile memory device according to some exemplary embodiments may be applied not only to the SSD1200 but also to a memory card system, a computing system, a Universal Flash Storage (UFS), and the like. Further, the method of operating a nonvolatile memory device according to some example embodiments may be applied to various electronic systems including nonvolatile memories.

While certain exemplary embodiments have been particularly shown and described, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of some exemplary embodiments as defined by the following claims.

Claims

1. A method performed by a non-volatile memory device, the method comprising:

initiating a first programming operation corresponding to a first programming cycle among a plurality of programming cycles;

receiving a pause command of an emergency read operation during the first program operation;

determining a resume time from among a first time and a second time based on the pause command and at least one of a pause time count and a number of pause commands, the first time being concurrent with receiving the pause command, the second time being after completion of the first programming operation, the pause time count being an amount of time between a first time at which a voltage of a selected word line begins to increase and a second time at which the pause command is received, and the number of pause commands being a number of pause commands received while the first programming operation is being performed; and

The restore is initiated at the restore time by applying a restore voltage to the selected word line.

2. The method of claim 1, further comprising:

performing the emergency read operation after the restoration is completed;

receiving a recovery command for performing a programming operation; and

in response to receiving the resume command, a programming operation is initiated.

3. The method of claim 2, wherein initiating the programming operation includes, when the restoration time is the first time, re-initiating the first programming operation.

4. The method of claim 2, wherein initiating the programming operation includes, when the recovery time is the second time, initiating a second programming operation corresponding to a second programming cycle among the plurality of programming cycles, the second programming cycle corresponding to a next cycle after the first programming cycle.

5. The method of claim 1, wherein the first programming operation includes sequentially applying a plurality of stepwise increasing supply voltages to the selected word line, the plurality of stepwise increasing supply voltages including a reference supply voltage; and is also provided with

Determining the restoration time is based on determining the restoration time as follows:

At least one of the pause time count and the pause command number, and

a determination is made as to whether the pause command was received prior to application of the reference supply voltage.

6. The method of claim 1, wherein the first programming operation includes increasing a voltage of the selected word line.

7. The method of claim 6, wherein determining the restoration time instant is based on determining the restoration time instant as follows:

at least one of the pause time count and the pause command number; and

when the pause command is received, a determination is made as to whether the voltage of the selected word line is less than a reference voltage.

8. The method of claim 6, further comprising determining a pause time count by determining an amount of time between the first time and the second time.

9. The method of claim 8, wherein

Determining the restoration time based on the pause time count is performed by,

determining the restoration time as the first time in response to the pause time count being less than a reference time; and

in response to the pause time count being equal to or greater than the reference time, the restoration time is determined to be the second time.

10. The method of claim 1, further comprising counting the number of pause commands.

11. The method of claim 10, wherein determining the recovery time instant comprises determining the recovery time instant as the second time instant in response to the number of pause commands being equal to or greater than a reference count.

12. The method of claim 11, wherein the first programming operation includes sequentially applying a plurality of stepwise increasing supply voltages including a reference supply voltage; and is also provided with

Determining the restoration time further comprises:

in response to the number of pause commands being less than the reference count and the pause commands being received before the reference supply voltage is applied, determining the recovery time as the first time, and

in response to the number of pause commands being less than the reference count and the pause commands being received after the reference supply voltage is applied, the restoration time is determined to be the second time.

13. The method of claim 1, further comprising outputting a ready signal after the restoring is completed.

14. A method performed by a non-volatile memory device, the method comprising:

Increasing a voltage level of a selected word line corresponding to a program command by sequentially applying a plurality of stepwise increased supply voltages to the selected word line;

receiving a pause command for an emergency read operation during increasing a voltage level of the selected word line;

determining a recovery mode based on the pause command and at least one of a pause time count, which is an amount of time between a first time at which a voltage level of a selected word line begins to increase, and a pause command number, which is a number of pause commands received while the voltage level of the selected word line is increased, and the pause command;

performing restoration according to the restoration mode; and

the emergency read operation is performed in response to a read command,

wherein the restore mode is a cancel mode in which the restore is performed while receiving the pause command, or a loop mode in which the restore is performed after increasing the voltage level of the selected word line to a target voltage.

15. The method of claim 14, wherein determining the recovery pattern is based on determining the recovery pattern based on:

the pause command and the at least one of pause time count and pause command number, and

a determination of whether the pause command is received before a reference supply voltage included in the plurality of stepwise increased supply voltages is applied.

16. The method of claim 14, further comprising:

the number of pause commands is counted and,

wherein determining the restoration pattern further comprises,

in response to determining the recovery mode as the cycling mode,

the number of pause commands is equal to or greater than a reference count, or

The number of pause commands is smaller than the reference count and the pause commands are received after the reference supply voltages included in the plurality of stepwise increased supply voltages are applied, and

in response to the number of pause commands being less than the reference count and the pause commands being received before the reference supply voltage is applied, the recovery mode is determined to be the cancel mode.

17. A non-volatile memory device, comprising:

at least one processor configured to execute computer-readable instructions in a non-transitory computer-readable storage, such that:

In response to a program command, applying a program voltage to a selected word line to increase a voltage level of the selected word line to perform a program operation,

during the programming operation, in response to receiving a pause command for an emergency reading operation, applying a reset voltage to the selected word line according to a reset mode, and

determining a recovery mode based on the pause command and at least one of a pause time count, which is an amount of time between a first time at which a voltage level of the selected word line begins to increase, and a second time at which the pause command is received, and the pause command number, which is a number of pause commands received while the program operation is performed,

wherein the recovery mode is a cancel mode in which the recovery voltage is applied before a first program loop corresponding to the program command is completed, or a loop mode in which the recovery voltage is applied after the first program loop is completed.

18. The non-volatile memory device of claim 17, wherein the at least one processor is configured to determine the resume mode based on the pause command and the number of pause commands.

19. The non-volatile memory device of claim 17, wherein the at least one processor is further configured to:

sequentially applying a plurality of increased programming voltages to the selected word line; and

the restoration mode is determined based on the following,

the method further includes determining whether the pause command is received before applying a reference supply voltage included in a plurality of stepwise increased supply voltages to the selected word line.

20. The non-volatile memory device of claim 17, wherein the at least one processor is further configured to:

determining the number of pause commands;

sequentially applying a plurality of increased programming voltages to the selected word line;

in response to determining the recovery mode as the cycling mode,

the number of pause commands is equal to or greater than a reference count, or

The pause command number is smaller than the reference count and is received after a reference supply voltage included in a plurality of stepwise increased supply voltages is applied to the selected word line; and