CN109408873B - Multi-dimensional array signal control method and device and computer readable storage medium - Google Patents
Multi-dimensional array signal control method and device and computer readable storage medium Download PDFInfo
- Publication number
- CN109408873B CN109408873B CN201811073316.8A CN201811073316A CN109408873B CN 109408873 B CN109408873 B CN 109408873B CN 201811073316 A CN201811073316 A CN 201811073316A CN 109408873 B CN109408873 B CN 109408873B
- Authority
- CN
- China
- Prior art keywords
- array signal
- node
- signal
- multidimensional array
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The invention discloses a multidimensional array signal control method, a multidimensional array signal control device and a computer readable storage medium, wherein the method comprises the steps of establishing an RTL netlist; the RTL netlist comprises a multi-dimensional array signal and associated information of the multi-dimensional array signal; establishing an RAM corresponding to the multidimensional array signal according to the associated information of the multidimensional array signal; the invention also discloses a device and a computer readable storage medium, wherein the RAM corresponding to the multidimensional array signal is established, so that the multidimensional array signal is not required to be subjected to dimension reduction processing, and the established RAM is mapped onto the FPGA, thereby fully utilizing the macro-unit RAM on the FPGA, saving logic resources and improving the layout wiring and routing rate.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and more particularly, to a method and an apparatus for controlling signals in a multidimensional array, and a computer-readable storage medium.
Background
In recent years, field Programmable Gate Arrays (FPGAs) have been significantly improved in speed, capacity and functionality, so that they are gradually replacing Application Specific Integrated Circuits (ASICs) in many application fields, and the application and wide popularization of FPGAs bring great flexibility to the design of digital systems; a Random Access Memory (RAM) is a data space for storing random variables during program operation, and most of the FPGAs currently have embedded Block RAMs (Block RAMs); hardware Description Language (HDL) is a Language for describing the structure and behavior of digital system Hardware in text form, and can be used to represent logic circuit diagrams, logic expressions, and logic functions performed by digital logic systems.
Logic synthesis tools map an HDL code at RTL (Register Transfer Level) Level to a netlist at logic gate Level or a macro cell such as RAM, and usually, a one-dimensional array signal in HDL is identified and mapped to RAM in FPGA. While the multidimensional array signal is processed differently, some tools reduce the multidimensional array signal into one dimension and then map the one dimension onto a plurality of RAMs, but a decoder (decoder) and a data selector (MUX) are additionally generated, so that a large amount of Lookup Table (LUT) logic resources are occupied; some tools reduce the dimension completely, and each signal in the array is mapped to a D-type Flip-Flop (DFF) in the FPGA, which consumes a large amount of look-up table and Flip-Flop logic resources.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method and an apparatus for controlling multidimensional array signals, and a computer-readable storage medium, in order to solve the technical problem that multidimensional array signals occupy a large amount of logic resources due to the fact that multidimensional array signals are mapped to an FPGA after being subjected to dimension reduction.
In order to solve the above technical problem, the present invention provides a multidimensional array signal control method, including:
establishing an RTL netlist; the RTL netlist comprises a multi-dimensional array signal and associated information of the multi-dimensional array signal;
creating an RAM corresponding to the multidimensional array signal according to the associated information of the multidimensional array signal;
the RAM is mapped onto the FPGA device.
Optionally, the establishing the RTL netlist includes:
reading in a preset design file, and establishing an RTL netlist according to the preset design file;
the associated information of the multidimensional array signal comprises at least one of a multidimensional array signal writing node connected with the multidimensional array signal and a multidimensional array signal reading node connected with the multidimensional array signal.
Optionally, the multidimensional array signal writing node includes: presetting a first selection signal, a data input signal and a clock signal in a design file; the multi-dimensional array signal reading node comprises a second selection signal and a data output signal in a preset design file.
Optionally, creating the RAM corresponding to the multidimensional array signal according to the correlation information of the multidimensional array signal includes:
traversing the RTL netlist, and determining each multi-dimensional array signal in the RTL netlist;
and creating a RAM corresponding to each multi-dimensional array signal one by one according to each relevant information corresponding to each multi-dimensional array signal.
Optionally, creating, according to each piece of association information corresponding to each multi-dimensional array signal, a RAM in one-to-one correspondence with each multi-dimensional array signal includes:
determining each multidimensional array signal writing node, and creating a writing port of each RAM node corresponding to each multidimensional array signal writing node;
and/or the presence of a gas in the gas,
and determining each multidimensional array signal reading node, and creating a reading port of each RAM node corresponding to each multidimensional array signal reading node.
Optionally, determining a certain multidimensional array signal writing node, and creating a writing port of the RAM node corresponding to the certain multidimensional array signal writing node includes:
taking a first selection signal of a certain multidimensional array signal writing node as an address signal of a writing port of an RAM node;
taking a data input signal of a certain multidimensional array signal writing node as a data input signal of a RAM node writing port;
and taking a clock signal of a certain multidimensional array signal writing node as a clock signal of a RAM node writing port.
Optionally, determining a certain multidimensional array signal read node, and creating a read port of the RAM node corresponding to the certain multidimensional array signal read node includes:
taking a second selection signal level of a certain multidimensional array signal reading node as an address signal of a read port of an RAM node;
and taking the data output signal of a certain multidimensional array signal reading node as the data output signal of the RAM node reading port.
Optionally, after creating the RAM corresponding to the multidimensional array signal, before mapping the RAM onto the FPGA device, the method includes:
and setting a read-write mode of the RAM according to the connection relation between the multidimensional array signal write node and the multidimensional array signal read node.
Furthermore, the invention also provides a device, which comprises a processor, a memory and a communication bus;
the communication bus is used for realizing connection communication between the processor and the memory;
the processor is configured to execute one or more programs stored in the memory to implement the steps of the multi-dimensional array signal control method as described above.
Further, the present invention also provides a computer-readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the steps of the multi-dimensional array signal control method as described above.
Advantageous effects
The invention provides a multidimensional array control method, a multidimensional array control device and a computer readable storage medium, aiming at the problem that multidimensional array signal processing occupies a large amount of resources by mapping to an FPGA after carrying out dimension reduction processing on multidimensional array signals in the prior art; the RTL netlist comprises a multi-dimensional array signal and associated information of the multi-dimensional array signal; establishing an RAM corresponding to the multidimensional array signal according to the associated information of the multidimensional array signal; the RAM is mapped to the FPGA device, namely the multi-dimensional array signal is mapped to the FPGA without dimension reduction processing by establishing the corresponding RAM for the multi-dimensional array signal, and the established RAM is mapped to the FPGA, so that macro-unit RAM on the FPGA is fully utilized, logic resources are saved, and the layout wiring and routing rate is improved.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a basic flowchart of a multi-dimensional array signal control method according to a first embodiment of the present invention;
FIG. 2 is a flowchart of a multi-dimensional array signal control method according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of an HDL file provided in accordance with a second embodiment of the present invention;
FIG. 4 is a diagram illustrating a multidimensional array signal being identified and mapped to a single RAM according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of an apparatus according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example one
In order to solve the problem that the multidimensional array signal processing occupies a large amount of logic resources due to the fact that the multidimensional array signal is mapped into an FPGA after being subjected to dimension reduction processing in the prior art, this embodiment provides a multidimensional array signal control method, as shown in fig. 1, fig. 1 is a basic flow chart of the multidimensional array signal control method provided by this embodiment, and the multidimensional array signal control method includes:
and S101, establishing an RTL netlist.
In this embodiment, the establishing an RTL netlist (netlist) specifically includes: reading in a preset design file, and establishing an RTL netlist according to the preset design file; the default design file includes, but is not limited to, an HDL file, and in some embodiments, the default design file may also be a Very-High-Speed-Integrated Circuit Hardware description language (VHDL). In this embodiment, codes in the preset design file may be converted into an RTL netlist according to a synthesis tool, where the RTL netlist includes information in the preset design file, for example, the RTL netlist includes a multidimensional array signal and associated information of the multidimensional array signal, it can be understood that the array information refers to a plurality of signal sets arranged (arrayed) according to a certain rule, and the multidimensional array signal is an array signal including multiple dimensions, for example, a two-dimensional array signal includes a high-dimensional depth and a low-dimensional depth; the correlation information of the multidimensional array signal comprises at least one of a multidimensional array signal writing node connected with the multidimensional array signal and a multidimensional array signal reading node connected with the multidimensional array signal; it can be understood that, in this embodiment, the number of the multidimensional array signals is read from a preset design file, and the multidimensional array signal writing node and the multidimensional array signal reading node are established according to the multidimensional array signals, and certainly, the relationship between the multidimensional array signal writing node, the multidimensional array signal reading node, and the multidimensional array signals is also established according to the preset design file, and certainly, according to the difference of the preset design file, the relationship between the multidimensional array signals and the multidimensional array signal writing node may be a one-to-one correspondence relationship or a one-to-many relationship, and the relationship between the multidimensional array signals and the multidimensional array signal reading node may also be a one-to-many correspondence relationship or a one-to-many relationship in the same manner.
It should be understood that the multidimensional array signal writing node includes a first selection signal, a data input signal and a clock signal in a preset design file; of course the first selection signal may comprise a plurality of sub-selection signals; the multidimensional array signal reading node comprises a second selection signal and a data output signal in a preset design file; of course, the first selection signal and the second selection signal may be the same or different in this embodiment; that is, the signals included in the write node and the read node of the multidimensional array signal in this embodiment are obtained according to a preset design file.
And S102, creating a RAM corresponding to the multi-dimensional array signal according to the correlation information of the multi-dimensional array signal.
In the embodiment, after the RTL netlist is established, a corresponding RAM is established according to the multi-dimensional array signals; specifically, the RTL netlist is traversed first, each multi-dimensional array signal in the RTL netlist is determined, and then the RAM corresponding to each multi-dimensional array signal is created according to each piece of association information corresponding to each multi-dimensional array signal. Wherein the associated information of the multidimensional array signal comprises a multidimensional array signal write node and/or a multidimensional array signal read node, creating a one-to-one correspondence RAM to the multidimensional array signal comprises: determining each multidimensional array signal writing node, and creating a writing port of each RAM node corresponding to each multidimensional array signal writing node; and/or determining each multidimensional array signal reading node, and creating a reading port of each RAM node corresponding to each multidimensional array signal reading node. Of course, when the associated information of the multidimensional array signal includes a multidimensional array signal read node and a multidimensional array signal write node, the created RAM node includes a write port and a read port.
For ease of understanding, the present embodiment is described with a multi-dimensional array signal as an example: determining the multi-dimensional array signal, the write node and the read node of the multi-dimensional array signal of the RTL netlist; creating a write port of the RAM node corresponding to the multidimensional array signal write node, and creating a read port of the RAM node corresponding to the multidimensional array signal read node; the write node of the multidimensional array signal comprises a first selection signal, a data input signal and clock information, so that the first selection signal of the write node of the multidimensional array signal is used as an address signal of a write port of the RAM node; taking the data input signal of the multidimensional array signal writing node as the data input signal of a RAM node writing port; taking a clock signal of a multidimensional array signal writing node as a clock signal of a RAM node writing port; when the first selection signal of the write node of the multidimensional array signal comprises a plurality of sub-selection signals, the plurality of sub-selection signals are cascaded into one signal to be used as an address signal of a read port of the RAM node; similarly, since the read node of the multidimensional array signal comprises the second selection signal and the data output signal, the second selection signal of the read node of the multidimensional array signal is used as an address signal of the read port of the RAM node; and taking the data output signal of the multidimensional array signal reading node as the data output signal of a RAM node reading port.
It should be noted that, in this embodiment, the RAM includes a read mode and a write mode, and after the corresponding RAM is created according to the multidimensional array signal, the read-write mode of the RAM may also be set according to the connection relationship between the multidimensional array signal write node and the multidimensional array signal read node, which may be the read mode when the RAM is set. For example, when the single fan-out of a certain multidimensional array signal reading node is a DFF, the DFF is sucked into the RAM, and a clock signal of the DFF is used as a clock signal of a reading port of the RAM node; the DFF and the RAM node are synthesized into one node if the DFF is connected with the lower level of the multi-dimensional array signal reading node; because the DFF has clock signals, after the DFF and the RAM are combined into one node, the clock signals of the DFF are used as clock signals of a read port of the RAM node, and the RAM is used as synchronous clock signals; of course, when the multidimensional array signal is not connected with the DFF, the RAM is asynchronous clock signal. Certainly, in some embodiments, when the address signals and the clock signals of the read port and the write port of the RAM node are the same, the read port and the write port of the RAM node may be combined into one read-write port, and then the read-write port may implement a read-write mode.
And S103, mapping the RAM to the FPGA device.
It should be understood that, in this embodiment, the multidimensional array signal may be one or multiple according to different preset design files, when there are multiple multidimensional array signals, there are multiple RAMs also created, and at this time, the multiple RAMs are respectively mapped onto the FPGA device; for example, when 2 RAMs 1 exist in the FPGA and 4 RAMs 2 are created according to the multidimensional array signal, 2 RAMs 2 may be first mapped into the RAMs 1 in the FPGA, respectively, and after the mapping is completed, the remaining 2 RAMs 2 are mapped into the RAMs 1 existing in the FPGA.
Certainly, in some embodiments, when the number of the multidimensional array signals is the same as the number of the RAMs in the FPGA, the RAM does not need to be created, and the first selection signal, the data input signal, and the clock signal of the multidimensional array write node can be directly used as an address signal, a data input signal, and a clock signal of the RAM write port in the FPGA, respectively; and taking the second selection signal and the data output signal of the multi-dimensional array reading node as an address signal and a data output signal of a RAM reading port in the FPGA.
In the multidimensional array signal control method provided by this embodiment, an existing dimension reduction method is not adopted, a corresponding RAM is created for multidimensional array signals in a preset design file, and a selection signal, a data input signal, and a clock signal of the multidimensional array signals are respectively used as an address signal, a data input signal, and a clock signal of a RAM write port; the selection signal and the data output signal of the multidimensional array reading node are used as the address signal and the data output signal of the RAM reading port, so that the multidimensional array signal is directly identified as a single RAM, the RAM is mapped into the FPGA, macro units in the FPGA can be fully utilized, logic resources such as LUT (look-up table) and DFF (distributed feedback function) are not occupied, and the effects of saving the logic resources, improving the layout wiring and the wiring rate and the like are achieved.
Example two
For better understanding of the present invention, this embodiment describes a multidimensional array signal control method with a more specific example, as shown in fig. 2, and fig. 2 is a detailed flowchart of a multidimensional array signal control method provided by a second embodiment of the present invention; the control method of the multi-dimensional array signal comprises the following steps:
s201, reading in a preset HDL design file, and modeling into an RTL netlist according to the preset HDL design file.
The preset HDL design file in this embodiment is shown in fig. 3, where mem is a two-dimensional array signal, where the high-dimensional depth is 256, the low-dimensional depth is 128, and each member signal bit width is 8; and modeling the RTL netlist according to a preset HDL design file, wherein the RTL netlist comprises a two-dimensional array signal node with a high-dimensional depth of 256 and a low-dimensional depth of 128, the RTL netlist further comprises a read node and a write node which are connected with a multi-dimensional array signal, and the multi-dimensional array signal in the embodiment comprises a multi-dimensional array signal read node and a multi-dimensional array signal write node.
S202, traversing the RTL netlist in a topological sequence, determining the multi-dimensional array signals, and creating RAM nodes corresponding to the multi-dimensional array signals.
Since only one multidimensional array signal is in the RTL netlist in this embodiment, individual RAM nodes are created.
S203, determining multidimensional array signal write nodes connected with the multidimensional array signals, and creating a write port of the RAM node.
In this embodiment, a write port is created on the RAM node according to the multidimensional array signal write node, specifically, as can be seen from fig. 1, the two-dimensional array signal write node includes selection signals s0 and s1, a data input signal d, and a clock signal clk; then, the selection signals s0 and s1 are cascaded into a signal { s0, s1} which is used as an address signal of a write port of the RAM node; taking a data input signal d of a multidimensional array signal writing node as a data input signal of a RAM node writing port; writing a clock signal clk of a multidimensional array signal writing node as a clock signal of a writing port of the RAM node; as shown in fig. 4, fig. 4 is a schematic diagram of multi-dimensional array signal identification and mapping to a single RAM of the present embodiment.
S204, determining the multi-dimensional array signal reading nodes connected with the multi-dimensional array signals, and creating a reading port of the RAM node.
As can be seen from fig. 1, the two-dimensional array signal reading node includes selection signals s0 and s1 and a data input signal out; cascading selection signals s0 and s1 of the two-dimensional array signal reading node into a signal { s0, s1} to serve as an address signal of a reading port of the RAM node; taking the data output signal out of the multidimensional array signal reading node as a data output signal of a reading port of the RAM node; since the address signals and clock signals of the read port and write port of the RAM node in this embodiment are the same, the RAM in this embodiment includes one read/write port, as shown in fig. 4.
It is understood that, in this embodiment, the step in S203 may be executed first, and then the step in S204 may be executed; or the step in S204 may be executed first, and then the step in S203 may be executed; the steps in S203 and S204 may be performed simultaneously.
S205, setting a read-write mode of the RAM according to the connection relation between the multidimensional array signal writing node and the multidimensional array signal reading node.
In this embodiment, the read mode when writing to the RAM is specifically set to read priority. Firstly, judging whether the lower-level connection of the multi-dimensional array signal reading node is a DFF (distributed feed function), if so, synthesizing the DFF and the RAM node into a node; because the DFF has clock signals, after the DFF is synthesized into one node, the clock signals of the DFF are used as clock signals of a read port of the RAM node, and the read mode when the RAM is written is read priority.
And S206, mapping the created RAM to the FPGA device.
In order to better understand the invention, the embodiment describes the multidimensional array signal by a specific example, when an HDL design file is read in, a model is created as an RTL netlist, the RTL netlist is traversed by a topological order, multidimensional array signal write nodes are determined, and write ports of corresponding RAM nodes are created; compared with the existing dimensionality reduction method, the multidimensional array signal control method does not occupy logic resources such as LUT (look-up table) and DFF (distributed feedback function), thereby achieving the effects of saving the logic resources, improving the layout wiring and the wiring rate and the like.
EXAMPLE III
The present embodiment further provides an apparatus, as shown in fig. 4, which includes a processor 401, a memory 402, and a communication bus 403, where:
the communication bus 403 is used for realizing connection communication between the processor 401 and the memory 402;
processor 401 is configured to execute one or more programs stored in memory 402 to implement the steps of:
establishing an RTL netlist; the RTL netlist comprises a multi-dimensional array signal and associated information of the multi-dimensional array signal;
creating an RAM corresponding to the multidimensional array signal according to the associated information of the multidimensional array signal;
the RAM is mapped onto the FPGA device.
In this embodiment, the establishing an RTL netlist includes reading in a preset design file, and establishing an RTL netlist according to the preset design file; the associated information of the multidimensional array signal comprises at least one of a multidimensional array signal writing node connected with the multidimensional array signal and a multidimensional array signal reading node connected with the multidimensional array signal; the multidimensional array signal writing node includes: presetting a first selection signal, a data input signal and a clock signal in a design file; the multi-dimensional array signal reading node comprises a second selection signal and a data output signal in a preset design file.
It is to be noted that, according to the correlation information of the multidimensional array signal, the creating of the RAM corresponding to the multidimensional array signal of the present embodiment includes: traversing the RTL netlist, and determining each multi-dimensional array signal in the RTL netlist; and creating a RAM corresponding to each multi-dimensional array signal one by one according to each associated information corresponding to each multi-dimensional array signal. Specifically, each multidimensional array signal writing node is determined, and a writing port of each RAM node corresponding to each multidimensional array signal writing node is established; and/or determining each multidimensional array signal reading node, and creating a reading port of each RAM node corresponding to each multidimensional array signal reading node. Determining a certain multidimensional array signal writing node, and creating a writing port of the RAM node corresponding to the certain multidimensional array signal writing node comprises the following steps: taking a first selection signal of a certain multidimensional array signal writing node as an address signal of a RAM node writing port; taking a data input signal of a certain multidimensional array signal writing node as a data input signal of a RAM node writing port; and taking a clock signal of a certain multidimensional array signal writing node as a clock signal of a RAM node writing port. Wherein, determining a certain multidimensional array signal reading node, and establishing a reading port of the RAM node corresponding to the certain multidimensional array signal reading node comprises: taking a second selection signal level of a certain multidimensional array signal reading node as an address signal of a read port of an RAM node; and taking the data output signal of a certain multidimensional array signal reading node as the data output signal of a RAM node reading port.
Of course, the processor 401 in this embodiment may also set a read-write mode of the RAM according to a connection relationship between the multidimensional array signal write node and the multidimensional array signal read node after creating the RAM corresponding to the multidimensional array signal and before mapping the RAM onto the FPGA device.
It is to be noted that, in order to avoid redundant description, all examples of the first embodiment, the second embodiment, and the third embodiment are not fully described in the present embodiment, and it should be clear that all examples of the first embodiment, the second embodiment, and the third embodiment are applicable to the present embodiment.
The present embodiment also provides a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the steps of the multidimensional array signal control method according to the first embodiment and/or the second embodiment.
The invention provides a device and a computer readable storage medium, which are used for realizing a multi-dimensional array control method in each embodiment; the RTL netlist comprises a multi-dimensional array signal and associated information of the multi-dimensional array signal; establishing an RAM corresponding to the multidimensional array signal according to the associated information of the multidimensional array signal; according to the multi-dimensional array signal control method provided by the embodiment, the multi-dimensional array signals do not need to be subjected to dimension reduction processing by establishing the corresponding RAM for the multi-dimensional array signals, and then the established RAM is mapped onto the FPGA, so that the macro-unit RAM on the FPGA is fully utilized, logic resources are saved, and the layout wiring and routing rate is improved.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A multi-dimensional array signal control method, comprising:
establishing an RTL netlist; the RTL netlist comprises a multi-dimensional array signal and associated information of the multi-dimensional array signal;
creating a RAM corresponding to the multidimensional array signal according to the associated information of the multidimensional array signal;
setting a read-write mode of the RAM according to the connection relation between the multidimensional array signal writing node and the multidimensional array signal reading node;
and mapping the RAM to the FPGA device.
2. The multi-dimensional array signal control method of claim 1, wherein the building an RTL netlist comprises:
reading in a preset design file, and establishing an RTL netlist according to the preset design file;
the associated information of the multidimensional array signal comprises at least one of a multidimensional array signal writing node connected with the multidimensional array signal and a multidimensional array signal reading node connected with the multidimensional array signal.
3. A method for controlling a multidimensional array signal as recited in claim 2, wherein the multidimensional array signal write node comprises: a first selection signal, a data input signal and a clock signal in the preset design file; the multidimensional array signal reading node comprises a second selection signal and a data output signal in the preset design file.
4. The method according to any one of claims 1 to 3, wherein the creating a RAM corresponding to the multidimensional array signal based on the correlation information of the multidimensional array signal comprises:
traversing the RTL netlist to determine each multi-dimensional array signal in the RTL netlist;
and creating a RAM corresponding to each multi-dimensional array signal one by one according to each associated information corresponding to each multi-dimensional array signal.
5. The method of claim 4, wherein the creating a one-to-one RAM for each of the multi-dimensional array signals based on each of the association information corresponding to each of the multi-dimensional array signals comprises:
determining each multidimensional array signal writing node, and creating a writing port of each RAM node corresponding to each multidimensional array signal writing node;
and/or the presence of a gas in the gas,
and determining each multidimensional array signal reading node, and creating a reading port of each RAM node corresponding to each multidimensional array signal reading node.
6. The multidimensional array signal control method of claim 5, wherein determining a certain multidimensional array signal write node, and creating a write port of a RAM node corresponding to the certain multidimensional array signal write node comprises:
taking the first selection signal of the certain multidimensional array signal writing node as an address signal of a writing port of the RAM node;
taking the data input signal of the certain multidimensional array signal writing node as the data input signal of the RAM node writing port;
and taking the clock signal of the certain multidimensional array signal writing node as the clock signal of the RAM node writing port.
7. The multidimensional array signal control method of claim 5, wherein determining a certain multidimensional array signal read node, and creating a read port of the RAM node corresponding to the certain multidimensional array signal read node comprises:
taking the second selection signal level of the certain multidimensional array signal reading node as an address signal of the RAM node reading port;
and taking the data output signal of the certain multidimensional array signal reading node as the data output signal of the RAM node reading port.
8. An apparatus comprising a processor, a memory, and a communication bus;
the communication bus is used for realizing connection communication between the processor and the memory;
the processor is configured to execute one or more programs stored in the memory to implement the steps of the multi-dimensional array signal control method according to any one of claims 1 to 7.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium stores one or more programs which are executable by one or more processors to implement the steps of the multi-dimensional array signal control method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811073316.8A CN109408873B (en) | 2018-09-14 | 2018-09-14 | Multi-dimensional array signal control method and device and computer readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811073316.8A CN109408873B (en) | 2018-09-14 | 2018-09-14 | Multi-dimensional array signal control method and device and computer readable storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109408873A CN109408873A (en) | 2019-03-01 |
| CN109408873B true CN109408873B (en) | 2023-03-24 |
Family
ID=65464938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811073316.8A Active CN109408873B (en) | 2018-09-14 | 2018-09-14 | Multi-dimensional array signal control method and device and computer readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109408873B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112949235B (en) * | 2021-04-16 | 2022-07-12 | 山东高云半导体科技有限公司 | Configuration method and device of electronic equipment, processor and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541850A (en) * | 1994-05-17 | 1996-07-30 | Vlsi Technology, Inc. | Method and apparatus for forming an integrated circuit including a memory structure |
| US6334169B1 (en) * | 1998-09-30 | 2001-12-25 | International Business Machines Corporation | System and method for improved bitwrite capability in a field programmable memory array |
| US7251186B1 (en) * | 2004-06-07 | 2007-07-31 | Virage Logic Corporation | Multi-port memory utilizing an array of single-port memory cells |
| CN104754249A (en) * | 2013-12-30 | 2015-07-01 | 中国科学院声学研究所 | Signal processing system for underwater imaging sonar |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8566764B2 (en) * | 2010-04-30 | 2013-10-22 | International Business Machines Corporation | Enhanced analysis of array-based netlists via phase abstraction |
-
2018
- 2018-09-14 CN CN201811073316.8A patent/CN109408873B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541850A (en) * | 1994-05-17 | 1996-07-30 | Vlsi Technology, Inc. | Method and apparatus for forming an integrated circuit including a memory structure |
| US6334169B1 (en) * | 1998-09-30 | 2001-12-25 | International Business Machines Corporation | System and method for improved bitwrite capability in a field programmable memory array |
| US7251186B1 (en) * | 2004-06-07 | 2007-07-31 | Virage Logic Corporation | Multi-port memory utilizing an array of single-port memory cells |
| CN104754249A (en) * | 2013-12-30 | 2015-07-01 | 中国科学院声学研究所 | Signal processing system for underwater imaging sonar |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109408873A (en) | 2019-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104407809A (en) | Multi-channel FIFO (First In First Out) buffer and control method thereof | |
| EP3432157B1 (en) | Data table joining mode processing method and apparatus | |
| CN105094707A (en) | Method and device for storing and reading data | |
| CN111079917A (en) | Tensor data block access method and device | |
| CN105354315A (en) | Region division method in distributed database, Region node and system | |
| CN114925647A (en) | Gate-level netlist migration method, machine-readable medium and integrated circuit design system | |
| CN109408873B (en) | Multi-dimensional array signal control method and device and computer readable storage medium | |
| CN104573112A (en) | Page query method and data processing node for OLTP cluster database | |
| CN104598161A (en) | Data reading and writing method and device and data storage structure | |
| US8954838B2 (en) | Presenting data in a tabular format | |
| JP2022508028A (en) | Data read / write methods and systems, storage media and terminals in 3D image processing | |
| US5848263A (en) | File conversion method and apparatus for LSI design data | |
| US7734456B2 (en) | Method and apparatus for priority based data processing | |
| CN106250321A (en) | The data processing method of 2R1W memorizer and data handling system | |
| CN109697234B (en) | Multi-attribute information query method, device, server and medium for entity | |
| US9965581B1 (en) | Fanout optimization to facilitate timing improvement in circuit designs | |
| CN105045767B (en) | A kind of method of immediate access and reading power system sparse matrix data | |
| US20170344504A1 (en) | Method for accessing a number of slave devices with registers by a master device over a network | |
| CN111090397A (en) | Data deduplication method, system, equipment and computer readable storage medium | |
| US20240036863A1 (en) | Vector reading and writing method, vector register system, device, and medium | |
| CN114327660B (en) | Initialization method of external memory based on FPGA | |
| CN110085284B (en) | SSD (solid State disk) -oriented gene comparison method and system | |
| JP7062793B2 (en) | Circuit wiring storage method, FPGA system and storage medium | |
| US11100267B1 (en) | Multi dimensional memory compression using bytewide write enable | |
| CN109446127B (en) | Physical BRAM matching method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |