CN109446127B - Physical BRAM matching method - Google Patents

Abstract

The application relates to the field of integrated circuits and discloses a matching method of a physical BRAM port. The method is used for carrying out port matching optimization on the logic RAM with X read ports and Y write ports under the condition that the physical BRAM is used and other logic circuits are not added, so that FPGA resources are effectively distributed to an optimization result, the performance of an integrated circuit is improved, and the influence on the time sequence of the circuit is minimum. Meanwhile, in the invention, the situation of physical BRAM of N ports is considered, the dependence on the number of BRAM ports of a specific FPGA device and other constraint conditions is reduced, and the method is more common.

Description

Physical BRAM matching method

Technical Field

The present application relates to the field of integrated circuits, and in particular, to a physical BRAM matching method.

Background

In an FPGA, four input look-up tables (LUTs) of a CLB can be configured as a 16x1bit synchronous RAM, and 2 LUTs slices of the same cell can be configured as a 16x2bit or 32x1bit synchronous RAM, or a 16x1bit dual port synchronous RAM. But the capacity is low and cannot meet the requirements of users. Each BRAM has 4096 memory cells, each port has independent control signals, so that each port of the BRAM can be independently configured as a read-write, read-only or write-only port with a specific data width, and an embedded bus width conversion function is provided. The BRAMs are typically arranged in columns of 5, with special routing resources on the BRAM columns so that the block RAMs can be cascaded with minimal routing delay. This only sacrifices less timing than using ordinary routing channels, thereby achieving a wider or deeper RAM structure.

However, once the BRAM resources are tight, or all BRAMs are used up, the performance of the integrated circuit is generally degraded, even if the channel (route) is not available. The BRAM and the distributed RAM are flexibly and reasonably applied, so that FPGA resources can be effectively utilized, and the system performance is improved.

Disclosure of Invention

The application aims to provide a physical BRAM matching method, which solves the problem that under the condition that only a physical BRAM is used and other logic circuits are not added, a logic RAM is optimized, so that the influence of an optimization result on the time sequence of a final integrated circuit is minimum, and the performance of the integrated circuit is improved to a great extent.

In order to solve the above problem, the present application discloses a matching method for a physical BRAM port, which includes the following steps:

step 101: acquiring any logic RAM in an RTL circuit, and putting all read ports and write ports in the logic RAM into a queue;

step 102: judging whether the logic RAM can be realized by matching one physical BRAM according to the preset physical BRAM constraint condition, simultaneously recording the judgment result, if so, executing the step 103, otherwise, realizing the logic RAM by using an FPGA general logic unit and executing the step 108;

step 103: extracting a read port or a write port as a first port from the queue;

step 104: mapping the first port to a port of the physical BRAM;

step 105: judging whether a second port which can be merged to the first port exists in the queue or not according to the physical BRAM constraint condition, if so, executing a step 106, otherwise, executing a step 107;

step 106: extracting the second port from the queue and merging the second port to the first port;

step 107: judging whether the queue has residual read ports or write ports, if so, executing step 103, otherwise, executing step 108;

step 108: and replacing the original logic RAM by the implementation of the physical BRAM or the implementation of the general logic unit.

In a preferred embodiment, the method further comprises a step 109, where the step 109 includes: checking whether the logic RAM which can be optimized still exists in the circuit, if so, executing the step 101, otherwise, ending the execution.

In a preferred embodiment, the constraint includes: the same port can simultaneously perform read operation and write operation through the same address.

In a preferred embodiment, the physical BRAM has N ports, wherein N is a natural number, and one port of the physical BRAM supports both read and write operations or only supports read and write operations.

In a preferred embodiment, the one logical RAM is a RAM of X write ports and Y read ports, where X and Y are natural numbers.

In a preferred embodiment, the case that the logical RAM cannot be implemented with a physical BRAM match in step 102 includes: the physical BRAM only has one port and only supports one address to read and write, but the logical RAM can be realized by different read and write addresses.

In a preferred embodiment, the step 101 comprises the following sub-steps:

acquiring any logic RAM in an RTL circuit, extracting read port and write port information in the logic RAM and recording the read port and the write port information on a corresponding read port or write port; wherein the information includes address, data and enable status;

the read port and write port are placed in the queue.

In a preferred embodiment, the step 102 is to check different constraints of the physical BRAM, and for a new physical BRAM type or a new physical BRAM constraint, the preset physical BRAM constraint in the step 102 needs to be replaced.

The application also discloses a matching system of a physical BRAM port, which comprises:

a memory for storing computer executable instructions; and the number of the first and second groups,

a processor for implementing the steps in the method as described hereinbefore when executing the computer executable instructions.

The present application also discloses a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the steps in the method as described hereinbefore.

In the embodiment of the application, whether a logic RAM can be matched and realized by a physical BRAM is judged according to a preset physical BRAM constraint condition, a read port or a write port of the logic RAM is extracted according to the judgment result, the read port or the write port is mapped to the physical BRAM port, then other read ports or write ports which can be combined to the read port or the write port and exist in a queue are judged and extracted, the read port or the write port is combined and mapped to the physical BRAM port, and finally, a new physical BRAM is used for replacing the logic RAM to realize read operation and write operation; circularly searching a new logic RAM and mapping the new logic RAM into the physical BRAM according to the steps; therefore, under the condition that only the physical BRAM is used and other logic circuits are not added, the logic RAM is optimized through reasonable matching, so that the time sequence of the final circuit is minimally influenced by the optimization result, the physical BRAM resources are reasonably distributed, and the stability of the system performance is greatly improved.

The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.

Drawings

Fig. 1 is a schematic flow chart of a physical BRAM matching method according to a first embodiment of the present application

Fig. 2 is a schematic diagram of physical BRAM port relationship in a specific example according to the first embodiment of the present application

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

Description of partial concepts:

FPGA: field Programmable Gate Array, Field Programmable logic Array. The circuit is a semi-custom circuit in the field of application-specific integrated circuits, not only overcomes the defects of a full-custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable logic device is limited.

RTL: Register-Transfer Level, Register Transfer Level. It is an abstract model of synchronous digital circuits, which is determined by the flow of digital signals between logic units such as hardware registers, memory, combinational logic devices, and buses, and by the way in which they operate logically algebraically.

RAM: random-access memory, Random-access memory. And the logic unit is used for storing data and can read and write the data through the address.

Port: port. Refers to a set of input and output signals of the RAM.

A read port: read Port. A set of input-output signals for implementing a read operation of RAM data.

Writing port: write Port. And a set of input and output signals for implementing a write operation of RAM data.

BRAM: block Random Access Memory. Mainly applied to constructing data caches, deep FIFOs and buffers, etc.

A logic RAM: the user acts as a random access memory described in the circuit, or a random access memory called directly by RTL level.

And (3) physical BRAM: a specific BRAM on the FPGA device.

A general logic unit: including LUT, registers, etc.

LUT: lookup Table. In computer science, a lookup table is a data structure that replaces a run-time computed array or an associated array with a simple query operation.

Register (Register): is a component part of the central processing unit. Registers are high-speed storage elements of limited storage capacity that may be used to temporarily store instructions, data, and addresses.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

A first embodiment of the present application relates to a physical BRAM matching method, a flow of which is shown in fig. 1, and the method includes the following steps:

step 101: acquiring any logic RAM in an RTL circuit, and putting all read ports and write ports in the logic RAM into a queue L;

step 102: judging whether the logic RAM can be realized by matching one physical BRAM according to the preset physical BRAM constraint condition, simultaneously recording the judgment result, if so, executing step 103, otherwise, realizing the logic RAM by using an FPGA general logic unit (the process is set in step 110 in the figure) and executing step 108;

step 103: extracting a read port or a write port as a first port from the queue L;

step 104: mapping the first port to a port of the physical BRAM;

step 105: judging whether a second port which can be merged to the first port exists in the queue L according to the physical BRAM constraint condition, if so, executing a step 106, otherwise, executing a step 107;

step 106: extracting the second port from the queue and merging the second port to the first port;

step 107: judging whether the queue has residual read ports or write ports, if so, executing step 103, otherwise, executing step 108;

step 108: and replacing the original logic RAM by the implementation of the physical BRAM or the implementation of the general logic unit.

Optionally, a step 109 is further included, where the step 109 includes: checking whether the logic RAM which can be optimized still exists in the circuit, if so, executing the step 101, otherwise, ending the execution.

Optionally, the second ports are read ports or write ports that can be merged with the first ports in the queue L, and the number of the second ports is not limited to 1, and may be N (N ≧ 2); if the number of second ports is N, then N fetches and merges need to be performed (step 106) until there are no more ports that can be merged, then step 107 is performed again.

Optionally, considering that the constraint conditions of the physical BRAMs are different among different devices of different FPGA manufacturers, the present application focuses the checks of different constraint conditions (including the number of ports, addresses, data, read/write, etc.) of the physical BRAMs on the step 102 for processing, and sets the checks as "preset physical BRAM constraint conditions", so as to reduce the influence on other steps in the method, and records the check results for use when performing port merging in steps 105 and 106. Other constraints include, but are not limited to, the following:

1) the same port can simultaneously carry out reading operation and writing operation through the same address,

2) the address needs register caching; and the number of the first and second groups,

other BRAM input and output constraints which influence whether the read-write ports can be combined or not;

when a new physical BRAM type or a new physical BRAM constraint needs to be supported, only corresponding adjustments need to be made in the implementation in step 102.

Optionally, the physical BRAM has N ports, where N is a natural number, and one port of the physical BRAM may be, but is not limited to: (1) simultaneously supporting read operation and write operation; (2) only read or write operations are supported.

Alternatively, the one logical RAM is a RAM of X write ports and Y read ports, where X and Y are natural numbers.

Optionally, the situation that the logical RAM in the step 102 cannot be implemented with a physical BRAM match includes but is not limited to: the physical BRAM only has one port and only supports one address to read and write, but the logical RAM can be realized by different read and write addresses.

Optionally, this step 101 comprises the following sub-steps:

step 1: acquiring any logic RAM in an RTL circuit, extracting read port and write port information in the logic RAM and recording the read port and the write port information on a corresponding read port or write port; wherein the information includes address, data and enable status;

step 2: the read port and write port are placed in the queue L.

In order to better understand the technical solution of the present application, the following description is given with reference to a specific example, in which the following settings are made:

(1) the logic RAM (recorded as RAM1) has 2 write ports and 2 read ports;

(2) the physical BRAM adopts the physical BRAM with the port number of 2 to realize ram1 (because the port number of the FPGA physical BRAM which is mainstream at present is 2);

(3) the constraint condition of the physical BRAM is set as follows: the same port may use the same address for both read and write operations.

Wherein, the read and write port information of ram1 is shown in table 1;

TABLE 1 logical RAM read and write Port information

Port(s)	Read-write type	Address	Data of	Enable the
					write_port1	Writing	addr1	din1	we1
write_port2	Writing	addr2	din2	we2
					read_port1	Reading	addr1	dout1	re1
read_port2	Reading	addr2	dout2	re2

Therefore, the present embodiment is a method for automatically matching a logical RAM having 2 read ports and 2 write ports to a physical BRAM having 2 ports, and the specific steps are as follows:

step 101, selecting a logic RAM (random access memory), such as RAM1 in the example, extracting information of a read port and a write port in RAM1, and recording the information on the corresponding read port and write port; the queue L for recording read ports and write ports is shown in table 2;

TABLE 2 read-write Port information records

write_port1＝{addr1,din1,we1}
	write_port2＝{addr2,din2,we2}
read_port1＝{addr1,dout1,re1}
	read_port2＝{addr2,dout2,re2}

Step 102, according to the constraint condition of physical BRAM, that the same port can use the same address to perform read operation and write operation, and it can be judged that the logical RAM can be implemented by using one physical BRAM, then step 103 is continuously executed;

step 103, extracting a first port write _ port1 from the read port and write port queue L, and continuing to execute step 104; at this time, the read/write ports in the queue L are shown in table 3;

TABLE 3 queue after first round fetch first write port

write_port2＝{addr2,din2,we2}
	read_port1＝{addr1,dout1,re1}
read_port2＝{addr2,dout2,re2}

Step 104, mapping a write port write _ port1 to a physical BRAM port, which is marked as port 1;

step 105, according to the physical BRAM constraint condition that the same port can use the same address to perform read operation and write operation, checking that a read port read _ port1 exists in the queue L, and merging the read port read _ port1 into a physical BRAM port 1;

step 106, extracting read _ port1 from the queue L and merging it to write _ port1 (namely, on physical BRAM port 1); at this time, the read port and the write port in the queue L are shown in table 4;

table 4 queue with optimized read/write ports in the first round

write_port2＝{addr2,din2,we2}
	read_port2＝{addr2,dout2,re2}

Step 107, checking that there are remaining read ports or write ports in the queue L, as shown in table 4; jumping to step 103;

step 103, extracting a first port write _ port2 from the read/write port queue L, and continuing to execute step 104, where the read/write ports in the queue L are shown in table 5;

TABLE 5 queue with write port taken out in the second round

read_port2＝{addr2,dout2,re2}

Step 104, mapping a write port write _ port2 to a physical BRAM port, which is marked as port 2;

step 105, checking that there is a read _ port2 in the queue L according to the physical BRAM constraint condition that "the same port can use the same address to perform read operation and write operation", and merging the read _ port2 into the write port write _ port2 (i.e. the physical BRAM port 2);

step 106, extracting a read port read _ port1 from the queue L, and merging the read port read _ port1 to a write port write _ port2 (namely, a physical BRAM port2), wherein no read/write port exists in the queue L at this time;

step 107, checking that there is no read port or write port in the queue L, and continuing to the next step

Step 108, using the implementation of the physical BRAM, replaces the original logical RAM, namely RAM 1. Connecting corresponding input and output signals at the same time, and continuing the next step; the physical BRAM is generated as shown in FIG. 2;

step 109, checking that no other optimizable logic RAM exists in the circuit;

finally, the RAM optimization process ends.

A second embodiment of the present application relates to a matching system for a physical BRAM port, including:

a memory for storing computer executable instructions; and the number of the first and second groups,

a processor for implementing the steps in the method as described hereinbefore when executing the computer executable instructions.

A third embodiment of the present application relates to a computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, implement the steps in the method as described above.

It should be noted that those skilled in the art should understand that the embodiment of the present invention also provides a computer storage medium, in which computer executable instructions are stored, and the computer executable instructions are executed by a processor to implement the method embodiments of the present invention.

In addition, the embodiment of the invention also provides a matching system of the physical BRAM port, which comprises a memory for storing computer executable instructions and a processor; the processor is configured to implement the steps of the method embodiments described above when executing the computer-executable instructions in the memory.

It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.

All documents mentioned in this application are to be considered as being incorporated in their entirety into the disclosure of this application so as to be subject to modification as necessary. Further, it is understood that various changes or modifications may be made to the present application by those skilled in the art after reading the above disclosure of the present application, and such equivalents are also within the scope of the present application as claimed.

Claims (10)

1. A matching method for a physical BRAM port is characterized by comprising the following steps:

step 101: acquiring any one logic RAM in an RTL circuit, and putting all read ports and write ports in the logic RAM into a queue;

step 102: judging whether the logic RAM can be realized by matching one physical BRAM according to a preset physical BRAM constraint condition, simultaneously recording a judgment result, if so, executing a step 103, otherwise, realizing the logic RAM by using an FPGA general logic unit and executing a step 108;

step 103: extracting a read port or a write port as a first port from the queue;

step 104: mapping the first port to one port of the physical BRAM;

step 105: judging whether a second port which can be merged to the first port exists in the queue or not according to the physical BRAM constraint condition, if so, executing a step 106, otherwise, executing a step 107;

step 106: extracting the second port from the queue and merging the second port to the first port;

step 107: judging whether the queue has residual read ports or write ports, if so, executing step 103, otherwise, executing step 108;

step 108: and replacing the original logic RAM by the implementation of the physical BRAM or the implementation of the general logic unit.

2. The matching method according to claim 1, further comprising step 109, wherein step 109 comprises: checking whether the logic RAM which can be optimized still exists in the circuit, if so, executing the step 101, otherwise, ending the execution.

3. The matching method according to claim 2, wherein the constraint condition includes: the same port can simultaneously perform read operation and write operation through the same address.

4. The matching method according to claim 3, wherein said one physical BRAM has N ports, where N is a natural number, and one port of said physical BRAM supports both read and write operations or only read or write operations.

5. The matching method according to claim 4, wherein the one logical RAM is a RAM of X write ports and Y read ports, where X and Y are natural numbers.

6. The matching method according to claim 1, wherein the case that the logical RAM cannot be implemented with a physical BRAM match in step 102 comprises: the physical BRAM only has one port and only supports one address to read and write, but the logical RAM can be realized only by different read and write addresses.

7. Matching method according to claim 1, characterized in that said step 101 comprises the following sub-steps:

acquiring any logic RAM in an RTL circuit, extracting read port and write port information in the logic RAM and recording the read port and the write port information on a corresponding read port or write port; wherein the information comprises an address, data and an enable status;

and putting the read port and the write port into the queue.

8. The matching method according to claim 1, wherein said step 102 is a check of different constraints of said physical BRAM, and said preset physical BRAM constraints in step 102 are required to be replaced for a new physical BRAM type or a new physical BRAM constraint.

9. A system for matching a physical BRAM port, comprising:

a memory for storing computer executable instructions; and the number of the first and second groups,

a processor for implementing the steps in the method of any one of claims 1 to 8 when executing the computer-executable instructions.

10. A computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the steps in the method of any one of claims 1 to 8.

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