CN109408873A - A kind of multi-dimension array signal control method, device and computer readable storage medium - Google Patents
A kind of multi-dimension array signal control method, device and computer readable storage medium Download PDFInfo
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Abstract
The invention discloses a kind of multi-dimension array signal control method, device and computer readable storage medium, this method includes establishing RTL netlist；Wherein RTL netlist includes the related information of multi-dimension array signal and multi-dimension array signal；According to the related information of multi-dimension array signal, RAM corresponding with multi-dimension array signal is created；RAM is mapped on FPGA device, solve it is existing by multi-dimension array signal carry out dimension-reduction treatment after, it is mapped in FPGA, lead to the problem of a large amount of resource is occupied to multi-dimension array signal processing, the invention also discloses a kind of device and computer readable storage mediums, RAM corresponding to multi-dimension array signal creation, so that multi-dimension array signal and do not have to carry out dimension-reduction treatment, and then the RAM of creation is mapped on FPGA, make full use of the macroelement RAM on FPGA, reach saving logical resource, improves placement-and-routing's completion rate.
Description
Technical field
The present invention relates to IC design fields, more specifically to a kind of multi-dimension array signal control method, dress
It sets and computer readable storage medium.
Background technique
In recent years, field programmable gate array (Field Programmable Gate Array, FPGA) is in speed, appearance
Amount and functional aspect are obviously improved, therefore gradually replace specific integrated circuit (application in many application fields
Specific integrated circuit, ASIC), the application of FPGA and the widely available design for digital display circuit bring pole
Big flexibility；And random access memory (random access memory, RAM) be in program is run storage with
The data space of machine variable, current most of FPGA have embedded block RAM (Block RAM)；Hardware description language
(Hardware Description Language, HDL) is the structure and row for describing digital display circuit hardware in the form of text
For language, can indicate logical circuitry, logical expression with it, also may indicate that the logic that digital logic system is completed
Function.
The HDL code of RTL (Register Transfer Level) rank is mapped to logic gate level by logic synthesis tool
Netlist or the macroelements such as RAM, in general, the one-dimensional array signal in HDL will be identified and be mapped on the RAM in FPGA.
And be not quite similar to the processing of multi-dimension array signal, its dimensionality reduction at one-dimensional, is then mapped on multiple RAM by some tools, but
It is that can additionally generate decoder (decoder) and data selector (multiplexer, MUX), so that a large amount of search will be occupied
Table (Lookup Table, LUT) logical resource；Each signal in array is mapped to by some tools by its complete dimensionality reduction
On D flip-flop (D type Flip Flop, DFF) in FPGA, a large amount of look-up table and trigger logic resource will be expended.
Summary of the invention
The technical problem to be solved in the present invention is that it is existing by multi-dimension array signal carry out dimension-reduction treatment after, be mapped to
In FPGA, cause to provide a kind of multidimensional battle array for the technical problem to a large amount of logical resource of multi-dimension array signal processing occupancy
Column signal control method, device and computer readable storage medium.
In order to solve the above technical problems, the present invention provides a kind of multi-dimension array signal control method, the multi-dimension array signal
Control method includes:
Establish RTL netlist；RTL netlist includes the related information of multi-dimension array signal and multi-dimension array signal；
According to the related information of multi-dimension array signal, RAM corresponding with multi-dimension array signal is created；
RAM is mapped on FPGA device.
Optionally, establishing RTL netlist includes:
Preset design file is read in, RTL netlist is established according to preset design file；
The related information of multi-dimension array signal include the multi-dimension array signal being connect with multi-dimension array signal write node, with it is more
The multi-dimension array signal for tieing up array signal connection reads at least one of node.
Optionally, it includes: that first selection signal, the data in preset design file input letter that multi-dimension array signal, which writes node,
Number and clock signal；It includes the second selection signal in preset design file, data output signal that multi-dimension array signal, which reads node,.
Optionally, according to the related information of multi-dimension array signal, creating RAM corresponding with multi-dimension array signal includes:
RTL netlist is traversed, determines each multi-dimension array signal in RTL netlist；
According to each related information corresponding with each multi-dimension array signal, create one-to-one with each multi-dimension array signal
RAM。
Optionally, according to each related information corresponding with each multi-dimension array signal, creation and each multi-dimension array signal are one by one
Corresponding RAM includes:
It determines that each multi-dimension array signal writes node, creates and write the corresponding each RAM node of node with each multi-dimension array signal
Write port；
And/or
It determines that each multi-dimension array signal reads node, creates each RAM node corresponding with each multi-dimension array signal reading node
Read port.
Optionally, determine that some multi-dimension array signal writes node, it is corresponding that creation with some multi-dimension array signal writes node
The write port of RAM node includes:
The first selection signal that some multi-dimension array signal is write to node, the address signal as RAM node write port；
The data input signal that some multi-dimension array signal is write to node, the data as RAM node write port input letter
Number；
The clock signal that some multi-dimension array signal is write to node, the clock signal as RAM node write port.
Optionally, determine that some multi-dimension array signal reads node, creation is corresponding with some multi-dimension array signal reading node
The read port of RAM node includes:
The second selection signal grade that some multi-dimension array signal is read to node, the address signal as RAM node read port；
The data output signal that some multi-dimension array signal is read to node, the data as RAM node read port export letter
Number.
Optionally, after creating RAM corresponding with multi-dimension array signal, include: before RAM is mapped on FPGA device
Node is write according to multi-dimension array signal and multi-dimension array signal reads the connection relationship of node, and the read-write mould of RAM is set
Formula.
Further, the present invention also provides a kind of device, device includes processor, memory and communication bus；
Communication bus is for realizing the connection communication between processor and memory；
Processor is for executing one or more program stored in memory, to realize that above-mentioned multi-dimension array such as is believed
The step of number control method.
Further, the present invention also provides a kind of computer readable storage medium, computer-readable recording medium storages
There is one or more program, one or more program can be executed by one or more processor, to realize as above-mentioned
The step of multi-dimension array signal control method.
Beneficial effect
The present invention provides a kind of multi-dimension array control method, device and computer readable storage medium, passes through for existing
It after carrying out dimension-reduction treatment to multi-dimension array signal, is mapped in FPGA, causes to occupy multi-dimension array signal processing a large amount of money
The problem of source, multi-dimension array control method of the invention is by establishing RTL netlist；Wherein RTL netlist includes multi-dimension array signal
And the related information of multi-dimension array signal；According to the related information of multi-dimension array signal, create corresponding with multi-dimension array signal
RAM；RAM is mapped on FPGA device, i.e., the present invention is by the corresponding RAM of multi-dimension array signal creation, so that multidimensional
Array signal simultaneously does not have to carry out dimension-reduction treatment, and then the RAM of creation is mapped on FPGA, makes full use of the macroelement on FPGA
RAM reaches saving logical resource, improves placement-and-routing's completion rate.
Detailed description of the invention
Present invention will be further explained below with reference to the attached drawings and examples, in attached drawing:
Fig. 1 is the multi-dimension array signal control method basic flow chart that first embodiment of the invention provides；
Fig. 2 is the multi-dimension array signal control method flow chart that second embodiment of the invention provides；
Fig. 3 is the schematic diagram for the hdl file that second embodiment of the invention provides；
Fig. 4 be second embodiment of the invention provide by multi-dimension array signal identification and be mapped to the schematic diagram of single RAM；
Fig. 5 is the structural schematic diagram for the device that third embodiment of the invention provides.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, below by specific embodiment knot
Attached drawing is closed to be described in further detail the embodiment of the present invention.It should be appreciated that specific embodiment described herein is only used to
It explains the present invention, is not intended to limit the present invention.
Embodiment one
In order to solve it is existing by multi-dimension array signal carry out dimension-reduction treatment after, be mapped in FPGA, cause to multidimensional
Array signal processing occupies a large amount of logical resource problem, and the present embodiment provides a kind of multi-dimension array signal control method, such as Fig. 1
Shown, Fig. 1 is multi-dimension array signal control method basic flow chart provided in this embodiment, the multi-dimension array signal control method
Include:
S101, RTL netlist is established.
In the present embodiment, it establishes RTL netlist (netlist) to specifically include: preset design file is read in, according to setting
Meter file establishes RTL netlist；Wherein preset design file include but is not limited to be hdl file, it is certainly pre- in some embodiments
If file can also be VHSIC hardware description language (Very-High-Speed Integrated Circuit
Hardware Descri, VHDL).It in the present embodiment, can be according to synthesis tool by the code conversion in preset design file
It include pre- in RTL netlist for describing the mutual connection relationship of circuit element in preset design file for RTL netlist
It, can be with if the information in design document, such as RTL netlist include the related information of multi-dimension array signal and multi-dimension array signal
Understand, array information refers to that several arrange the signal set of (array) according to certain rules, and multi-dimension array signal is to include
The array signal of multiple dimensions, such as two-dimensional array signal include higher-dimension depth and low-dimensional depth；Wherein multi-dimension array signal
Related information includes the multidimensional battle array that the multi-dimension array signal connecting with multi-dimension array signal is write node, connect with multi-dimension array signal
Column signal reads at least one of node；It is understood that the number of multi-dimension array signal is from setting in the present embodiment
It is read out in meter file, and multi-dimension array signal, which writes node and multi-dimension array signal reading node, to be built according to multi-dimension array signal
Vertical, certain multi-dimension array signal writes node, multi-dimension array signal reads node and the relationship of multi-dimension array signal is also according to pre-
If what design document was established, certainly according to the difference of preset design file, wherein multi-dimension array signal is write with multi-dimension array signal
The relationship of node can be one-to-one relationship, be also possible to many-one relationship, and similarly multi-dimension array signal and multi-dimension array are believed
Number read node relationship be also possible to one-to-one relationship, many-one relationship.
It should be understood that it includes the first selection signal in preset design file, data that multi-dimension array signal, which writes node,
Input signal and clock signal；Certain first selection signal may include multiple sub- selection signals；Multi-dimension array signal reads node
Including the second selection signal and data output signal in preset design file；First selection signal and the in certain the present embodiment
Two selection signals may be the same or different；Writing node and reading node for multi-dimension array signal i.e. in the present embodiment include
Signal be according to obtained in preset design file.
S102, according to the related information of multi-dimension array signal, create RAM corresponding with multi-dimension array signal.
In the present embodiment, after establishing RTL netlist, according to the corresponding RAM of multi-dimension array signal creation；Specifically, first
RTL netlist is first traversed, determines each multi-dimension array signal in RTL netlist, then according to corresponding with each multi-dimension array signal each
Related information, creation and each one-to-one RAM of multi-dimension array signal.Wherein the related information of multi-dimension array signal includes multidimensional
Array signal writes node and/or multi-dimension array signal reads node, then creates the one-to-one RAM packet with multi-dimension array signal
It includes: determining that each multi-dimension array signal writes node, create and write end with what each multi-dimension array signal write the corresponding each RAM node of node
Mouthful；And/or determine that each multi-dimension array signal reads node, create each RAM node corresponding with each multi-dimension array signal reading node
Read port.Certainly when the related information of multi-dimension array signal includes that multi-dimension array signal reading node and multi-dimension array signal write node
When, the RAM node of creation includes write port and read port.
In order to make it easy to understand, the present embodiment is illustrated by taking a multi-dimension array signal as an example: determining the RTL netlist multidimensional
Array signal and the multi-dimension array signal write node, read node；Creation writes node corresponding RAM section with the multi-dimension array signal
The write port of point creates the read port of RAM node corresponding with multi-dimension array signal reading node；Due to multi-dimension array signal
To write node include first selection signal, data input signal and clock information, therefore by the node of writing of the multi-dimension array signal
Address signal of the first selection signal as RAM node write port；Multi-dimension array signal is write to the data input signal of node, is made
For the data input signal of RAM node write port；The clock signal that multi-dimension array signal is write to node writes end as RAM node
The clock signal of mouth；It, will wherein when the first selection signal for writing node of multi-dimension array signal includes multiple sub- selection signals
Multiple sub- selection signals are cascaded into a signal, the address signal as RAM node read port；Similarly, since multi-dimension array is believed
Number reading node include the second selection signal and data output signal, then by the multi-dimension array signal read node second selection believe
Number, the address signal as RAM node read port；The data output signal that multi-dimension array signal is read to node, as RAM node
The data output signal of read port.
It is worth noting that, in the present embodiment, RAM includes reading mode and WriteMode, according to multi-dimension array signal creation
After corresponding RAM, node can also be write according to multi-dimension array signal and multi-dimension array signal reads the connection relationship of node, setting
The read-write mode of RAM can be reading mode when RAM is write in setting.Such as when some multi-dimension array signal reads single fan of node
When being out DFF, then RAM, clock signal of the clock signal of DFF as RAM node read port are sucked；I.e. multi-dimension array is believed
Number reading node junior connects DFF, then the DFF and RAM node is synthesized a node；Since DFF has clock signal, work as synthesis
After a node, clock signal of the clock signal of DFF as RAM node read port, RAM is synchronizing clock signals；Certainly
When multi-dimension array signal does not connect DFF, RAM is asynchronous clock signal at this time.Certainly in some embodiments, when RAM is saved
The address signal and clock signal of point read port and write port are all identical, RAM node read port and write port can be merged into
One reading-writing port, and then read-write mode may be implemented in the reading-writing port.
S103, RAM is mapped on FPGA device.
It should be understood that the multi-dimension array signal in the present embodiment can be one according to the difference of preset design file
It is a, be also possible to it is multiple, when there are multiple multi-dimension array signals, creation RAM be also it is multiple, multiple RAM are reflected respectively at this time
It is mapped on FPGA device；Such as when in FPGA there are when 2 RAM1, when according to the RAM2 of multi-dimension array signal creation being 4, then
First 2 RAM2 can be respectively mapped in the RAM1 in FPGA, after the completion of mapping, be mapped to by remaining 2 RAM2
There are in RAM1 in FPGA.
Certainly in some embodiments, when the number of multi-dimension array signal is identical as the number of the RAM in FPGA, then without
RAM need to be created, can directly be made first selection signal, data input signal, clock signal that multi-dimension array writes node respectively
Address signal, data input signal, clock signal for the RAM write port in FPGA；Multi-dimension array is read to the second choosing of node
Select address signal, the data output signal of signal, data output signal as the RAM read port in FPGA.
Multi-dimension array signal control method provided in this embodiment, does not use existing dimension reduction method, by preset design
The corresponding RAM of multi-dimension array signal creation in file, by the selection signal of multi-dimension array signal, data input signal, clock
Address signal, data input signal, clock signal of the signal respectively as RAM write port；Multi-dimension array is read to the selection of node
Address signal, the data output signal of signal, data output signal as RAM read port, so that multi-dimension array signal is direct
It is identified as single RAM, and then RAM is mapped in FPGA, the macroelement in FPGA can be made full use of, is not take up LUT, DFF etc.
Logical resource improves placement-and-routing's completion rate and other effects to reach saving logical resource.
Embodiment two
In order to better understand the present invention, the present embodiment controls multi-dimension array signal with a more specific example
Method is illustrated, and the control method if Fig. 2, Fig. 2 are the multi-dimension array signal that second embodiment of the invention provides refines process
Figure；The control method of the multi-dimension array signal includes:
S201, default HDL design document is read in, RTL netlist is modeled as according to default HDL design document.
Default HDL design document in the present embodiment is as shown in figure 3, wherein mem is two-dimensional array signal, and wherein higher-dimension is deep
Degree is 256, and low-dimensional depth is 128, and each member's signal bit wide is 8；It is modeled as RTL netlist according to default HDL design document,
Middle RTL netlist includes that a higher-dimension depth is 256, the two-dimensional array signal node that low-dimensional depth is 128, and RTL netlist further includes
The reading node that connect with multi-dimension array signal and node is write, and the multi-dimension array signal in the present embodiment includes a multi-dimension array
Signal reads node, and a multi-dimension array signal writes node.
S202, topological order traverse RTL netlist, determine multi-dimension array signal, are created that corresponding with multi-dimension array signal
RAM node.
By only one multi-dimension array signal in RTL netlist in this present embodiment, then RAM node one by one is created.
S203, the multi-dimension array signal for determining that multi-dimension array signal is connected write node, and be created that RAM node writes end
Mouthful.
Node is write on RAM node according to multi-dimension array signal in the present embodiment and creates write port, specifically, according to Fig. 1
It is found that it includes selection signal s0, s1, data input signal d, clock signal clk that two-dimensional array signal, which writes node,；Then selection is believed
Number s0, s1 are cascaded into a signal { s0, s1 }, the address signal as RAM node write port；Multi-dimension array signal is write into node
Data input signal d, the data input signal as RAM node write port；Multi-dimension array signal is write to the clock letter of node
Number clk, the clock signal as RAM node write port；As shown in figure 4, Fig. 4 is the multi-dimension array signal identification of this implementation and reflects
It is mapped to the schematic diagram of single RAM.
S204, it determines that the multi-dimension array signal that multi-dimension array signal is connected reads node, is created that the reading end of RAM node
Mouthful.
As can be seen from FIG. 1, it includes selection signal s0, s1, data input signal out that two-dimensional array signal, which reads node,；By two
Selection signal s0, s1 that dimension array signal reads node is cascaded into a signal { s0, s1 }, the address as RAM node read port
Signal；The data output signal out that multi-dimension array signal is read to node, the data output signal as RAM node read port；By
The address signal and clock signal of RAM node read port and write port in this present embodiment are all identical, therefore in the present embodiment
RAM include a reading-writing port, as shown in Figure 4.
It is understood that the step in S203 can be first carried out in the present embodiment, then execute the step in S204；It can also
To be the step first carried out in S204, then execute the step in S203；It can also be the step being performed simultaneously in S203, S204.
S205, the connection relationship that node and multi-dimension array signal reading node are write according to multi-dimension array signal, are arranged the reading of RAM
WriteMode.
In the present embodiment, reading mode when RAM is write in specific setting is preferential to read.First determine whether that the multi-dimension array signal is read
Whether the connection of node junior is DFF, if so, the DFF and RAM node are then synthesized a node；Since DFF has clock letter
Number, after synthesizing a node, clock signal of the clock signal of DFF as RAM node read port, when writing RAM at this time
Reading mode is to read preferentially.
S206, creation RAM is mapped on FPGA device.
In order to better understand the present invention, the present embodiment says multi-dimension array signal with a more specific example
It is bright, when reading in HDL design document, it is modeled as RTL netlist, topological order traverses RTL netlist, determines that multi-dimension array signal writes section
Point, and it is created that the write port of corresponding RAM node；It determines that multi-dimension array signal reads node, and creates corresponding RAM node
Read port, and then by multi-dimension array signal Direct Recognition at single RAM uses dimension reduction method compared to existing, this implementation it is more
Dimension array signal control method is not take up the logical resources such as LUT, DFF, to reach saving logical resource, improves placement-and-routing's cloth
Passband and other effects.
Embodiment three
The present embodiment additionally provides a kind of device, shown in Figure 4 comprising processor 401, memory 402 and communication
Bus 403, in which:
Communication bus 403 is for realizing the connection communication between processor 401 and memory 402；
Processor 401 is for executing one or more program stored in memory 402, to realize following steps:
Establish RTL netlist；RTL netlist includes the related information of multi-dimension array signal and multi-dimension array signal；
According to the related information of multi-dimension array signal, RAM corresponding with multi-dimension array signal is created；
RAM is mapped on FPGA device.
In the present embodiment, establishing RTL netlist includes reading in preset design file, establishes RTL according to preset design file
Netlist；The related information of multi-dimension array signal includes that the multi-dimension array signal connecting with multi-dimension array signal writes node and multidimensional
The multi-dimension array signal of array signal connection reads at least one of node；It includes: preset design that multi-dimension array signal, which writes node,
First selection signal, data input signal and clock signal in file；It includes preset design text that multi-dimension array signal, which reads node,
The second selection signal in part, data output signal.
It is worth noting that, the related information according to multi-dimension array signal of the present embodiment, creation and multi-dimension array signal
Corresponding RAM includes: traversal RTL netlist, determines each multi-dimension array signal in RTL netlist；According to each multi-dimension array signal
Corresponding each related information, creation correspond RAM with each multi-dimension array signal.Specifically, determining that each multi-dimension array signal is write
Node creates the write port that the corresponding each RAM node of node is write with each multi-dimension array signal；And/or determine each multi-dimension array letter
Number read node, the read port of creation and the corresponding each RAM node of each multi-dimension array signal reading node.Wherein determine some multidimensional battle array
Column signal writes node, and creating and writing the write port of the corresponding RAM node of node with some multi-dimension array signal includes: by some multidimensional
Array signal writes the first selection signal of node, the address signal as RAM node write port；Some multi-dimension array signal is write
The data input signal of node, the data input signal as RAM node write port；Some multi-dimension array signal is write into node
Clock signal, the clock signal as RAM node write port.Wherein determine some multi-dimension array signal read node, creation and certain
The read port that a multi-dimension array signal reads the corresponding RAM node of node includes: that some multi-dimension array signal is read the second of node
Selection signal grade, the address signal as RAM node read port；The data that some multi-dimension array signal reads node are exported into letter
Number, the data output signal as RAM node read port.
Processor 401 in certain the present embodiment can also be after creating RAM corresponding with multi-dimension array signal, will
Before RAM is mapped on FPGA device, node can also be write according to multi-dimension array signal and multi-dimension array signal reads the company of node
Relationship is connect, the read-write mode of RAM is set.
It is worth noting that, not fully expounding first embodiment, second in the present embodiment in fact in order not to burden explanation
Apply example, all examples in 3rd embodiment, it is understood that, first embodiment, second embodiment, in 3rd embodiment
All examples are suitable for the present embodiment.
The present embodiment also provides a kind of computer readable storage medium, the computer-readable recording medium storage have one or
The multiple programs of person, one or more program can be executed by one or more processor, with realization such as embodiment one and/or in fact
The step of applying multi-dimension array signal control method in example two.
The present invention provides a kind of device and computer readable storage medium, for realizing the multi-dimension array control in each embodiment
Method processed multi-dimension array control method of the invention is by establishing RTL netlist；Wherein RTL netlist include multi-dimension array signal and
The related information of multi-dimension array signal；According to the related information of multi-dimension array signal, create corresponding with multi-dimension array signal
RAM；RAM is mapped on FPGA device, solve it is existing by multi-dimension array signal carry out dimension-reduction treatment after, be mapped to FPGA
In, cause to occupy multi-dimension array signal processing a large amount of resource, multi-dimension array signal control method provided in this embodiment leads to
RAM corresponding to multi-dimension array signal creation is crossed, so that multi-dimension array signal and not having to carry out dimension-reduction treatment, and then by creation
RAM is mapped on FPGA, makes full use of the macroelement RAM on FPGA, reaches saving logical resource, and it is logical to improve placement-and-routing's cloth
Rate.
It should be noted that, in this document, the terms "include", "comprise" or its any other variant are intended to non-row
His property includes, so that the process, method, article or the device that include a series of elements not only include those elements, and
And further include other elements that are not explicitly listed, or further include for this process, method, article or device institute it is intrinsic
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including being somebody's turn to do
There is also other identical elements in the process, method of element, article or device.
The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.
Through the above description of the embodiments, those skilled in the art can be understood that above-described embodiment side
Method can be realized by means of software and necessary general hardware platform, naturally it is also possible to by hardware, but in many cases
The former is more preferably embodiment.Based on this understanding, technical solution of the present invention substantially in other words does the prior art
The part contributed out can be embodied in the form of software products, which is stored in a storage medium
In (such as ROM/RAM, magnetic disk, CD), including some instructions are used so that a device (can be mobile phone, computer, service
Device, air conditioner or network equipment etc.) method that executes each embodiment of the present invention.
The embodiment of the present invention is described with above attached drawing, but the invention is not limited to above-mentioned specific
Embodiment, the above mentioned embodiment is only schematical, rather than restrictive, those skilled in the art
Under the inspiration of the present invention, without breaking away from the scope protected by the purposes and claims of the present invention, it can also make very much
Form, all of these belong to the protection of the present invention.
Claims (10)
1. a kind of multi-dimension array signal control method, which is characterized in that the multi-dimension array signal control method includes:
Establish RTL netlist；The RTL netlist includes the related information of multi-dimension array signal and the multi-dimension array signal；
According to the related information of the multi-dimension array signal, RAM corresponding with the multi-dimension array signal is created；
The RAM is mapped on FPGA device.
2. multi-dimension array signal control method as described in claim 1, which is characterized in that the RTL netlist of establishing includes:
Preset design file is read in, RTL netlist is established according to the preset design file；
The related information of the multi-dimension array signal include the multi-dimension array signal being connect with the multi-dimension array signal write node,
The multi-dimension array signal connecting with the multi-dimension array signal reads at least one of node.
3. multi-dimension array signal control method as claimed in claim 2, which is characterized in that the multi-dimension array signal writes node
It include: first selection signal, data input signal and the clock signal in the preset design file；The multi-dimension array signal
Reading node includes the second selection signal in the preset design file, data output signal.
4. multi-dimension array signal control method as described in any one of claims 1-3, which is characterized in that described according to described more
The related information of array signal is tieed up, creating RAM corresponding with the multi-dimension array signal includes:
The RTL netlist is traversed, determines each multi-dimension array signal in the RTL netlist；
According to each related information corresponding with each multi-dimension array signal, creation with each multi-dimension array signal one by one
Corresponding RAM.
5. multi-dimension array signal control method as claimed in claim 4, which is characterized in that the basis and each multidimensional battle array
The corresponding each related information of column signal, creation correspond RAM with each multi-dimension array signal and include:
Determine that each multi-dimension array signal writes node, creation and each multi-dimension array signal write the corresponding each RAM section of node
The write port of point；
And/or
Determine that each multi-dimension array signal reads node, creation and each multi-dimension array signal read the corresponding each RAM section of node
The read port of point.
6. multi-dimension array signal control method as claimed in claim 5, which is characterized in that determine that some multi-dimension array signal is write
Node, creating the write port for writing the corresponding RAM node of node with some described multi-dimension array signal includes:
The first selection signal that some described multi-dimension array signal is write to node, the address as the RAM node write port are believed
Number；
Some described multi-dimension array signal is write to the data input signal of node, the data as the RAM node write port are defeated
Enter signal；
The clock signal that some described multi-dimension array signal is write to node, the clock signal as the RAM node write port.
7. multi-dimension array signal control method as claimed in claim 5, which is characterized in that determine that some multi-dimension array signal is read
Node, the read port for creating RAM node corresponding with some multi-dimension array signal reading node include:
The second selection signal grade that some described multi-dimension array signal is read to node, the address as the RAM node read port
Signal；
Some described multi-dimension array signal is read to the data output signal of node, the data as the RAM node read port are defeated
Signal out.
8. multi-dimension array signal control method as described in any one of claims 1-3, which is characterized in that it is described creation with it is described
After the corresponding RAM of multi-dimension array signal, include: before the RAM is mapped on FPGA device
Node is write according to the multi-dimension array signal and the multi-dimension array signal reads the connection relationship of node, and the RAM is set
Read-write mode.
9. a kind of device, which is characterized in that described device includes processor, memory and communication bus；
The communication bus is for realizing the connection communication between processor and memory；
The processor is for executing one or more program stored in memory, to realize as appointed in claim 1 to 8
The step of multi-dimension array signal control method described in one.
10. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage have one or
Multiple programs, one or more of programs can be executed by one or more processor, to realize such as claim 1 to 8
Any one of described in multi-dimension array signal control method the step of.
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