CN109408419B - DSP hardware abstraction layer and DSP processor - Google Patents
DSP hardware abstraction layer and DSP processor Download PDFInfo
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- CN109408419B CN109408419B CN201811182025.2A CN201811182025A CN109408419B CN 109408419 B CN109408419 B CN 109408419B CN 201811182025 A CN201811182025 A CN 201811182025A CN 109408419 B CN109408419 B CN 109408419B
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Abstract
The application relates to a DSP hardware abstraction layer and a DSP processor. The DSP hardware abstraction layer comprises: bus interface adaptation module, message receiving analysis module and subassembly interface adaptation module, keep apart DSP hardware abstraction layer and the bus drive of bottom completely through bus interface adaptation module, keep apart DSP hardware abstraction layer and the waveform component on upper strata completely through subassembly interface adaptation module, thereby guarantee that DSP hardware abstraction layer code has the independent characteristic of platform, make DSP hardware abstraction layer can be applied to on different hardware platforms very conveniently, higher commonality and scalability have, the portability on DSP hardware abstraction layer has effectively been improved.
Description
Technical Field
The present application relates to the field of wireless communications technologies, and in particular, to a DSP hardware abstraction layer and a DSP processor.
Background
With the rapid development of wireless communication technology, software radio technology is mature day by day and is widely applied to the fields of military communication, personal mobile communication and the like, and the ideal state of software radio is to enable wireless communication equipment to adopt a universal, standard and modularized hardware platform to realize various functions of the wireless equipment in a software programming and dynamic loading and unloading mode.
In wireless communication, bottom layer interface drivers of a DSP (Digital Signal Processing) processor are large in difference and complex, and for different bottom layer interface drivers and waveform components, a specific hardware abstraction layer needs to be developed to be coupled with the bottom layer interface drivers and an upper layer waveform component, respectively, resulting in low portability of the DSP hardware abstraction layer.
Disclosure of Invention
In view of the above, it is desirable to provide a DSP hardware abstraction layer and a DSP processor capable of improving portability of the DSP hardware abstraction layer.
A DSP hardware abstraction layer, comprising: the device comprises a bus interface adaptation module, a message receiving and analyzing module and a component interface adaptation module;
the bus interface adaptation module is respectively connected with an interface driving layer comprising at least one interface driver and the message receiving and analyzing module, and is used for receiving a first hardware abstraction layer message transmitted by the interface driver and sending the first hardware abstraction layer message to the message receiving and analyzing module; the first hardware abstraction layer message is a message to be received of the current processor, which is determined by the interface driver according to a receiving destination logic address in the first hardware abstraction layer message;
the message receiving and analyzing module is connected with the component interface adapting module and used for analyzing the first hardware abstraction layer message to obtain data to be received and a receiving destination logical address and sending the data to be received and the receiving destination logical address to the component interface adapting module;
the component interface adaptation module is connected with a waveform component of an upper layer and used for determining a waveform component port according to the receiving destination logic address and sending the data to be received to a destination waveform component through the determined waveform component port.
A DSP processor comprising: the DSP hardware abstraction layer, the waveform component and the interface driver layer of any embodiment; the waveform component is connected with the DSP hardware abstraction layer, and the DSP hardware abstraction layer is connected with the interface driving layer.
Above-mentioned DSP hardware abstraction layer and DSP treater, bus drive through bus interface adaptation module with DSP hardware abstraction layer and bottom is kept apart completely, waveform component through subassembly interface adaptation module with DSP hardware abstraction layer and upper strata keeps apart completely, thereby guarantee that DSP hardware abstraction layer code has the platform independence characteristic, make DSP hardware abstraction layer can be applied to on different hardware platforms very conveniently, higher commonality and scalability have, effectively improved the portability of DSP hardware abstraction layer.
Drawings
FIG. 1 is a diagram illustrating the architecture of a DSP hardware abstraction layer in one embodiment;
FIG. 2 is a diagram illustrating the architecture of the DSP hardware abstraction layer in one embodiment;
FIG. 3 is a diagram illustrating the structure of a DSP hardware abstraction layer in one embodiment;
FIG. 4 is a diagram of an embodiment of a DSP processor.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, a DSP (Digital Signal Processing) hardware abstraction layer is provided, as shown in fig. 1, the DSP hardware abstraction layer 110 includes: a bus interface adapting module 111, a message receiving and analyzing module 112, and a component interface adapting module 113.
The bus interface adaptation module 111 is connected to an interface driver layer including at least one interface driver and the message receiving and analyzing module 112, and is configured to receive a first hardware abstraction layer message transmitted by the interface driver, and send the first hardware abstraction layer message to the message receiving and analyzing module 112. The first hardware abstraction layer message is a message to be received which is determined by the interface driver according to the receiving destination logic address in the first hardware abstraction layer message. The message to be received refers to a message which needs to be received by the current processor where the interface driver is located.
The bus interface adaptation module 111 defines a standard interaction interface between the hardware abstraction layer and the interface driver layer of the bottom layer bus, and is used for shielding the driving difference of different bus interfaces of the bottom layer hardware platform. The specific interface driver of the bus is implemented by a special driver engineer, and after the driver engineer completes the development of the internal functions of the driver, the interface driver of the bus is encapsulated according to the standard function interface defined by the bus interface adaptation module 111, so that the data interaction with the hardware abstraction layer can be implemented. Similarly, the hardware abstraction layer implemented according to the standard function interface design defined by the bus interface adaptation module 111 can also be adapted to any interface driver that also supports the interface, so as to separate the DSP hardware abstraction layer 110 from the interface driver at the bottom layer, thereby enabling the hardware abstraction layer to have good cross-platform portability.
In the present embodiment, the bus interface adaptation module 111 defines a bus read function and a data push function. The bus reading function is realized in the interface driver, data with a logic address of LD is read from an external interface and provided for the hardware abstraction layer, and if the interface driver receives the data with the logic address of LD, the data pushing function of the hardware abstraction layer is called to push the data to the hardware abstraction layer; the data pushing function is realized in the hardware abstraction layer, is provided for the interface driver to call, and is used for pushing the data received from the external interface to the hardware abstraction layer.
The message receiving and analyzing module 112 is connected to the component interface adapting module 113, and is configured to analyze the first hardware abstraction layer message to obtain data to be received and a receiving destination logical address, and send the data to be received and the receiving destination logical address to the component interface adapting module 113.
The component interface adaptation module 113 is connected to the waveform component in the upper layer, and is configured to determine a waveform component port according to the received destination logical address, and send data to be received to the destination waveform component through the determined waveform component port.
The component interface adaptation module 113 is a key module for implementing data interaction between the hardware abstraction layer and the waveform component and isolating the hardware abstraction layer from the waveform component. In this embodiment, the component interface adaptation module 113 includes a component receiving interface, and the component receiving interface is configured to read data from the hardware abstraction layer into the waveform component based on a defined component receiving interface function.
The DSP hardware abstraction layer 110 is separated from the upper-layer waveform component by the component interface adaptation module 113, so that the DSP hardware abstraction layer 110 code has the independent characteristic of the upper-layer waveform component.
Above-mentioned DSP hardware abstraction layer 110, bus drive complete isolation with DSP hardware abstraction layer 110 and bottom through bus interface adaptation module 111, waveform components complete isolation with DSP hardware abstraction layer 110 and upper strata through subassembly interface adaptation module 113, thereby guarantee that DSP hardware abstraction layer 110 code has the platform independence characteristic, make DSP hardware abstraction layer 110 can apply to different hardware platforms very conveniently, have higher commonality and scalability, effectively improved DSP hardware abstraction layer 110's portability.
In an embodiment, the component interface adaptation module 113 is further configured to obtain a data receiving request sent by the waveform component, where the data receiving request carries the specified logical address, and transmit the specified logical address to the bus interface adaptation module 111.
The bus interface adaptation module 111 is further configured to send the designated logical address to each interface driver, so that when a received destination logical address is the same as the designated logical address in the first hardware abstraction layer message received by any interface driver, it is determined that the received first hardware abstraction layer message is a to-be-received message of the current processor.
The designated logical address refers to a logical address of a waveform component port that needs to receive data. When the waveform component needs to receive data, the interface driver layer is informed of an appointed logic address of the data needing to be received through the hardware abstraction layer, when the interface driver receives a bus message, whether a receiving target logic address carried in the bus message is the appointed logic address is judged firstly, if yes, the hardware abstraction layer message received by the interface driver is determined to be a message to be received by a current processor, the interface driver sends the hardware abstraction layer message carried in the bus message to the hardware abstraction layer, and if not, the bus message is discarded.
More specifically, in the bus interface adaptation module 111, this function is implemented by a bus read function. And transmitting the appointed logical address to the interface driver through a bus read function so as to inform the interface driver that the current processor needs to receive a hardware abstraction layer message with the received target logical address as the appointed logical address.
By sending the designated logical address to the interface driver, the interface driver filters out data irrelevant to the current DSP processor according to the designated logical address, and the validity of the data received by the hardware abstraction layer through the interface driver is ensured.
In one embodiment, sending data to be received to a destination waveform component through the determined waveform component port comprises: when the determined waveform component port is in a working state, comparing the data priority of the data to be received with the data priority of the data currently received by the waveform component port; and when the data priority of the data to be received is higher than that of the currently received data, interrupting the sending of the currently received data and sending the data to be received to the corresponding waveform component through the waveform component port. Wherein, the current received data refers to the data being received by the waveform component port.
Further, when the data priority of the currently received data is higher than that of the data to be received, the data to be received is queued according to the data priority, and when the receiving condition is met, the data to be received is sent to the corresponding waveform component through the waveform component port. The receiving condition means that the port is currently in an idle state after the data with higher priority level is sent/received through the port.
By judging whether the port of the waveform component is in a working state, namely whether the port is receiving data, if so, the priority of the data is further judged so as to determine whether to queue the data to be received or interrupt the transmission of the currently received data and preferentially transmit the data with high priority of the data.
In one embodiment, as shown in fig. 2, the DSP hardware abstraction layer 110 further includes: a message sending and encapsulating module 114 and an LD (Logical Address-Destination) and PD (Physical Address-Destination) mapping table module 115, where the message sending and encapsulating module 114 is connected to the component interface adapting module 113, the LD-PD mapping table module 115 and the bus interface adapting module 111 respectively.
In this embodiment, the component interface adapting module 113 is further configured to obtain data to be sent and a sending destination logical address requested to be sent by the waveform component, and transmit the data to be sent and the sending destination logical address to the message sending and encapsulating module 114. The data to be transmitted refers to data that needs to be transmitted to other waveform components from any waveform component in waveform application. The transmit destination logical address refers to the logical address of the destination waveform component port.
Specifically, the component interface adaptation module 113 further includes a component transmission interface for enabling writing of data from the waveform component to the hardware abstraction layer based on the defined component transmission interface function.
The message sending and encapsulating module 114 is configured to query a first address mapping table (LD-PD mapping table) pre-stored in a first address mapping table module in the LD-PD mapping table module 115 according to the sending destination logical address to obtain a sending destination physical address, encapsulate the to-be-sent data and the sending destination logical address into a second hardware abstraction layer message, and transmit the second hardware abstraction layer message and the sending destination physical address to the bus interface adaptation module 111.
In an embodiment, the message sending and encapsulating module 114 encapsulates the data to be sent and the sending destination logical address into a second hardware abstraction layer message in the format of table 1. The hardware abstraction layer message is packaged in the format of table 1, so that the frame format of the hardware abstraction layer message is simple and efficient, and further the effective load is maximized.
TABLE 1 hardware abstraction layer message frame format
The second hardware abstraction layer message is a message that needs to be sent to the external processor. The LD-PD mapping table module 115 pre-stores a first address mapping table, where a plurality of logical address-physical address pairs are recorded in the first address mapping table. By inquiring the first address mapping table, the physical address corresponding to the sending destination logical address can be obtained, and the corresponding physical address is the sending destination physical address, namely the bus interface physical address of the processor where the destination waveform component is located.
The bus interface adaptation module 111 is further configured to determine an interface driver for sending data to be sent according to the sending destination physical address, and send the second hardware abstraction layer packet to the determined interface driver, so that the interface driver sends the data to be sent to a processor corresponding to the sending destination physical address.
And determining the bus name to which the data to be sent needs to be sent according to the sending target physical address, and further determining the interface drive according to the determined bus name. For example, when the bus name is SRIO (Serial Rapid I/O), it may be determined that the corresponding interface driver is an SRIO interface driver; when the bus name is HPI (Host Port Interface), it can be determined that the corresponding Interface driver is an HPI Interface driver. And then sending the second hardware abstraction layer message to the determined interface driver so as to send the data to be sent to the processor corresponding to the sending destination physical address through the interface driver.
The bus interface adaptation module 111 further defines a bus write function, which is implemented in the interface driver layer and provided to the hardware abstraction layer to send data to the external interface. More specifically, the bus interface adaptation module 111 determines an interface driver for transmitting data to be transmitted according to the transmission destination physical address, and writes the second hardware abstraction layer packet to the determined interface driver by calling a bus write function corresponding to the determined interface driver.
Furthermore, the interface driver layer also maintains an address mapping table, which is the same as the first address mapping table of the hardware abstraction layer, and in order to distinguish the two, the address mapping table maintained by the interface driver layer is called as a second address mapping table. When the hardware abstraction layer does not transmit the determined sending destination physical address to the interface driver layer, the interface driver layer can query the second address mapping table according to the sending destination logical address in the second hardware abstraction layer message, determine the sending destination physical address, and then send the second hardware abstraction layer message to the processor corresponding to the determined sending destination physical address.
In one embodiment, sending the second hardware abstraction layer packet to the determined interface driver includes: and generating a data sending request, sending the data sending request to the determined interface driver, and sending a second hardware abstraction layer message to the determined interface driver when receiving confirmation information of the interface driver responding to the data sending request.
The function is mainly realized by a data sending request function and a data sending request confirmation function defined by the bus interface adaptation module 111. The data sending request function is realized in an interface driver layer, is called by a hardware abstraction layer and is used for sending a data sending request to the interface driver; the data sending request confirmation function is implemented in the hardware abstraction layer, is called by the interface driver layer, and is used for feeding back confirmation information (ACK signal) to the hardware abstraction layer to inform the hardware abstraction layer that the data message with the logical address of LD can be sent to the interface driver next.
More specifically, generating a data transmission request, and transmitting the data transmission request to the determined interface driver, includes: calling a data sending request function provided by the determined interface driver, generating a data sending request, and sending the data sending request to the determined interface driver; sending a second hardware abstraction layer packet to the determined interface driver, including: and calling a bus write function provided by the determined interface driver, and sending a second hardware abstraction layer message to the determined interface driver.
In one embodiment, as shown in fig. 3, the DSP hardware abstraction layer 110 further includes: the LD-PD configuration module 116 and the LD-PD configuration module 116 are respectively connected to the message receiving and analyzing module 112 and the LD-PD mapping table module 115.
The message receiving and analyzing module 112 is further configured to, when the received destination logical address is a hardware abstraction layer logical address, obtain a logical address-physical address pair in the data to be received, and send the logical address-physical address pair to the LD-PD configuration module 116. The LD-PD configuration module 116 adds the logical address-physical address pairs to the first address mapping table.
The address mapping table configuration message refers to a hardware abstraction layer message sent by a software radio core framework and used for configuring an address mapping table. Specifically, when the message receiving and analyzing module 112 analyzes the received hardware abstraction layer message to obtain that the received destination logical address is consistent with the hardware abstraction layer logical address, it may be determined that the hardware abstraction layer message is a message sent to the hardware abstraction layer. The hardware abstraction layer logical address is an address for uniquely representing the hardware abstraction layer, and is represented by HAL _ LD. When the first address mapping table is established in the hardware abstraction layer, i.e. the HAL _ LD and the HAL _ PD (hardware abstraction layer physical address) of the hardware abstraction layer are recorded, when the receiving destination logical address is consistent with the HAL _ LD recorded in the first address mapping table, it can be determined that the hardware abstraction layer packet is a packet sent to the hardware abstraction layer.
When the data to be received in the hardware abstraction layer message obtained by the analysis is the address mapping table configuration field, it is determined that the hardware abstraction layer message is the address mapping table configuration message, the message receiving and analyzing module 112 extracts an LD-PD pair from the data to be received obtained by the analysis, and adds the LD-PD to the first address mapping table of the hardware abstraction layer through the LD-PD configuration module 116.
More specifically, the LD-PD configuration module 116 is configured to be responsible for interfacing with a software radio software platform, the software radio software platform generates an LD-PD configuration command (LD _ PD _ CMD) according to a waveform component port connection scheme planned in advance and sends the LD-PD configuration command (LD _ PD _ CMD) to each hardware abstraction layer, and the LD-PD configuration module 116 configures LD-PD mapping tables of the hardware abstraction layer and the driver layer, thereby implementing connection between input and output ports of different waveform components. The specific format of the LD-PD configuration command is shown in table 2 below:
TABLE 2 LD-PD configuration Command Format
Further, the LD-PD configuration module 116 is further connected to the bus interface adaptation module 111, and configured to send the logical address-physical address pair to the bus interface adaptation module 111; the bus interface adaptation module 111 is further configured to add the logical address-physical address pairs to a second address mapping table of the interface driver layer.
The bus interface adaptation module 111 calls a mapping table configuration function provided by the driver, and adds the LD-PD to the second address mapping table of the interface driver layer, so that the interface driver can determine the sending destination physical address of the second hardware abstraction layer packet according to the query of the second address mapping table. The mapping table configuration function is predefined in the bus interface adaptation module 111 and implemented in the interface driver layer, and the function is called by the bus interface adaptation module 111 to implement the configuration of the LD-PD mapping table in the interface driver layer.
Above-mentioned DSP hardware abstraction layer 110, bus drive complete isolation with DSP hardware abstraction layer 110 and bottom through bus interface adaptation module 111, waveform components complete isolation with DSP hardware abstraction layer 110 and upper strata through subassembly interface adaptation module 113, thereby guarantee that DSP hardware abstraction layer 110 code has the platform independence characteristic, make DSP hardware abstraction layer 110 can apply to different hardware platforms very conveniently, have higher commonality and scalability, effectively improved DSP hardware abstraction layer 110's portability. Meanwhile, a large amount of repeated and low-quality development of a hardware abstraction layer is avoided, the purposes of one-time development and multi-place use are achieved, and the high efficiency, stability and reliability of the DSP processor are greatly improved.
In one embodiment, a DSP processor 100 is provided, as shown in fig. 4, the DSP processor 100 comprising: the DSP hardware abstraction layer 110, the waveform component 120, and the interface driver layer 130 in any embodiment. The waveform component 120 is connected to the DSP hardware abstraction layer 110, and the DSP hardware abstraction layer 110 is connected to the interface driver layer 130.
The waveform component 120 refers to a software module that specifically performs a certain individual function in the communication system. Specifically, the waveform component 120 is configured to receive data to be received sent by the DSP hardware abstraction layer 110, perform corresponding processing of functions of the data to be received, and send the data to be sent and a sending destination logical address to the DSP hardware abstraction layer 110.
The interface driver layer 130 is used to enable data communication between the current processor and the external processor. Specifically, the interface driver layer 130 is configured to receive a first hardware abstraction layer packet sent by the external processor through the interface driver, and send the first hardware abstraction layer packet to the DSP hardware abstraction layer 110.
When the interface driver adopts a packet switching bus transmission mode, the interface driver receives a bus message sent by an external processor, queries a second address mapping table according to a receiving destination physical address in the bus message to obtain a receiving destination logical address, and sends a first hardware abstraction layer message in the bus message to the DSP hardware abstraction layer 110 when the received bus message is determined to be a message to be received by the current processor according to the receiving destination logical address. More specifically, the interface driver receives a bus packet sent by the external processor, queries an LD-PD mapping table maintained by the interface driver layer 130 according to a destination physical address (PD) field in the bus packet, finds a corresponding LD, confirms that this packet is data to be received by the local waveform component 120 according to the LD, and sends a payload field in the bus packet to the bus interface adaptation module 111 of the hardware abstraction layer by calling a data push function provided by the hardware abstraction layer.
When the interface driver adopts a shared memory transmission mode, the receiving driver receives a first hardware abstraction layer message sent by the external processor, judges whether the data is written according to the read-write identifier, and sends the first hardware abstraction layer message to the DSP hardware abstraction layer 110 if the data is written. More specifically, the receiving driver receives a first hardware abstraction layer message sent by the external processor, and determines whether the data is written according to the read-write identifier, and if the data is written, calls a data push function provided by the hardware abstraction layer to send the first hardware abstraction layer message to the DSP hardware abstraction layer 110.
In an embodiment, the interface driver layer 130 is further configured to send, through the interface driver, the second hardware abstraction layer packet sent by the DSP hardware abstraction layer 110 to the corresponding external processor. The external processor may be any processor including, but not limited to, a DSP, an FPGA (Field Programmable Gate Array), and a CPU (Central Processing Unit).
When the interface driver adopts a packet switching bus transmission mode, the interface driver generates a bus message according to the hardware abstraction layer message and the sending destination physical address, and sends the bus message to a processor corresponding to the sending destination physical address. More specifically, the interface driver obtains a sending destination logical address, obtains a sending destination physical address corresponding to the sending destination logical address from an LD-PD mapping table maintained inside the interface driver layer 130, writes the sending destination physical address into a destination physical address (PD) field in the bus message, writes a hardware abstraction layer message encapsulated by the message encapsulation module into a payload (payload) field in the bus message, and sends out the bus message by the packet switching bus interface driver.
And when the read-write identification bit is writable, the interface driver sends the hardware abstraction layer message to the shared memory corresponding to the sending destination physical address. More specifically, the interface driver directly writes the hardware abstraction layer packet encapsulated by the packet encapsulation module into the shared memory address corresponding to the PD, and sets the read-write flag bit to be readable, so as to inform the interface driver of the destination processor to receive the hardware abstraction layer packet.
Further, the interface driver also has a data priority processing function. When the interface corresponding to the interface drive is in a working state, comparing the data priority of the bus message to be sent with the data priority of the message currently sent by the interface; when the data priority of the bus message to be sent is higher than that of the current sent message, interrupting the sending of the current sent message and sending the bus message to be sent to a processor corresponding to a sending target physical address; otherwise, queuing the bus message to be sent according to the data priority level, and sending the bus message to be sent to a processor corresponding to the sending target physical address when the sending condition is met.
In this embodiment, the data priority level is a priority level of the sending destination physical address, and the priority level of the sending destination physical address is configured in advance according to a requirement. The current sending message refers to a bus message being sent by the interface. The bus message to be sent refers to the bus message which needs to be sent at present but is not sent yet. The sending condition refers to that the bus messages with higher data priority levels are all sent.
The interface driver further judges the data priority level by judging whether the interface corresponding to the interface driver is in a working state, namely whether the bus message is being sent, if so, the interface driver determines whether to queue the bus message to be sent or interrupt the current message sending and preferentially send the bus message with high data priority level. And the interface drives the execution of the data priority processing, so that the processing process of the hardware abstraction layer is further simplified, the data processing efficiency and speed of the hardware abstraction layer are improved, and the system computing resources are saved.
The DSP processor 100 realizes the interactive processing of data through the hardware abstraction layer completely isolated from the bottom bus interface driver, thereby ensuring that the hardware abstraction layer processing has platform-independent characteristics, enabling the hardware abstraction layer to be very conveniently transplanted to different hardware platforms, avoiding the development of a large amount of repetition and low quality of the hardware abstraction layer, realizing the purposes of one-time development and multi-place use, and greatly improving the high efficiency, stability and reliability of the DSP processor 100.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A DSP hardware abstraction layer, comprising: the device comprises a bus interface adaptation module, a message receiving and analyzing module and a component interface adaptation module;
the bus interface adaptation module is respectively connected with an interface driving layer comprising at least one interface driver and the message receiving and analyzing module, and is used for receiving a first hardware abstraction layer message transmitted by the interface driver and sending the first hardware abstraction layer message to the message receiving and analyzing module; the first hardware abstraction layer message is a message to be received which is determined by the interface driver according to a receiving destination logic address in the first hardware abstraction layer message; the first hardware abstraction layer message is received by the interface driver from an external processor;
the message receiving and analyzing module is connected with the component interface adapting module and used for analyzing the first hardware abstraction layer message to obtain data to be received and a receiving destination logical address and sending the data to be received and the receiving destination logical address to the component interface adapting module;
the component interface adaptation module is connected with a waveform component of an upper layer and used for determining a destination waveform component port according to the received destination logic address and sending the data to be received to the destination waveform component through the determined waveform component port; the component interface adaptation module comprises a component receiving interface, and the data to be received is read into the target waveform component through the component receiving interface.
2. The DSP hardware abstraction layer according to claim 1, wherein the component interface adaptation module is further configured to obtain a data receiving request sent by the waveform component, where the data receiving request carries a specified logical address, and transmit the specified logical address to the bus interface adaptation module;
the bus interface adaptation module is further configured to send the designated logical address to each interface driver, so that when a received destination logical address is the same as the designated logical address in a first hardware abstraction layer message received by any interface driver, it is determined that the received first hardware abstraction layer message is a to-be-received message of a current processor.
3. The DSP hardware abstraction layer according to claim 1, wherein said sending said data to be received to a destination waveform component through said determined waveform component port comprises: when the determined waveform component port is in a working state, comparing the data priority of the data to be received with the data priority of the data currently received by the waveform component port; when the data priority of the data to be received is higher than that of the currently received data, interrupting the sending of the currently received data, and sending the data to be received to a corresponding waveform component through the waveform component port; and when the data priority of the current received data is higher than that of the data to be received, queuing the data to be received according to the data priority, and when a receiving condition is met, sending the data to be received to a corresponding waveform component through the waveform component port.
4. The DSP hardware abstraction layer according to claim 1, further comprising: the device comprises a message sending and packaging module and an LD-PD mapping table module, wherein the message sending and packaging module is respectively connected with the component interface adaptation module, the LD-PD mapping table module and the bus interface adaptation module;
the component interface adaptation module is further configured to acquire data to be sent and a sending destination logical address requested to be sent by the waveform component, and transmit the data to be sent and the sending destination logical address to the message sending encapsulation module;
the message sending and packaging module is used for inquiring a first address mapping table prestored in a first address mapping table module in the LD-PD mapping table module according to the sending target logical address to obtain a sending target physical address, packaging the data to be sent and the sending target logical address into a second hardware abstraction layer message, and transmitting the second hardware abstraction layer message and the sending target physical address to a bus interface adaptation module;
the bus interface adaptation module is further configured to determine an interface driver for sending the data to be sent according to the sending destination physical address, and send the second hardware abstraction layer packet to the determined interface driver, so that the interface driver sends the data to be sent to a processor corresponding to the sending destination physical address.
5. The DSP hardware abstraction layer according to claim 4, wherein said sending said second hardware abstraction layer packet to said determined interface driver comprises: and generating a data sending request, sending the data sending request to the determined interface driver, and sending the second hardware abstraction layer message to the determined interface driver when receiving confirmation information of the interface driver responding to the data sending request.
6. The DSP hardware abstraction layer according to claim 5, wherein said generating a data send request, sending said data send request to said determined interface driver, comprises: and calling a data sending request function provided by the determined interface driver, generating a data sending request, and sending the data sending request to the determined interface driver.
7. The DSP hardware abstraction layer according to claim 4, wherein said sending said second hardware abstraction layer packet to said determined interface driver comprises: and calling a bus write function provided by the determined interface driver, and sending the second hardware abstraction layer message to the determined interface driver.
8. The DSP hardware abstraction layer according to claim 4, further comprising: the LD-PD configuration module is respectively connected with the message receiving and analyzing module and the LD-PD mapping table module;
the message receiving and analyzing module is further configured to, when the receiving destination logical address is a hardware abstraction layer logical address, obtain a logical address-physical address pair in data to be received, and send the logical address-physical address pair to the LD-PD configuration module;
the LD-PD configuration module adds the logical address-physical address pair to the first address mapping table.
9. The DSP hardware abstraction layer according to claim 8, wherein said LD-PD configuration module is further connected to said bus interface adaptation module for sending said logical address-physical address pair to said bus interface adaptation module;
the bus interface adaptation module is further configured to add the logical address-physical address pair to a second address mapping table of the interface driver layer.
10. A DSP processor, comprising: the DSP hardware abstraction layer, waveform component, and interface driver layer of any one of claims 1 to 9; the waveform component is connected with the DSP hardware abstraction layer, and the DSP hardware abstraction layer is connected with the interface driving layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811182025.2A CN109408419B (en) | 2018-10-11 | 2018-10-11 | DSP hardware abstraction layer and DSP processor |
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| CN110413327B (en) * | 2019-07-16 | 2022-07-19 | 创新先进技术有限公司 | Hardware driving method and device based on hardware abstraction layer |
| CN110908811B (en) * | 2019-11-01 | 2022-03-18 | 中国人民解放军国防科技大学 | Hardware abstraction layer message forwarding method based on cache dynamic allocation |
| CN110932737B (en) * | 2019-11-01 | 2021-04-06 | 中国人民解放军国防科技大学 | SCA waveform assembly combination and deployment method |
| CN110855552B (en) * | 2019-11-01 | 2021-09-03 | 中国人民解放军国防科技大学 | Hardware abstraction layer message forwarding method based on cache static allocation |
| CN111404745B (en) * | 2020-03-13 | 2020-11-10 | 上海介方信息技术有限公司 | Connection method and terminal supporting interconnection of waveform and logic equipment |
| CN112511526B (en) * | 2020-11-25 | 2023-01-24 | 深圳致星科技有限公司 | Data transmission method, device and readable storage medium |
| CN112799631B (en) * | 2021-01-22 | 2024-03-22 | 中汽创智科技有限公司 | Optimizing system and optimizing method for controlling DSP (digital Signal processor) on android system |
| CN115269221A (en) * | 2022-07-11 | 2022-11-01 | 上海介方信息技术有限公司 | FPGA hardware abstraction layer design method and system based on shared memory mechanism |
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