CN109408419A - DSP hardware level of abstraction and dsp processor - Google Patents
DSP hardware level of abstraction and dsp processor Download PDFInfo
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- CN109408419A CN109408419A CN201811182025.2A CN201811182025A CN109408419A CN 109408419 A CN109408419 A CN 109408419A CN 201811182025 A CN201811182025 A CN 201811182025A CN 109408419 A CN109408419 A CN 109408419A
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Abstract
This application involves a kind of DSP hardware level of abstraction and dsp processors.The DSP hardware level of abstraction includes: bus interface adaptation module, message receives parsing module and component interface adaptation module, it is by bus interface adaptation module that the bus driver of DSP hardware level of abstraction and bottom is completely isolated, it is by component interface adaptation module that the waveform components of DSP hardware level of abstraction and upper layer are completely isolated, there is platform independent property to guarantee that DSP hardware is abstracted layer identification code, DSP hardware level of abstraction is easily applied on different hardware platforms, Universal and scalability with higher, effectively increase the portability of DSP hardware level of abstraction.
Description
Technical field
This application involves wireless communication technology fields, more particularly to a kind of DSP hardware level of abstraction and dsp processor.
Background technique
With the fast development of wireless communication technique, software and radio technique is increasingly mature, in military communication, personal movement
The fields such as communication are found broad application, the perfect condition of software radio be make wireless telecom equipment using one general, standard,
Modular hardware platform realizes the various functions of wireless device by way of software programming and dynamic plus unloading.
In wireless communications, the bottom of DSP (Digital Signal Processing, Digital Signal Processing) processor
Interface driver otherness is larger and complexity needs to develop specific hardware and take out for the driving of different physical layer interfaces and waveform components
As layer causes the portability of DSP hardware level of abstraction low to couple respectively with physical layer interface driving and upper waveform component.
Summary of the invention
Based on this, it is necessary in view of the above technical problems, provide a kind of portability that can be improved DSP hardware level of abstraction
DSP hardware level of abstraction and dsp processor.
A kind of DSP hardware level of abstraction, comprising: bus interface adaptation module, message receive parsing module and component interface
Adaptation module；
The bus interface adaptation module respectively with interface driver layer and the report including at least one interface driver
Text receives parsing module connection, hard by described first for receiving the first hardware abstraction layer message of the interface driver transmission
Part level of abstraction message is sent to the message and receives parsing module；The first hardware abstraction layer message is the interface driver root
According to the reception purpose logical address in the first hardware abstraction layer message, it is determined as the message to be received of current processor；
The message receives parsing module and connect with the component interface adaptation module, takes out for parsing first hardware
As layer message obtains data to be received and receives purpose logical address, logically by the data to be received and the reception purpose
Location is sent to the component interface adaptation module；
The component interface adaptation module and the waveform components on upper layer connect, for according to the reception purpose logical address
It determines waveform components port, the data to be received is sent to purpose sets of waveforms by the identified waveform components port
Part.
A kind of dsp processor, comprising: DSP hardware level of abstraction, waveform components and interface driver described in any one embodiment
Layer；The waveform components are connect with the DSP hardware level of abstraction, and the DSP hardware level of abstraction is connect with the interface driver layer.
Above-mentioned DSP hardware level of abstraction and dsp processor, by bus interface adaptation module by DSP hardware level of abstraction and bottom
The bus driver of layer is completely isolated, by component interface adaptation module that the waveform components of DSP hardware level of abstraction and upper layer are complete
Isolation enables DSP hardware level of abstraction very convenient to guarantee that DSP hardware is abstracted layer identification code and has platform independent property
Ground is applied on different hardware platforms, Universal and scalability with higher, and effectively increase DSP hardware level of abstraction can
Transplantability.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of DSP hardware level of abstraction in one embodiment；
Fig. 2 is the structural schematic diagram of DSP hardware level of abstraction in one embodiment；
Fig. 3 is the structural schematic diagram of DSP hardware level of abstraction in one embodiment；
Fig. 4 is the structural schematic diagram of dsp processor in one embodiment.
Specific embodiment
It is with reference to the accompanying drawings and embodiments, right in order to which the objects, technical solutions and advantages of the application are more clearly understood
The application is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the application, not
For limiting the application.
In one embodiment, a kind of DSP (Digital Signal Processing, Digital Signal Processing) hardware is provided
Level of abstraction, as shown in Figure 1, the DSP hardware level of abstraction 110 includes: bus interface adaptation module 111, message reception parsing module
112 and component interface adaptation module 113.
Bus interface adaptation module 111 connects with the interface driver layer and message for including at least one interface driver respectively
It receives parsing module 112 to connect, for the first hardware abstraction layer message of receiving interface driving transmission, by the first hardware abstraction layer report
Text is sent to message and receives parsing module 112.First hardware abstraction layer message is interface driver according to the first hardware abstraction layer report
The message to be received that reception purpose logical address in text determines.Message to be received refers to current processor locating for interface driver
Need received message.
Wherein, bus interface adaptation module 111 defines marks between hardware abstraction layer and the interface driver layer of bottom bus
Quasi- interactive interface, for realizing the function of shielding bottom hardware platform different bus interface driver difference.Wherein, specific total
The interface drive program of line realized by special driving engineer, driving engineer complete the exploitation of driver built-in function with
Afterwards, the interface driver of bus need to be only packaged according to the canonical function interface that bus interface adaptation module 111 defines
Realize the data interaction with hardware abstraction layer.Equally, the canonical function Interface design defined according to bus interface adaptation module 111
The hardware abstraction layer of realization, also can with equally support that any interface driver of the interface is adapted to, realization DSP hardware is taken out
As layer 110 is separated with the interface driver of bottom, to make hardware abstraction layer that there is good cross-platform transplantability.
In the present embodiment, bus interface adaptation module 111 defines bus and reads function and data-pushing function.Wherein,
Bus is read function and is realized in interface driver, is supplied to hardware abstraction layer from external interface and reads in the data that logical address is LD,
If interface driver receives the data that logical address is LD, call the data-pushing function of hardware abstraction layer by data-pushing
To hardware abstraction layer；Data-pushing function is realized in hardware abstraction layer, interface driver calling is supplied to, for that will connect from outside
The data-pushing that mouth receives is to hardware abstraction layer.
Message receives parsing module 112 and connect with component interface adaptation module 113, for parsing the first hardware abstraction layer report
Text obtains data to be received and receives purpose logical address, and data to be received and reception purpose logical address are sent to component and are connect
Mouth adaptation module 113.
Component interface adaptation module 113 is connect with the waveform components on upper layer, for determining according to purpose logical address is received
Data to be received are sent to purpose waveform components by identified waveform components port by waveform components port.
Component interface adaptation module 113 is the data interaction realized between hardware abstraction layer and waveform components, and by hardware
The key modules that level of abstraction is isolated with waveform components.In the present embodiment, component interface adaptation module 113 includes that component connects
Mouthful, component receiving interface is used for the component receiving interface function based on definition, and realization reads in data to wave from hardware abstraction layer
Shape component.
DSP hardware level of abstraction 110 is separated with upper waveform component by component interface adaptation module 113, guarantees that DSP is hard
110 code of part level of abstraction has the independent property with upper waveform component.
Above-mentioned DSP hardware level of abstraction 110, by bus interface adaptation module 111 by DSP hardware level of abstraction 110 and bottom
Bus driver it is completely isolated, by component interface adaptation module 113 by the waveform components of DSP hardware level of abstraction 110 and upper layer
It is completely isolated, to guarantee that 110 code of DSP hardware level of abstraction has platform independent property, enable DSP hardware level of abstraction 110
Enough to be easily applied on different hardware platforms, Universal and scalability with higher effectively increases DSP hardware
The portability of level of abstraction 110.
In one embodiment, component interface adaptation module 113, the data receiver for being also used to obtain waveform components transmission are asked
It asks, data receiver request carries specified logical address, and specified logical address is transmitted to bus interface adaptation module 111.
Bus interface adaptation module 111 is also used to specified logical address being sent to each interface driver, so that ought arbitrarily connect
In the first received hardware abstraction layer message of mouth driving, when reception purpose logical address is identical as specified logical address, really
Fixed the first received hardware abstraction layer message is the message to be received of current processor.
Wherein, specified logical address refers to the logical address for needing to receive the waveform components port of data.Work as waveform components
When needing to receive data, inform that interface driver layer needs to receive the specified logical address of data by hardware abstraction layer, interface drives
It moves when receiving bus message, first judges whether the reception purpose logical address carried in bus message is to specify logically
Location, if so, determining that the hardware abstraction layer message that interface driver receives is the message to be received of current processor, interface driver
The hardware abstraction layer message carried in bus message is sent to hardware abstraction layer, otherwise abandons the bus message.
More specifically, in bus interface adaptation module 111, which reads function by bus and realizes.It is read by bus
Specified logical address is transferred to interface driver by function, and to inform interface driver, current processor, which needs to receive purpose, is patrolled
Collect the hardware abstraction layer message that address is specified logical address.
By the way that specified logical address is sent to interface driver, make interface driver according to specified logical address, filter out with
The unrelated data of current dsp processor, it is ensured that the validity for the data that hardware abstraction layer is received by interface driver.
In one embodiment, data to be received are sent to purpose waveform components by identified waveform components port,
It include: when identified waveform components port is in running order, by the data priority and waveform components of data to be received
The data priority that port currently receives data is compared；When the data priority of data to be received is higher than current reception data
Data priority when, interrupt the current transmission for receiving data, and data to be received are sent to pair by waveform components port
The waveform components answered.Wherein, currently receiving data refers to waveform components port just in received data.
It further, will be to when the data priority for currently receiving data is higher than the data priority of data to be received
It receives data to be lined up according to high priority data rank, when meeting condition of acceptance, data to be received is passed through into waveform components end
Mouth is sent to corresponding waveform components.Wherein, condition of acceptance refer to the higher data of high priority data rank by port send/
It receives, port is currently at idle state.
By judging whether waveform components port is in running order, namely whether data are being received, if so, into one
Step judges data priority, so that determination is to wait in line data to be received, or interrupt current reception number
According to transmission, preferential send the high data of high priority data rank.
In one embodiment, as shown in Fig. 2, DSP hardware level of abstraction 110 further include: message sends package module 114 and LD
(Logical Address-Destination, purpose logical address)-PD (Physical Address-Destination, mesh
Physical address) mapping table module 115, message send package module 114 reflected respectively with component interface adaptation module 113, LD-PD
Firing table module 115 and bus interface adaptation module 111 connect.
In the present embodiment, component interface adaptation module 113 is also used to obtain the number to be sent that waveform components request is sent
According to send purpose logical address, and by data to be sent and send purpose logical address be transmitted to message send package module
114.Wherein, data to be sent refer to the data for needing to be sent to other waveform components by random waveform component in waveform application.
Send the logical address that purpose logical address refers to purpose waveform components port.
Specifically, component interface adaptation module 113 further includes component transmission interface, is connect for the component transmission based on definition
Data are written from waveform components to hardware abstraction layer for mouth function, realization.
Message sends package module 114, for according in transmission purpose logical address inquiry LD-PD mapping table module 115
The first address mapping table module in the first address mapping table (LD-PD mapping table) for prestoring, obtain sending purpose physical address,
And data to be sent and transmission purpose logical address are packaged into the second hardware abstraction layer message, by the second hardware abstraction layer message
Bus interface adaptation module 111 is transmitted to purpose physical address is sent.
In one embodiment, message sends package module 114 and is packaged into data to be sent and transmission purpose logical address
Second hardware abstraction layer message of 1 format of table.Hardware abstraction layer message is encapsulated using 1 format of table, enables to hardware abstraction layer
Message frame format is succinctly efficient, and then maximizes payload.
1 hardware abstraction layer message frame format of table
Wherein, the second hardware abstraction layer message refers to the message for needing to be sent to ppu.LD-PD mapping table module
The first address mapping table is prestored in 115, and multiple logical address-physical address pair are recorded in the first address mapping table.Pass through
The first address mapping table is inquired, can be obtained physical address corresponding with purpose logical address is sent, the corresponding physical address
The bus interface physical address of processor where as sending purpose physical address namely purpose waveform components.
Bus interface adaptation module 111 is also used to determine according to purpose physical address is sent for sending data to be sent
Interface driver, the second hardware abstraction layer message is sent to identified interface driver, so that interface driver is by number to be sent
The corresponding processor of purpose physical address is sent according to being sent to.
The bus title for determining that data to be sent need to be sent to according to purpose physical address is sent, further according to really
Fixed bus title can determine interface driver.For example, working as the entitled SRIO of bus (Serial Rapid I/O, high speed serialization
Mouthful), it may be determined that corresponding interface driver is SRIO interface driver；As the entitled HPI of bus (Host Port Interface, master
Machine interface), it may be determined that corresponding interface driver is HPI interface driver.And then by the second hardware abstraction layer message be sent to really
Fixed interface driver sends the corresponding processor of purpose physical address will be sent to data to be sent by interface driver.
Bus interface adaptation module 111 also defines bus and writes function, and bus is write function and realized in interface driver layer, mentions
It supplies hardware abstraction layer and sends data to external interface.More specifically, bus interface adaptation module 111 is according to transmission purpose object
Address is managed, determines the interface driver for sending data to be sent, and by calling the corresponding bus of identified interface driver
Function is write, the second hardware abstraction layer message is written to identified interface driver.
Further, also maintenance has an address mapping table, the address mapping table and hardware abstraction to the maintenance of interface driver layer
First address mapping table of layer is identical, to distinguish the two, the address mapping table that interface driver layer is safeguarded is known as the second address and is reflected
Firing table.When identified transmission purpose physical address is not transmitted to interface driver layer by hardware abstraction layer, interface driver layer energy
Enough transmission purpose logical addresses according in the second hardware abstraction layer message inquire the second address mapping table, determine and send purpose object
Address is managed, and then the second hardware abstraction layer message is sent into the corresponding processor of identified transmission purpose physical address.
In one embodiment, the second hardware abstraction layer message is sent to identified interface driver, comprising: generate data
Request is sent, sends data sending request to identified interface driver, when receiving interface driving response data sends request
When confirmation message, the second hardware abstraction layer message is sent to identified interface driver.
The data sending request function and data sending request that the function is mainly defined by bus interface adaptation module 111 are true
Recognize function realization.Wherein, data sending request function is realized in interface driver layer, is called for hardware abstraction layer, for connecing
Mouth driving sends data sending request；Data sending request confirmation function is realized in hardware abstraction layer, for interface driver layer tune
With for informing next logical address can be by hardware abstraction layer to hardware abstraction layer feedback acknowledgment information (ack signal)
The data message of LD is sent to interface driver.
More specifically, data sending request is generated, sends data sending request to identified interface driver, comprising:
The data sending request function that interface driver determined by calling provides generates data sending request, drives to identified interface
It is dynamic to send data sending request；Second hardware abstraction layer message is sent to identified interface driver, comprising: calling determines
Interface driver provide bus write function, the second hardware abstraction layer message is sent to identified interface driver.
In one embodiment, as shown in figure 3, DSP hardware level of abstraction 110 further include: LD-PD configuration module 116, LD-PD
Configuration module 116 receives parsing module 112 with message respectively and LD-PD mapping table module 115 is connect.
Message receives parsing module 112, is also used to obtain when receiving purpose logical address is hardware abstraction layer logical address
Logical address-physical address pair in data to be received is taken, by logical address-physical address to being sent to LD-PD configuration module
116.LD-PD configuration module 116 is by logical address-physical address to being added to the first address mapping table.
Wherein, address mapping table configuration message refer to it is being sent by software radio core frame, reflected for carrying out address
The hardware abstraction layer message of firing table configuration.Specifically, when message receives parsing module 112 to the hardware abstraction layer message received
Parsed, obtain receive purpose logical address it is consistent with hardware abstraction layer logical address when, that is, can determine the hardware abstraction layer
Message is destined to the message of the hardware abstraction layer.Wherein, hardware abstraction layer logical address refers to for uniquely indicating that hardware is taken out
As the address of layer, indicated with HAL_LD.When hardware abstraction layer establishes the first address mapping table, that is, record the HAL_LD for having itself
With HAL_PD (hardware abstraction layer physical address), when receiving the HAL_LD recorded in purpose logical address and the first address mapping table
When consistent, that is, it can determine that the hardware abstraction layer message is destined to the message of the hardware abstraction layer.
When it is address mapping table configuration field that parsing, which obtains the data to be received in hardware abstraction layer message, determine that this is hard
Part level of abstraction message is address mapping table configuration message, and message receives in the data to be received that parsing module 112 analytically obtains
LD-PD pairs is extracted, and LD-PD is added in the first address mapping table of hardware abstraction layer by LD-PD configuration module 116.
More specifically, LD-PD configuration module 116 for be responsible for docked with software radio software platform, software without
Line electricity software platform generates LD-PD configuration order (LD_PD_CMD) simultaneously according to the waveform components port connection scheme of advance planning
It is sent in each hardware abstraction layer, hardware abstraction layer is configured by LD-PD configuration module 116 and the LD-PD of layer is driven to map
Table, and then realize the connection between the input of different wave component, output port.The table specific as follows 2 of LD-PD configuration order format
It is shown:
2 LD-PD configuration order format of table
Further, LD-PD configuration module 116 is also connect with bus interface adaptation module 111, is used for logical address-
Physical address is to being sent to bus interface adaptation module 111；Bus interface adaptation module 111 is also used to logical address-physics
Address is to the second address mapping table for being added to interface driver layer.
The mapping table configuration function for calling driving to provide by bus interface adaptation module 111, is added to interface for LD-PD
In the second address mapping table for driving layer, enables interface driver according to the second address mapping table is inquired, determine the second hardware
The transmission purpose physical address of level of abstraction message.Wherein, mapping table configuration function is pre-defined in bus interface adaptation module 111
In, it is realized in interface driver layer, which is called by bus interface adaptation module 111, realizes the LD- in interface driver layer
The configuration of PD mapping table.
Above-mentioned DSP hardware level of abstraction 110, by bus interface adaptation module 111 by DSP hardware level of abstraction 110 and bottom
Bus driver it is completely isolated, by component interface adaptation module 113 by the waveform components of DSP hardware level of abstraction 110 and upper layer
It is completely isolated, to guarantee that 110 code of DSP hardware level of abstraction has platform independent property, enable DSP hardware level of abstraction 110
Enough to be easily applied on different hardware platforms, Universal and scalability with higher effectively increases DSP hardware
The portability of level of abstraction 110.While a large amount of repetitions, the low-quality exploitation of hardware abstraction layer are avoided, realization primary development,
The purpose that many places use greatly improves the high efficiency, stability and reliability of dsp processor.
In one embodiment, a kind of dsp processor 100 is provided, as shown in figure 4, dsp processor 100 includes: that any one is real
Apply DSP hardware level of abstraction 110, waveform components 120 and the interface driver layer 130 in example.Waveform components 120 and DSP hardware are abstract
Layer 110 connects, and DSP hardware level of abstraction 110 is connect with interface driver layer 130.
Wherein, waveform components 120 refer to the specific software module for executing a certain independent function in communication system.Specifically,
Waveform components 120 are used to receive the data to be received of the transmission of DSP hardware level of abstraction 110, and execute it to data to be received and had
The alignment processing of standby function, and data to be sent and transmission purpose logical address are sent to DSP hardware level of abstraction 110.
Interface driver layer 130 is for realizing the data communication between current processor and ppu.Specifically, interface
It drives layer 130 to be used for through interface driver, receives the first hardware abstraction layer message that ppu is sent, and by the first hardware
Level of abstraction message is sent to DSP hardware level of abstraction 110.
When interface driver uses packet-switched bus transmission mode, interface driver receives total report from a liner that ppu is sent
Text obtains receiving purpose logical address according to reception purpose physics the second address mapping table of address lookup in bus message, when
According to receive purpose logical address determine institute received bus message for current processor message to be received when, by bus message
In the first hardware abstraction layer message be sent to DSP hardware level of abstraction 110.More specifically, interface driver receives ppu
The bus message of transmission, the LD- safeguarded according to purpose physical address (PD) the Field Inquiry interface driver layer 130 in bus message
PD mapping table finds corresponding LD, confirms that this message is that local waveform components 120 prepare received data according to the LD,
The data-pushing function for calling hardware abstraction layer to provide is driven through at this time to be sent to the payload field in bus message firmly
The bus interface adaptation module 111 of part level of abstraction.
When interface driver uses shared drive transmission mode, the first hardware for receiving driving reception ppu transmission is taken out
Judge whether data write as layer message, and according to read-write mark, if writing, the first hardware abstraction layer message is sent to
DSP hardware level of abstraction 110.More specifically, receiving driving receives the first hardware abstraction layer message that ppu is sent, and root
Judge whether data write according to read-write mark, if writing, the data-pushing function for calling hardware abstraction layer to provide is hard by first
Part level of abstraction message is sent to DSP hardware level of abstraction 110.
In one embodiment, interface driver layer 130 is also used to send DSP hardware level of abstraction 110 by interface driver
Second hardware abstraction layer message, is sent to corresponding ppu.Ppu can be any one processor, including
But it is not limited to DSP, FPGA (Field Programmable Gate Array, field programmable gate array), CPU
(Central Processing Unit, central processing unit).
When interface driver uses packet-switched bus transmission mode, interface driver is according to hardware abstraction layer message and sends mesh
Physical address generate bus message, bus message is sent to and sends the corresponding processor of purpose physical address.More specifically,
Interface driver, which obtains, sends purpose logical address, obtains and sends from the LD-PD mapping table of 130 internal maintenance of interface driver layer
The corresponding transmission purpose physical address of purpose logical address, and by the purpose in the transmission purpose physical address write bus message
Physical address (PD) field, while effective load in the hardware abstraction layer message write bus message that message package module is encapsulated
Lotus (payload) field is sent bus message by packet-switched bus interface driver.
When interface driver use shared drive transmission mode, judge read-write be identified as it is writeable or readable, when read-write identify
When position is writeable, hardware abstraction layer message is sent to by interface driver sends the corresponding shared drive of purpose physical address.More
Body, the hardware abstraction layer message that message package module encapsulates is write direct shared drive address corresponding to PD by interface driver
In the middle, and by read-write flag bit it is set as readable, to inform that the interface driver of purpose processor receives hardware abstraction layer message.
Further, interface driver also has data priority processing function.When the corresponding interface of interface driver is in work
When making state, the data priority of bus message to be sent and the data priority of the currently transmitted message of interface are compared
Compared with；When the data priority of bus message to be sent is higher than the data priority of currently transmitted message, interrupt currently transmitted
The transmission of message, and bus message to be sent is sent to and sends the corresponding processor of purpose physical address；It otherwise, will be pending
The bus message sent is lined up according to high priority data rank, and when meeting transmission condition, bus message to be sent is sent
To the corresponding processor of transmission purpose physical address.
In the present embodiment, high priority data rank is to send the priority level of purpose physical address, sends purpose physical address
Priority level configured in advance according to demand.Wherein, currently transmitted message refers to the bus message that interface is being sent.To
The bus message of transmission refers to the bus message for currently carrying out sending but not yet send.Transmission condition refers to data priority
Not higher bus message is sent.
By judging whether the corresponding interface of interface driver is in running order, namely whether bus message is being sent,
If so, interface driver further judges data priority, so that determination is to arrange bus message to be sent
Team waits, or interrupts the bus message that current message is sent, preferential transmission high priority data rank is high.And it is executed by interface driver
Data priority processing, further simplifies the treatment process of hardware abstraction layer, improves the data processing effect of hardware abstraction layer
Rate and speed, have saved system resources in computation.
Above-mentioned dsp processor 100, by by driving completely isolated hardware abstraction layer to realize data with bottom bus interface
Interaction process, thus guarantee hardware abstraction layer processing have platform independent property, enable hardware abstraction layer very convenient
Ground is transplanted on different hardware platforms, avoid hardware abstraction layer it is a large amount of repeat, low-quality exploitation, realize primary development,
The purpose that many places use greatly improves the high efficiency, stability and reliability of dsp processor 100.
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
Above embodiments only express the several embodiments of the application, and the description thereof is more specific and detailed, but can not
Therefore it is construed as limiting the scope of the patent.It should be pointed out that for those of ordinary skill in the art,
Under the premise of not departing from the application design, various modifications and improvements can be made, these belong to the protection scope of the application.
Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of DSP hardware level of abstraction characterized by comprising bus interface adaptation module, message receive parsing module and
Component interface adaptation module；
The bus interface adaptation module connects with the interface driver layer and the message for including at least one interface driver respectively
Parsing module connection is received, for receiving the first hardware abstraction layer message of the interface driver transmission, first hardware is taken out
Parsing module is received as layer message is sent to the message；The first hardware abstraction layer message is the interface driver according to institute
State the message to be received that the reception purpose logical address in the first hardware abstraction layer message determines；
The message receives parsing module and connect with the component interface adaptation module, for parsing first hardware abstraction layer
Message obtains data to be received and receives purpose logical address, and the data to be received and the reception purpose logical address are sent out
It send to the component interface adaptation module；
The component interface adaptation module and the waveform components on upper layer connect, for being determined according to the reception purpose logical address
The data to be received are sent to purpose sets of waveforms by the identified waveform components port by purpose waveform components port
Part.
2. DSP hardware level of abstraction according to claim 1, which is characterized in that the component interface adaptation module is also used to
Obtain the data receiver request that the waveform components are sent, the data receiver request carries specified logical address, and by institute
It states specified logical address and is transmitted to the bus interface adaptation module；
The bus interface adaptation module is also used to the specified logical address being sent to each interface driver, so that working as
In first hardware abstraction layer message received by any interface driver, purpose logical address and the specified logic are received
When address is identical, determine that the first received hardware abstraction layer message is the message to be received of current processor.
3. DSP hardware level of abstraction according to claim 1, which is characterized in that described that the data to be received are passed through institute
The determining waveform components port is sent to purpose waveform components, comprising: when the identified waveform components port is in
When working condition, the data priority of data to be received and the waveform components port are currently received to the data priority of data
It is compared；When the data priority of the data to be received is higher than the current data priority for receiving data, interrupt
The current transmission for receiving data, and the data to be received are sent to corresponding waveform by the waveform components port
Component；When the current data priority for receiving data is higher than the data priority of the data to be received, will it is described to
It receives data to be lined up according to high priority data rank, when meeting condition of acceptance, the data to be received is passed through into the wave
Shape component ports are sent to corresponding waveform components.
4. DSP hardware level of abstraction according to claim 1, which is characterized in that further include: message send package module and
LD-PD mapping table module, the message send package module and map respectively with the component interface adaptation module, the LD-PD
Table module is connected with the bus interface adaptation module；
The component interface adaptation module is also used to obtain data to be sent and send purpose that the waveform components request is sent
Logical address, and the data to be sent and transmission purpose logical address are transmitted to the message and send package module；
The message sends package module, for inquiring the LD-PD mapping table module according to the transmission purpose logical address
In the first address mapping table module in the first address mapping table for prestoring, obtain sending purpose physical address, and will it is described to
Send data and send purpose logical address be packaged into the second hardware abstraction layer message, will the second hardware abstraction layer message with
The transmission purpose physical address is transmitted to bus interface adaptation module；
The bus interface adaptation module is also used to according to the transmission purpose physical address, and determination is described pending for sending
The second hardware abstraction layer message is sent to identified interface driver, so that the interface by the interface driver for sending data
The data to be sent are sent to the corresponding processor of the transmission purpose physical address by driving.
5. DSP hardware level of abstraction according to claim 4, which is characterized in that described by the second hardware abstraction layer report
Text is sent to identified interface driver, comprising: generates data sending request, sends the data to identified interface driver
Request is sent, when the reception interface driver responds the confirmation message of the data sending request, second hardware is taken out
As layer message is sent to identified interface driver.
6. DSP hardware level of abstraction according to claim 5, which is characterized in that the generation data sending request, to really
Fixed interface driver sends the data sending request, comprising: the data sending request that interface driver determined by calling provides
Function generates data sending request, sends the data sending request to identified interface driver.
7. DSP hardware level of abstraction according to claim 4, which is characterized in that described by the second hardware abstraction layer report
Text is sent to identified interface driver, comprising: the bus that interface driver determined by calling provides writes function, by described second
Hardware abstraction layer message is sent to identified interface driver.
8. DSP hardware level of abstraction according to claim 4, which is characterized in that further include: LD-PD configuration module, it is described
LD-PD configuration module receives parsing module with the message respectively and the LD-PD mapping table module is connect；
The message receives parsing module, is also used to when the reception purpose logical address is hardware abstraction layer logical address,
Logical address-physical address pair in data to be received is obtained, by the logical address-physical address to being sent to the LD-
PD configuration module；
The LD-PD configuration module is by the logical address-physical address to being added to first address mapping table.
9. DSP hardware level of abstraction according to claim 8, which is characterized in that the LD-PD configuration module also with it is described total
The connection of line interface adaptation module, for by the logical address-physical address to being sent to the bus interface adaptation module；
The bus interface adaptation module is also used to the logical address-physical address to being added to the interface driver layer
The second address mapping table.
10. a kind of dsp processor characterized by comprising the described in any item DSP hardware level of abstractions of claim 1 to 9, wave
Shape component and interface driver layer；The waveform components are connect with the DSP hardware level of abstraction, the DSP hardware level of abstraction and institute
State the connection of interface driver layer.
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