CN109388864B - High-efficiency signal line electro-migration analysis method for semi-customized physical design of integrated circuit - Google Patents
High-efficiency signal line electro-migration analysis method for semi-customized physical design of integrated circuit Download PDFInfo
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- CN109388864B CN109388864B CN201811112697.6A CN201811112697A CN109388864B CN 109388864 B CN109388864 B CN 109388864B CN 201811112697 A CN201811112697 A CN 201811112697A CN 109388864 B CN109388864 B CN 109388864B
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Abstract
The invention discloses a high-efficiency signal line electro-migration analysis method for semi-customized physical design of an integrated circuit, which comprises the following steps. Step S1: the parasitic parameter data is subject to targeted examination according to a flat design or a hierarchical design. Step S2: format conversion is performed on the parasitic parameter data. And step S3: and (5) arranging and generating logic information for chip design. And step S4: generating attribute information from the format-converted parasitic parameter data and logic information for chip design. The invention discloses a high-efficiency signal line electromigration analysis method of an integrated circuit semi-customized physical design, which is based on the physical and logical relation of signal lines and obtains signal line electromigration analysis data by utilizing an FIT calculation mode according to logical information, attribute information and parasitic parameter data, thereby improving the design efficiency, avoiding ineffective work, reducing the design iteration times and shortening the whole chip design period.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design automation, and particularly relates to a high-efficiency signal line electromigration analysis method for integrated circuit semi-customized physical design.
Background
As chip design scales are larger, the risk of chip failure due to fracture and melting of metal interconnection lines caused by Electromigration (EM) is larger. Neglecting their presence can cause degradation of the metal lines during the normal lifetime of the chip, and these adverse effects ultimately lead to costly field failures and serious product reliability problems.
At present, in a conventional signal line electromigration analysis method, an efficient signal line electromigration analysis process does not exist, but the efficient signal line electromigration analysis process is a technical problem which needs to be solved urgently in the current semi-customized back-end design situation.
Disclosure of Invention
The invention overcomes the defects in the prior art and provides a high-efficiency signal line electro-migration analysis method for semi-customized physical design of an integrated circuit.
The invention adopts the following technical scheme that the integrated circuit semi-customized physical design high-efficiency signal line electromigration analysis method comprises the following steps:
step S1: performing targeted inspection on the parasitic parameter data according to a flat design or a hierarchical design;
step S2: carrying out format conversion on the parasitic parameter data;
and step S3: logic information for chip design is generated through sorting;
and step S4: generating attribute information according to the parasitic parameter data subjected to format conversion and logic information for chip design;
step S5: obtaining a calculation result according to the attribute information, and reversely marking the calculation result to a corresponding signal line;
step S6: and obtaining signal line electro-migration analysis data by using an FIT calculation mode according to the logic information, the attribute information and the parasitic parameter data based on the physical and logic relations of the signal lines.
According to the above technical solution, the basic information data of the FIT calculation manner in step S6 includes current density information of the signal line and temperature information corresponding to the signal line.
According to the above technical solution, step S6 specifically includes the following steps:
step S6.1: logic unit resistance and capacitance arrangement;
step S6.2: pull-up and pull-down network generation;
step S6.3: calculating current density;
step S6.4: establishing signal network model data;
step S6.5: generating a calculation matrix point;
step S6.6: calculating power supply voltage data;
step S6.7: calculating temperature data;
step S6.8: and generating current density information of the signal wire and temperature information corresponding to the signal wire according to the steps S6.1 to S6.7.
According to the above technical solution, step S1 specifically includes the following steps:
judging the design type of the parasitic parameter data, integrating the data when the parasitic parameter data is in a module level, and directly extracting the data when the parasitic parameter data is in an independent and complete design.
According to the above technical solution, the logic information in step S3 includes function information, connection relationship information, minimum composition unit information, and enable valid information.
According to the above technical solution, the attribute information in step S4 includes transmission delay information, load information, frequency information, and signal line switching flow information of the signal line.
The invention discloses a high-efficiency signal line electromigration analysis method for semi-customized physical design of an integrated circuit, which has the advantages that logic information, attribute information and parasitic parameter data are obtained through the pertinence check of the parasitic parameter data, and signal line electromigration analysis data are obtained by utilizing an FIT calculation mode based on the physical and logic relations of signal lines and according to the logic information, the attribute information and the parasitic parameter data, so that the design efficiency can be improved, the invalid work is avoided, the design iteration times are reduced, and the whole chip design period is shortened.
Drawings
FIG. 1 is a system flow diagram of a preferred embodiment of the present invention.
Fig. 2 is a system block diagram of signal line electro-migration analysis data calculation according to a preferred embodiment of the present invention.
Detailed Description
The invention discloses a high-efficiency signal line electro-migration analysis method for semi-customized physical design of an integrated circuit, and the specific implementation mode of the invention is further described by combining with a preferred embodiment.
It is worth mentioning that those skilled in the art should note that the present patent application refers to "EM" (electro migration), which is defined as "ElectroMigration"; the present patent application relates to "FIT" (Failure In Time), which is defined as "Time lapse method".
Referring to fig. 1 and fig. 2 of the drawings, fig. 1 shows an execution flow of the integrated circuit semi-customized physical design efficient signal line electromigration analysis method, and fig. 2 shows a system structure of the integrated circuit semi-customized physical design efficient signal line electromigration analysis method.
Preferably, the method for analyzing the integrated circuit semi-customized physical design high-efficiency signal line electro-migration comprises the following steps:
step S1: carrying out targeted inspection on the parasitic parameter data according to a flat design or a hierarchical design;
step S2: carrying out format conversion on the parasitic parameter data;
and step S3: logic information for chip design is generated through sorting;
and step S4: generating attribute information according to the parasitic parameter data subjected to format conversion and logic information for chip design;
step S5: obtaining a calculation result according to the attribute information, and reversely marking the calculation result to a corresponding signal line;
step S6: and obtaining signal line electro-migration analysis data by using an FIT calculation mode according to the logic information, the attribute information and the parasitic parameter data based on the physical and logic relations of the signal lines.
The basic information data of the FIT calculation method in step S6 includes current density information of the signal line and temperature information corresponding to the signal line.
Wherein, step S6 specifically includes the following steps:
step S6.1: logic unit resistance and capacitance arrangement;
step S6.2: pull-up and pull-down network generation;
step S6.3: calculating current density;
step S6.4: establishing signal network model data;
step S6.5: generating a calculation matrix point;
step S6.6: calculating power supply voltage data;
step S6.7: calculating temperature data;
step S6.8: and generating current density information of the signal wire and temperature information corresponding to the signal wire according to the steps S6.1 to S6.7.
Wherein, step S1 specifically includes the following steps:
judging the design type of the parasitic parameter data, integrating the data when the parasitic parameter data is in a module level, and directly extracting the data when the parasitic parameter data is in an independent and complete design.
The logic information in step S3 includes function information, connection relationship information, minimum composition unit information, and enable valid information.
The attribute information in step S4 includes transmission delay information, load information, frequency information, and signal line switching flow information of the signal line.
According to the preferred embodiment, the integrated circuit semi-customized physical design high-efficiency signal line electro-migration analysis method disclosed by the patent application is specifically described as follows.
1. The data integrity is checked.
The most basic data for performing signal line electromigration analysis includes parasitic parameter information between signal lines of a chip, and the information directly determines the accuracy of the electromigration analysis. Therefore, data of parasitic parameters need to be checked. Because the design is divided into flat and hierarchical design, different data composition modes exist in different design types. Therefore, data integration is required when parasitic parameter data provided in the design is at a module level, and complete parasitic parameter information needs to be directly extracted if the design is an independent complete design.
2. Format conversion of the parasitic parameter data.
After step 1 (checking data integrity), since the data format used by the design tool for performing the electromigration analysis has its own requirement characteristics, the format of the original parasitic parameter data needs to be converted into a specific data format required by the design tool for the electromigration analysis.
3. Logical information generation
Electromigration analysis has a direct link to the logic function of the chip design itself. The electromigration analysis results of the chip under different logic functions are different. Therefore, the logic information of the chip design needs to be sorted and analyzed.
The generated logic information includes most of function information, connection relation information, minimum composition unit information, and enable valid information 4.
4. Attribute information generation
Based on the information in steps 2 and 3, the transmission delay information and the load information of the specific signal line can be calculated, and the frequency information of the chip design and the signal line switching flow information are arranged.
5. Attribute information denotation
And (4) reversely marking the actual calculation result to the corresponding signal line for final electromigration analysis based on the attribute information calculated and sorted in the step (4).
6. Signal line electromigration computation
Calculation of signal line electromigration analysis data is performed based on all the signal line information having a physical and logical correspondence provided in step 5, as shown in fig. 2.
The signal line electromigration technique requires the input of three basic data, logic information, parasitic parameter data and attribute information, which are generated by the previous steps.
In signal line electromigration computation, an important technique we call FIT (time lapse method), which requires 2 very important data: current density of the signal line and corresponding temperature information.
2 pieces of basic information data required before FIT calculation are obtained by sequentially executing 7 steps of logic unit resistor-capacitor sorting, pull-up and pull-down network generation, current density calculation, signal network model data, calculation matrix point generation, power supply voltage data calculation and temperature data calculation.
And finally calculating the electromigration analysis result of the final signal through an FIT algorithm.
It should be noted that, according to the above preferred embodiment, the efficient signal line electromigration analysis method for semi-custom physical design of an integrated circuit disclosed in the present application has the technical key points that the design efficiency is improved, and based on the advancement, integrity and maturity of the design method, a back-end design team can effectively avoid invalid work and reduce the number of design iterations, and finally shorten the whole chip design cycle. The method is suitable for back-end design projects with different design requirements in the atmosphere, and has good universality and advancement.
It will be apparent to those skilled in the art that modifications and equivalents can be made to the embodiments described above, or some features of the embodiments described above, and any modifications, equivalents, improvements, and the like, which fall within the spirit and principle of the present invention, are intended to be included within the scope of the present invention.
Claims (6)
1. A method for analyzing the electro-migration of an efficient signal line in semi-customized physical design of an integrated circuit is characterized by comprising the following steps:
step S1: performing targeted inspection on the parasitic parameter data according to a flat design or a hierarchical design;
step S2: carrying out format conversion on the parasitic parameter data;
and step S3: logic information for chip design is generated through sorting;
and step S4: generating attribute information according to the parasitic parameter data subjected to format conversion and logic information for chip design;
step S5: obtaining a calculation result according to the attribute information, and reversely marking the calculation result to a corresponding signal line;
step S6: and obtaining signal line electro-migration analysis data by using an FIT calculation mode according to the logic information, the attribute information and the parasitic parameter data based on the physical and logic relations of the signal lines.
2. The integrated circuit semi-custom physical design high-efficiency signal line electromigration analysis method according to claim 1, wherein the basic information data of the FIT calculation manner in step S6 includes current density information of the signal line and temperature information corresponding to the signal line.
3. The method for integrated circuit semi-custom physical design high efficiency signal line electromigration analysis of claim 2 wherein step S6 specifically includes the steps of:
step S6.1: logic unit resistance and capacitance arrangement;
step S6.2: pull-up and pull-down network generation;
step S6.3: calculating current density;
step S6.4: establishing signal network model data;
step S6.5: calculating matrix point generation;
step S6.6: calculating power supply voltage data;
step S6.7: calculating temperature data;
step S6.8: and generating current density information of the signal wire and temperature information corresponding to the signal wire according to the steps S6.1 to S6.7.
4. The method for analyzing electro-migration of signal lines in an integrated circuit semi-custom physical design according to claim 1, wherein step S1 specifically comprises the steps of:
judging the design type of the parasitic parameter data, integrating the data when the parasitic parameter data is in a module level, and directly extracting the data when the parasitic parameter data is in an independent and complete design.
5. The method for analyzing signal line electro-migration of integrated circuit semi-custom physical design according to claim 1, wherein the logic information in step S3 includes function information, connection relation information, minimum composition unit information and enable valid information.
6. The method according to claim 1, wherein the attribute information in step S4 includes transmission delay information, load information, frequency information and signal line switching flow information of the signal line.
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| US20150356229A1 (en) * | 2014-06-09 | 2015-12-10 | Qualcomm Incorporated | Physical cell electromigration data generation |
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