CN109387985B

CN109387985B - Display device

Info

Publication number: CN109387985B
Application number: CN201811441500.3A
Authority: CN
Inventors: 陈宏昆; 李宜锦; 张鸿光; 高毓谦; 朱瑞清; 宋立伟; 黄惠敏
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2014-03-14
Filing date: 2014-12-03
Publication date: 2022-05-17
Anticipated expiration: 2034-12-03
Also published as: CN104914596B; CN104914596A; CN109387985A

Abstract

The invention discloses a display device, comprising: a display device, comprising: a substrate having a sidewall; a data line disposed on the substrate and extending along a direction; a common electrode disposed on the substrate and having a first opening, wherein the first opening is an arc-shaped opening and the arc-shaped opening has a first width in the direction; and a pixel electrode disposed on the substrate, wherein the pixel electrode and the common electrode have an overlap and the overlap has a second width in the direction, and the first width is greater than the second width.

Description

Display device

The application is a divisional application of a Chinese invention patent application (application number: 201410723711.1, application date: 2014, 12 and 03, invention name: display device).

Technical Field

The present invention relates to a display device.

Background

With the development of digital technology, display devices have been widely used in various aspects of daily life, such as televisions, notebooks, computers, mobile phones, smart phones, and other modern information devices, and the display devices are continuously developed toward high resolution, light weight, thin and narrow frame.

In order to achieve high resolution and solve the problem of the conventional lcd that the viewing angle is too small, an In-Plane-Switching (IPS) image display device is proposed, which displays images with a wide viewing angle by controlling the alignment direction of liquid crystal molecules by applying an electric field parallel to the substrate to the liquid crystal molecules. However, the conventional high-resolution in-plane switching type image display device still has the problems of low transmittance, low contrast, color shift, and flicker.

Disclosure of Invention

To solve the above problems, the present invention provides a display device including: a substrate having a sidewall; a data line disposed on the substrate and extending along a direction; a common electrode disposed on the substrate and having a first opening, wherein the first opening is an arc-shaped opening and the arc-shaped opening has a first width in the direction; and a pixel electrode disposed on the substrate, wherein the pixel electrode and the common electrode have an overlap and the overlap has a second width in the direction, and the first width is greater than the second width.

The present invention also provides a display device including: a substrate having a sidewall; another substrate, which is arranged opposite to the substrate and is provided with a side wall; a frame glue arranged between the substrate and the other substrate; and a first spacer disposed in the sealant.

In order to make the features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic plan view of a display device according to an embodiment of the invention;

FIG. 2 is an enlarged schematic view of a portion of the switch of FIG. 1;

FIG. 3 is a schematic plan view of a display device according to another embodiment of the invention;

FIG. 4 is an enlarged schematic view of the pixel of FIG. 3 and its adjacent gate lines and data lines;

FIG. 5 is a schematic plan view of a pixel according to an embodiment of the present invention;

FIG. 6 is an enlarged view of a pixel at a switch according to another embodiment of the present invention;

FIG. 7A is a schematic cross-sectional view of the structure of FIG. 6 taken along line F-F';

FIG. 7B is a schematic cross-sectional view of the structure of FIG. 6 taken along line G-G';

FIG. 8 is an enlarged view of a pixel at a switch portion according to another embodiment of the present invention;

FIG. 9 is a schematic cross-sectional view of the structure of FIG. 8 taken along line H-H';

fig. 10 is a schematic top view of a display device according to an embodiment of the invention;

FIG. 11 is a schematic diagram of a side view of the display device of FIG. 10 from the X direction;

FIGS. 12A-12D are schematic cross-sectional views of the display device shown in FIG. 10 along the line E-E';

FIG. 13 is a schematic cross-sectional view of a display device according to another embodiment of the present invention, taken along line E-E';

fig. 14 is a schematic top view of a mother substrate of a display device, which is cut to obtain the display device shown in fig. 10 according to the present invention;

fig. 15A to 15F are enlarged schematic views of a second stable region 160B of a mother board of a display device according to an embodiment of the invention;

fig. 16 is a schematic top view of a display device according to another embodiment of the invention;

fig. 17 is a schematic top view of a display device with test lines according to an embodiment of the invention;

fig. 18 and 19 are schematic top views of display devices with test circuits according to other embodiments of the present invention;

FIG. 20A is a top view of a display device according to an embodiment of the invention;

FIG. 20B is an enlarged view of a portion of the display device of FIG. 20A;

FIG. 21 is a top view of a test pad of an embodiment of the present invention;

FIGS. 22A-22B are cross-sectional views of the test pad of FIG. 21 taken along line 3-3;

FIG. 23 is a top view of a test pad according to another embodiment of the present invention;

FIG. 24 is a top view of a test pad according to another embodiment of the present invention;

FIG. 25 is a top view of a test pad according to another embodiment of the present invention;

FIG. 26 is a top view of a test pad according to another embodiment of the present invention;

fig. 27 is a top view of a display device according to an embodiment of the invention;

FIG. 28A is a schematic cross-sectional view of the display device shown in FIG. 27 along line A-A';

fig. 28B and 28C are schematic cross-sectional views along the line a-a' of the display device according to other embodiments of the present invention;

fig. 29 is a top view of a display device according to another embodiment of the invention;

FIG. 30A is a schematic cross-sectional view of the display device shown in FIG. 29 taken along line B-B';

FIG. 30B and FIG. 30C are schematic cross-sectional views along the line B-B' of the display device according to another embodiment of the present invention;

fig. 31 is a top view of a display device according to yet another embodiment of the invention;

FIG. 32 is a cross-sectional view of the display device of FIG. 31 taken along line C-C;

fig. 33 and 34 are top views of mother boards of display devices according to other embodiments of the present invention;

FIG. 35A is a top view of an embodiment of the present invention;

FIG. 35B is a cross-sectional view taken along line 1B-1B of FIG. 35A;

FIG. 36 is a top view of another embodiment of the present invention;

FIG. 37 is a cross-sectional view of another embodiment of the present invention;

FIG. 38 is a cross-sectional view of another embodiment of the present invention;

FIG. 39 is a cross-sectional view of another embodiment of the present invention;

FIG. 40A is a top view of a display device according to an embodiment of the invention;

FIG. 40B is an enlarged view of a portion of the display device of FIG. 40A;

FIG. 40C is a schematic view of the display device of FIG. 40B without the enlarged portion;

fig. 41A is a cross-sectional view of a display device according to an embodiment of the present invention;

FIG. 41B is a top view of a display device according to an embodiment of the present invention;

FIG. 41C is a side view of a display device according to an embodiment of the invention;

FIG. 42A is a top view of a display device according to another embodiment of the invention;

FIG. 42B is a side view of a display device according to another embodiment of the invention;

fig. 43 is a top view of a display device according to another embodiment of the invention;

fig. 44 is a top view of a display device according to another embodiment of the invention;

fig. 45 is a top view of a display device according to another embodiment of the invention;

fig. 46 is a sectional view of a display device according to another embodiment of the present invention.

Description of the symbols

100 a display device;

101 a first substrate;

102 a substrate;

103 a second substrate;

104 a display area;

105 a non-display area;

106 a drive unit;

107 a gate drive circuit;

108a wiring area;

108a first line area;

108b a second line area;

108c a third circuit region;

109 a test pad;

110 lines/signal line groups;

a 110A line;

a 110B line;

110C a first block circuit;

110D second block circuit;

111 a gate signal output contact;

112 a first conductive line;

a region 113A;

a region 113B;

114 a second conductive line;

115 an external pin connection area;

116 a first conductive loop;

118 a second conductive loop;

120 frame glue;

a 120A straight section;

a 120B U shaped portion;

122a peripheral boundary;

122A first boundary;

122B second boundary;

122C a third boundary;

123 boundary;

124, presetting a cutting path;

126 a first transparent substrate;

127 the linear portion interfaces with the U-shaped portion;

128 light-shielding layer;

130a color filter layer;

a 130A color filter layer;

a 130B color filter layer;

a 130C color filter layer;

130D a first color filter layer;

130E a second color filter layer;

132 a planar layer;

134 a second transparent substrate;

136 an insulating layer;

138 a liquid crystal material;

140 partition walls;

142 a primary spacer;

a 142T top surface;

142TE edge;

142B bottom surface;

144 corner regions;

146 sliver region;

148 a first alignment layer;

150 a second alignment layer;

154 first substrate sidewall;

156 a first cut crack surface;

157 a first intermediate cracked surface;

158 a first fracture surface;

160 cutting the stable area;

160A first stable area;

160B second stable region;

160C third stable region;

a 161 spacer;

162 a planar layer;

163 short side;

165 long side;

164 second substrate sidewalls;

166 a second cut crack surface;

167 a second medium crack surface;

168 second fracture surface;

170 testing the circuit;

172 a first contact pad;

174 a second contact pad;

176 a first circuit;

178 a second circuit;

180 circuit board;

1B-1B line segment;

1B region;

201 display device motherboard;

202 a first conductive block;

204 a second conductive block;

205 a first through-hole;

206a dielectric layer;

206A dielectric layer;

206B dielectric layer;

207 a second through hole;

208 a protective layer;

209 a third through hole;

210 a conductive layer;

211a connection layer;

211A fourth through hole;

212 a planar layer;

213 a fifth through hole;

215 a liquid crystal layer;

3-3 line segments;

300a first region;

a 300A block;

300B blocks;

300Aa sub-block;

300Ab subblock;

302a second zone;

a 302A block;

a 302B block;

304 primary gap;

306 a first gap;

308 intra-block gaps;

310 intra-line gaps;

312 a second gap;

320 gate lines;

322 data lines;

324 a switch;

326 a grid electrode;

328 an active layer;

330 a source electrode;

332a drain electrode;

332A connection part;

332B a slope part;

an extension 332C;

334 pixels;

336 a first transparent electrode;

338a second transparent electrode;

338A fingers;

338B connecting part;

340 a first opening;

342 a second opening;

344 third opening;

346 a gate insulating layer;

348 a first protective layer;

350 a flat layer;

352 a second protective layer;

354 undercut;

356 intersection point;

358 undercut;

400 pixels;

402 sub-pixels;

402R sub-pixel columns;

402R1 subpixel columns;

402R2 subpixel columns;

402C sub-pixel columns;

404 a matrix part;

404R matrix section columns;

404C matrix section column;

406 an enlarged portion;

406A main enlargement;

406AE edge;

406B times enlargement;

406BE edge;

408, meeting;

410 spacers;

410B bottom surface;

410BE edge;

410T top surface;

412 a roughened region;

412E edge;

414 rubbing direction;

416 sub-pixel regions;

a1 contact area;

A-A' tangent line;

B-B' tangent line;

C-C' tangent line;

the distance D1;

the distance D2;

the distance D3;

the distance D4;

the distance D5;

the distance D6;

the distance D7;

the distance D8;

the distance D9;

the distance D10;

the distance D11;

the distance D12;

the distance D13;

the distance D14;

the distance D15;

the distance D16;

the distance D17;

da distance;

the Dc distance;

a De distance;

the Df distance;

the Dg distance;

the Dh distance;

E-E' tangent line;

F-F' tangent line;

G-G' tangent line;

g1 first gap;

g2 second gap;

H-H' tangent;

height H1;

height H2;

height H3;

height H4;

height H5;

the H6 distance;

the H7 distance;

height H8;

the H9 distance;

the H10 distance;

an M conductive layer;

m1 first conductive layer;

m2 second conductive layer;

l length;

l1 length of first conducting block;

length of the second conductive block of L2;

length of La

Lx length;

the length of Ly;

q a fourth direction;

s1 first side;

a second side of S2;

s3 interfacing;

s4 first side;

a second side of S5;

t1 thickness;

t2 thickness;

t3 thickness;

t4 thickness;

t01 thickness;

t11 thickness;

t12 thickness;

t13 thickness;

t02 thickness;

t21 thickness;

t22 thickness;

t23 thickness;

a V1 pilot hole;

a V2 guide hole;

a V3 pilot hole;

a W0 width;

w0' width;

w1 line width of the first conductive line;

a W11 width;

the line width of the W2 second conductive line;

w3 width of overlap of the first and second conductive lines;

a W4 width;

a W5 width;

a W6 width;

a W7 width;

a W8 width;

a W9 width;

wa width;

wb width;

wc width;

x a first direction;

a Y second direction;

a Z third direction;

theta 1a first included angle;

theta 2a second included angle;

theta 3a third angle;

θ 4a fourth angle;

theta 5 included angle; and

and theta 6.

Detailed Description

The display device of the present invention will be described in detail below. It is to be understood that the following description provides many different embodiments, or examples, for implementing different aspects of the invention. The specific components and arrangements described below are simply illustrative of the present invention. These are, of course, merely examples and are not intended to be limiting. Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely for simplicity and clarity of describing the present invention, and are not intended to represent any interrelationships between the different embodiments and/or structures discussed. Furthermore, when a first material layer is located on or above a second material layer, the first material layer and the second material layer are in direct contact. Alternatively, one or more further layers of material may be provided, in which case there may not be direct contact between the first and second layers of material.

It is to be understood that the components specifically described and illustrated may exist in various forms well known to those skilled in the art. Further, when a layer is "on" another layer or a substrate, it may mean "directly on" the other layer or the substrate, or that the layer is on the other layer or the substrate, or that the other layer is interposed between the other layer and the substrate.

And in the drawings, the shape or thickness of the embodiments may be exaggerated for simplicity or convenience. Moreover, although the invention has been described in connection with specific embodiments thereof, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Moreover, the use of ordinal numbers such as "first," "second," "third," etc., in the specification and in the claims to modify a component of a request does not by itself connote any preceding ordinal number of the request component, nor does it denote the order of a certain request component or sequence of another request component or method of manufacture, but are used merely to distinguish one request component having a certain name from another request component having a same name.

The display device according to the embodiment of the invention can improve the photo current leakage phenomenon and increase the performance of the display device by designing the relative position of the gate and the active layer and introducing the drain with a specific structure. In addition, the display device can be a Fringe Field Switching (FFS) image display device, which includes a transparent electrode having at least two fingers, and the design of the number of the fingers, the width of the fingers, and the distance between any two adjacent fingers can improve the light transmittance and contrast of the display device, and avoid the occurrence of flicker and color shift. Furthermore, the display device according to the embodiment of the invention can increase the contrast ratio and the aperture ratio of the display device by designing the sizes and the relative positions of the opening in the protective layer, the opening in the planarization layer, and the opening in the transparent electrode.

Fig. 1 is a schematic plan view of a display device 100 according to an embodiment of the invention, in which only some components are shown and other components (such as alignment layers) are omitted. The display device 100 includes a plurality of gate lines 320 and a plurality of data lines 322 disposed on a substrate 102, wherein each gate line 320 substantially extends along a first direction X, and the gate lines 320 have a substantially main extending direction, although not linear, extending along the first direction; each data line 322 substantially extends along a second direction Y, the data lines 322 are not straight but substantially extend along the second direction Y, and an included angle between the data lines and the second direction Y is between 0 and 10 degrees. In one embodiment, the first direction X is substantially perpendicular to the second direction Y, but in other embodiments, the first direction X need not be perpendicular to the second direction Y. The display device 100 also includes a plurality of switches 324, and each Thin Film Transistor (TFT) switch 324 is located at an intersection of the gate line 320 and the data line 322. To simplify the illustration and to illustrate the relative positions of the components of the display device 100, fig. 1 shows only the configuration of the gate lines 320, the data lines 322, and the switches 324.

Fig. 2 is an enlarged schematic view of the switch 324 of the display device 100 shown in fig. 1. The switch 324 includes a gate 326, an active layer 328, a source 330, and a drain 332. The gate 326 is connected to the gate line 320, and the source 330 is connected to the data line 322. Here, to simplify the illustration and to explain the relative positions of the components of the switch 324 of the display device 100, fig. 2 only shows the arrangement of the gate 326, the active layer 328, the source 330, the drain 332, the gate line 320, and the data line 322.

Still referring to fig. 2, the active layer 328 is disposed on the gate 326 and at least partially overlaps the gate 326. The gate 326 is separated from the active layer 328 by an insulating layer (not shown). The source 330 and the drain 332 are formed on the active layer 328 and are respectively connected to the active layer 328. It is noted that the distance De between the edge of the gate 326 and the edge of the active layer 328 may be 1.2 to 3 μm. In other words, the projection of the gate 326 to the horizontal plane overlaps with the projection of the active layer 328 to the horizontal plane, the projection of the gate 326 is larger than the projection of the active layer 328, and the distance De from the projection edge of the gate 326 to the projection of the active layer 328 may be 1.2 to 3 μm. The horizontal plane may be, for example, a surface of the substrate 102. Therefore, not only the active layer 328 can be prevented from exceeding the gate 326 due to the exposure displacement error, but also the photo current leakage (photo current leakage) phenomenon can be improved, and the performance of the display device can be increased. In addition, according to other embodiments of the present invention, the minimum horizontal distance De from all edges of the projection of the gate 326 to the edges of the projection of the active layer 328 may be between 1.2 μm and 3 μm.

In order to increase the pixel aperture area of the display and ensure the pixel charging capability, according to an embodiment of the present invention, the length Lx of the projection of the active layer 328 to the horizontal plane along the first direction X may be 6-11 μm, and the length Ly of the projection of the active layer 328 to the horizontal plane along the second direction Y may be 3-7 μm. In addition, the area of the projection of the active layer 328 to the horizontal plane may be 18 to 77 μm²。

With continued reference to fig. 2, the drain electrode 332 may be formed by a connecting portion 332A, an inclined portion 332B, and an extending portion 332C, wherein the inclined portion 332B is located between the connecting portion 332A and the extending portion 332C, and at least a portion of the inclined portion 332B overlaps the gate electrode 326, thereby ensuring the device integrity of the source electrode 330 and the drain electrode 332. A projection of one side of the inclined portion 332B to a horizontal plane is defined as the third direction Z, and the inclined portion 332B extends substantially toward the third direction Z. Wherein, an included angle θ 5 between the third direction Z and the first direction X is greater than 0 degree and less than 90 degrees.

According to an embodiment of the present invention, the gate line 320 and the gate electrode 326 may be formed of the same material in the same step, and the data line 322, the source electrode 330, and the drain electrode 332 may be formed of the same material in the same step. The gate line 320 and the data line 322 may be made of the same material or different materials, such as a single layer or multiple layers of metal conductive material (e.g., aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), or alloys thereof), metal compound conductive material, metal alloys (e.g., aluminum (Al) -containing alloy, copper (Cu) -containing alloy, molybdenum (Mo) -containing alloy, titanium (Ti) -containing alloy, platinum (Pt) -containing alloy, iridium (Ir) -containing alloy, nickel (Ni) -containing alloy, chromium (Cr) -containing alloy, silver (Ag) -containing alloy, gold (Au) -containing alloy, tungsten (W) -containing alloy, magnesium (Mg) -containing alloy, or combinations thereof). In addition, the gate line 320 is separated from the data line 322 by an insulating layer. The insulating layer may be made of an organic insulating material (photosensitive resin) or an inorganic insulating material (silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or a combination thereof). The active layer 328 may be an amorphous silicon, polysilicon, or metal oxide semiconductor material, and may be further doped with any suitable dopant.

Fig. 3 is a schematic plan view of a display device 100 according to an embodiment of the invention. The plurality of gate lines 320 extending in the first direction X and the plurality of data lines 322 extending in the second direction Y form a plurality of pixels 334, and each pixel 334 is connected to its corresponding switch 324. Each pixel 334 has a first transparent electrode 336 and a second transparent electrode 338. For simplicity of illustration and description of the relative positions of the components of the display device 100, fig. 3 only shows the circuit configurations (e.g., the gate lines 320, the data lines 322, the first transparent electrode 336, the second transparent electrode 338, and the switches 324). The first transparent electrode 336 is disposed on the gate line 320, the data line 322, and the switch 324, wherein the first transparent electrode 336 is separated from the data line 322 by a first passivation layer (not shown) and a planarization layer (not shown). The second transparent electrode 338 is disposed on the first transparent electrode 336 and separated from the first transparent electrode 336 by a second passivation layer (not shown). An alignment layer (not shown) is disposed on the second transparent electrode 338.

Fig. 4 is an enlarged schematic view of a pixel 334, an adjacent gate line 320 and a data line 322 of the display device 100 shown in fig. 3. To simplify the illustration and to illustrate the relative positions of the components of the display device 100, fig. 4 only shows the circuit configurations (e.g., the gate lines 320, the data lines 322, the first transparent electrode 336, the second transparent electrode 338, and the switches 324). The first transparent electrode 336 of the pixel 334 is used as a common electrode and has a first opening 340 exposing the extension portion 332C of the drain 332 and a portion of the slope portion 332B, and the second transparent electrode 338 of the pixel 334 is used as a pixel electrode and can be electrically connected to the drain 332 through the first opening 340. According to an embodiment of the present invention, to ensure the display device 100 has higher resolution and corresponding optical performance, the length La of the pixel 334 (i.e. from one side of the gate line 330 to the next side of the next gate line 330) may be 40 to 70 μmThe width Wa of the pixel 334 (i.e., from one side of the data line 332 to the next side of the next data line 332) may be 14 to 23 μm, and the ratio (La/Wa) of the length La of the pixel 334 to the width Wa of the pixel 334 may be 2.8 to 3.2. In addition, the area of the pixel 334 can be 600 to 1600 μm²。

In addition, the light transmittance and contrast of the display device 100 are improved, and the flicker is avoided. The second transparent electrode 338 can have two fingers 338A (e.g., as shown in fig. 4, the second transparent electrode 338 has two fingers 338A), and a connection portion 338B. The fingers 338A extend substantially parallel to the data line 322, and the connecting portion 338B connects the fingers 338A. The connecting portion 338B overlaps and is electrically connected to the drain 332, and in fig. 4, the connecting portion 338B overlaps and is electrically connected to the extending portion 332C of the drain 332 and the inclined portion 332B. In order to achieve the best transmittance of the device 100 and further avoid the color shift of the display device 100, the width Wb of the fingers 338A (i.e., the minimum horizontal distance between two sides of the fingers 338A substantially parallel to the second direction Y) may be 2.25 to 2.75 μm, and the distance Df between any two adjacent fingers 338A in the pixel 334 (i.e., the minimum horizontal distance between any two adjacent fingers 338A) may be 2.9 to 4.5 μm. Furthermore, when the sum (Dg + Wc) of the distance Dg between the finger portion 338A of the pixel 334 and the data line 322 (i.e., the minimum horizontal distance between the finger portion 338A of the pixel 334 and the data line 322 of the adjacent pixel 334) and the width Wc of the data line is 7.6 to 9.0 μm, and/or the distance Dh between the finger portions 338A of the second transparent electrodes 338 of any two adjacent pixels 334 (i.e., the minimum horizontal distance between the finger portions 338A of any two adjacent pixels 334, please refer to fig. 3) is 9.5 to 12 μm, the optical performance and the color shift of the display device 100 can be further improved.

On the other hand, referring to fig. 5, an enlarged schematic view of a pixel 334 of the display device 100 according to an embodiment of the invention is shown. To simplify the illustration and to illustrate the relative positions of the components of the display device 100, fig. 5 only shows the circuit configurations (e.g., the gate lines 320, the data lines 322, the first transparent electrode 336, the second transparent electrode 338, and the switches 324). The second transparent electrode 338 of the pixel 334 may have two fingers 338A as shown in fig. 4, or may have more than two fingers 338A (e.g., the second transparent electrode 338 of the pixel 334 shown in fig. 5 has three fingers 338A and is connected by a connecting portion).

Referring to table 1, the results of measuring the transmittance, contrast, flicker level, and color shift of the pixel 334 with two or three fingers 338A, with different finger 338A widths Wb, and with different distances Df between any two adjacent fingers 338A are shown.

TABLE 1

According TO an embodiment of the present invention, the first transparent electrode 336 and the second transparent electrode 338 may be transparent conductive materials, such as Indium Tin Oxide (ITO) Tin Oxide (TO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Antimony Tin Oxide (ATO), Antimony Zinc Oxide (AZO), combinations thereof, or other suitable transparent conductive oxide materials with high corrosion resistance.

Fig. 6 is an enlarged schematic view of a pixel 334 of the switch 324 according to another example of the present invention. In addition, FIG. 7A is a schematic diagram showing a cross-sectional structure of the structure shown in FIG. 6 along a line F-F ', and FIG. 7B is a schematic diagram showing a cross-sectional structure of the structure shown in FIG. 6 along a line G-G'.

Referring to fig. 6, 7A and 7B, the second transparent electrode 338 is disposed on the first transparent electrode 336 and separated from the first transparent electrode 336 by a second passivation layer 352; in addition, the first transparent electrode 336 is disposed on a planarization layer 350, and the planarization layer 350 is disposed on a first passivation layer 348, such that the drain electrode 332 is separated from the first transparent electrode 336 by the first passivation layer 348 and the planarization layer 350. The first opening 340 is disposed in the first transparent electrode 336 to expose the planarization layer 350, and a second opening 342 and a third opening 344 are disposed in the planarization layer 350 and the first passivation layer 348, respectively, to expose a portion of the surface of the drain electrode 332, in this embodiment, to expose at least a portion of the upper surface of the extension portion 332C of the drain electrode 332; in other embodiments, a portion of the upper surface of the extension portion 332C and the inclined portion 332B of the drain electrode 332 may be exposed.

It is noted that, in order to increase the contrast ratio and the aperture ratio of the display device according to the present invention, the maximum width of the first opening 340 (i.e. the maximum horizontal distance between any two points on the edge of the first opening 340) may be 4 to 10.5 μm, the maximum width of the second opening 342 (i.e. the maximum horizontal distance between any two points on the edge of the second opening 342) may be 3.7 to 7.5 μm, and the maximum width of the third opening 344 (i.e. the maximum horizontal distance between any two points on the edge of the third opening 344) may be 2.5 to 4.5 μm, and furthermore, the maximum width of the first opening 340 is greater than the maximum width of the second opening 342, and the maximum width of the second opening 342 is greater than the maximum width of the third opening 344.

According to the embodiment of the invention, when the maximum widths of the first opening, the second opening and the third opening of the display device are designed according to the relationship, the widths of the first opening and the second opening in the first direction X can be maintained by reducing the widths of the first opening and the second opening in the second direction Y, so that the second transparent electrode filled in the first opening and the second opening in the cross-sectional structure in the first direction X can be ensured to be electrically connected with the drain electrode. Therefore, the horizontal projection of the first opening and the second opening of the display device of the present invention is more like rectangular, elliptical, or a combination thereof, and the horizontal projection of the third opening is more like square, circular, or a combination thereof. According to other embodiments of the present invention, the first opening, the second opening, and the third opening may have other shapes.

For example, according to an embodiment of the present invention, the first opening 340 and the second opening 342 may have longer widths in the first direction X on the drain 332 and relatively shorter widths in the second direction Y, as shown in fig. 6. When the second transparent electrode 338 is filled into the second opening 342, referring to fig. 7A (showing a cross-sectional structure of the structure along the tangent line F-F' (or the first direction X) shown in fig. 6), since the first opening 340 and the second opening 342 have a relatively large width in the first direction X on the drain 332, the first protection layer 348 does not have an undercut (undercut) phenomenon of the drain 332 when the third opening 344 is formed by patterning the first protection layer 348, so that the gate insulation layer 346 under the first protection layer 348 is removed. Therefore, the second transparent electrode 338 filling the first opening 340, the second opening 342, and the third opening 344 can be electrically connected to the drain 332 in the first direction X.

In addition, referring to fig. 7B (showing a schematic cross-sectional view of the structure along the tangent line G-G' (or the second direction Y direction) in fig. 6, the first opening 340 and the second opening 342 have a relatively shorter width in the second direction Y direction on the drain 332 compared to the first direction X direction, therefore, as can be seen from fig. 7B, when the third opening 344 is formed by patterning the first protection layer 348, an undercut (undercut) 354 is generated around the drain 332 along the second direction Y direction by the first protection layer 348, so that a portion of the gate insulation layer 346 under the first protection layer 348 is removed, the gate insulation layer 346 is between the active layer 328 and the gate 326, and is also between the source 332 and the gate 326, and thus, when the second transparent electrode 338 is filled into the first opening 340, the second opening 342, and the third opening 344, the second transparent electrode 338 is a discontinuous layer in the second direction Y direction due to the recessed gate insulating layer 346 beside the drain electrode 332, which causes a gap between the second transparent electrode 338 and the drain electrode 332 in the second direction Y direction. In this embodiment, although the second transparent electrode 338 is a discontinuous layer in the second direction Y due to the gap, the second transparent electrode 338 can still be electrically connected to the drain electrode 332 in the first direction X, as shown in fig. 7A.

According to the embodiment of the invention, the gate insulating layer 346 may be disposed under the drain and on a substrate 102, or disposed under the drainDisposed between the gate electrode (or gate line) and the active layer as a gate insulating layer. The gate insulating layer 346 may be made of an organic insulating material (photosensitive resin) or an inorganic insulating material (silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or a combination thereof). The gate insulation layer 346 is, for example, a silicon nitride layer. The first protection layer 348 and the second protection layer 352 may be made of the same material or different materials, such as an organic insulating material (photosensitive resin) or an inorganic insulating material (silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or a combination thereof). The material of the planarization layer 350 may be a film with insulating property, such as dielectric material or photosensitive resin. According to the embodiment of the present invention, the thicknesses of the gate insulating layer 346, the first passivation layer 348, the planarization layer 350 and the second passivation layer 352 are not particularly limited, and can be adjusted according to the actual requirements. In addition, in order to avoid the display device from generating image flicker, image sticking, etc., according to another embodiment of the present invention, the thickness of the second passivation layer 352 may be 900 to 900

The specific thickness of the second passivation layer 352 can also increase the capacitance between the first transparent electrode 336 and the second transparent electrode 338.

According to another embodiment of the invention, in order to increase the contrast ratio and the aperture ratio of the display device 100 according to the invention, the horizontal projection of the second opening 342 and the horizontal projection of the third opening 344 may partially overlap (i.e. at least a portion of the horizontal projection of the third opening 344 does not overlap with the horizontal projection of the second opening 342), please refer to fig. 8. In other words, the third opening 344 and the opening center of the second opening 342 have an offset distance, and the edge of the horizontal projection of the second opening 342 and the edge of the horizontal projection of the third opening 344 have at least two intersection points 356, wherein a line connecting the intersection points 356 has an extending direction Q, and an included angle θ 6 may be formed between the extending direction Q and the first direction X, wherein the included angle θ 6 is greater than 0 degree and smaller than 90 degrees. Fig. 9 shows a schematic cross-sectional view of the structure shown in fig. 8 along the line H-H'. Referring to fig. 9, when the contrast ratio and the aperture ratio of the display device are increased by using the above design, since the horizontal projection of the second opening 342 and the horizontal projection of the third opening 344 do not completely overlap, the first protection layer 348 is designed to be retracted on one side of the cross section along the tangent line H-H' when the first protection layer 348 is patterned. Although, the first passivation layer 348 and the planarization layer 350 form an undercut 358, such that the second transparent electrode 338 formed thereon has a gap at one side of the cross-sectional structure along the cutting line H-H', such that the second transparent electrode 338 cannot form a continuous film at the side region; however, the second transparent electrode 338 is electrically connected to the drain electrode 332 at the other side of the H-H' cross section, and the second transparent electrode 338 at the other side region is a continuous layer.

In summary, the invention can improve the photo current leakage (photo current leakage) phenomenon by designing the relative position of the gate and the active layer and introducing the drain with a specific structure, thereby increasing the performance of the high-resolution display device. In addition, the display device can be a Fringe Field Switching (FFS) image display device, which includes a transparent electrode having at least two fingers, and the design of the number of the fingers, the width of the fingers, and the distance between any two adjacent fingers can improve the light transmittance and contrast of the display device, and avoid the occurrence of flicker and color shift. Furthermore, the display device according to the embodiment of the invention can increase the contrast ratio and the aperture ratio of the display device by designing the sizes and the relative positions of the opening in the protective layer, the opening in the planarization layer, and the opening in the transparent electrode.

According to the display device provided by the embodiment of the invention, the supporting effect required during cutting can be increased by arranging the spacer in the cutting stable region. Therefore, specific cracks may be generated on the sidewall of the substrate after cutting, resulting in preferable cutting crack performance and reducing the possibility of substrate breakage. Therefore, the yield of the display device can be greatly improved.

In addition, according to the embodiment of the present invention, the display device of the present invention may further include a test line disposed along the predetermined cutting line. Therefore, after the cutting manufacturing process is carried out, whether the display device has the phenomenon of cutting line deviation can be known by using the test circuit.

Fig. 10 is a schematic top view of a display device 100 according to an embodiment of the invention. The display device 100 includes a first substrate 101 and a second substrate 103, wherein the first substrate 101 and the second substrate 103 are disposed opposite to each other and fixed by a sealant 120, and the first substrate 101 has a display region 104 thereon, and a cutting stabilizing region 160 is disposed on the second substrate 103 and corresponding to an area outside the display region 104 on the first substrate 101, and is adjacent to a peripheral boundary 122 (including a first boundary 122A, a second boundary 122B, and a third boundary 122C) overlapped with the first substrate 101 and the second substrate 103. In addition, a boundary 123 is formed between the area of the first substrate 101 covered by the second substrate 103 and the area of the first substrate 101 not covered by the second substrate 103, the sealant 120 is disposed between the first substrate 101 and the second substrate 103 along the first boundary 122A, the second boundary 122B, the third boundary 122C, and the boundary 123, and the sealant 120 is disposed outside the display region 104.

The display device 100 may be a liquid crystal display (e.g., a thin film transistor liquid crystal display) or an organic electroluminescent device (e.g., an active full color organic electroluminescent device). The display area 104 has a plurality of pixels (not shown). The first substrate 101 and the second substrate 103 may be made of quartz, glass, silicon, metal, plastic, or ceramic material. The sealant 120 can be a resin.

According to an embodiment of the present invention, the cutting stable region 160 has a plurality of spacers (spacers) 161 disposed therein, and the sealant 120 at least covers a portion of the spacers 161 (e.g., 5 spacers in the sealant and 5 spacers out of the sealant). In one embodiment, the sealant completely covers the spacers (10 spacers are in the sealant). However, in other embodiments, at least a portion of the spacers 161 is not covered by the sealant and exposes the adjacent liquid crystal layer (e.g., 5 spacers are completely inside the sealant, and each of the remaining 5 spacers has a portion inside the sealant and outside the sealant). The cutting stable region 160 can include a first stable region 160A, a second stable region 160B, and a third stable region 160C, respectively adjacent to the first boundary 122A, the second boundary 122B, and the third boundary 122C. It is noted that, since the interface 123 is generally disposed with a plurality of traces (not shown) electrically connecting the display region 104 and a driving unit (not shown), which may be an IC, the cutting stable region 160 is not disposed on the second substrate 103 at the interface 123 side. In other words, the scribe stabilizing area 160 is not adjacent to the boundary 123. In addition, the cutting stable region 160 is not directly contacted with the four corners of the second substrate 103, and any two of the first stable region 160A, the second stable region 160B, and the third stable region 160C are not contacted with each other, so as to conveniently dispose alignment marks (not shown) for cutting. The material of the spacer (spacer)161 may include a photoresist, such as a positive photoresist or a negative photoresist. In an embodiment, the photolithography process includes a photoresist patterning process, and the photoresist patterning process further includes a photoresist coating process, a soft baking process, a photomask alignment process, an exposure pattern process, a post-exposure baking process (post-exposure baking process), a photoresist developing process, and a hard baking process.

According to an embodiment of the present invention, the width of the cutting stabilizing zone may be between 50 μm and 150 μm, and a percentage value of the width W0 'of the cutting stabilizing zone to the width W11 of the sealant may be between 6% and 50% (6% ≦ W0'/W11 ≦ 50%). Referring to fig. 10, the portion of the cut stabilizing region 160 where the spacer 161 is not disposed can be filled with the sealant 120.

Referring to fig. 11, a side view of the display device 100 of fig. 10 from the first direction X is shown. According to the embodiment of the invention, the sidewall 154 of the first substrate 101 obtained after cutting has a first cutting crack surface 156, a first intermediate crack surface 157 and a first fracture surface 158, wherein the first intermediate crack surface 157 is between the first cutting crack surface 156 and the first fracture surface 158. The first fracture surface 156 is a cut fracture surface generated by a cutter wheel for cutting, the first intermediate fracture surface 157 is an extended fracture surface generated by cutter wheel pressure after cutting, and the first fracture surface 158 is a peeled fracture surface generated by external pressure peeling. In one embodiment of the present invention, if the first intermediate crack surface 157 has a greater propagation of the cutting cracks, the sidewall 154 has only the first cutting crack surface 156 and the first intermediate crack surface 157, and there is no first fracture surface 158. Wherein the roughness of the first cut crack surface 156, the roughness of the first intermediate cracks 157, and the roughness of the first fracture surface 158 are different from each other.

On the other hand, the sidewall 164 of the second substrate 103 may have a second cut crack surface 166, a second intermediate crack surface 167, and a second fracture surface 168, wherein the second intermediate crack surface 167 is between the second cut crack surface 166 and the second fracture surface 168. The second fracture surface 166 is a fracture surface of a cut crack generated by a cutter wheel for cutting, the second intermediate fracture surface 167 is an extended fracture surface generated by a cutter wheel pressure after cutting, and the second fracture surface 168 is a peeled fracture surface generated by external pressure peeling. In one embodiment of the present invention, if the second median crack surface 167 has a greater cut crack propagation, the sidewall 164 has only the second cut crack surface 166 and the second median crack surface 167, and there is no second fracture surface 168. Wherein the roughness of the first cut crack surface 166, the roughness of the first intermediate cracks 167, and the roughness of the first fracture surface 168 are different from each other.

Referring to fig. 12A, since the display device 100 of the present invention is provided with the cutting stabilizing region 160 to increase the supporting effect required during cutting, the ratio of the sum of the thickness T11 of the first cutting crack surface 156 and the thickness T12 of the first intermediate crack surface 157 to the thickness T01 of the sidewall 154 of the first substrate 101 may be between 0.3 and 1 (0.3 ≦ T11+ T12)/T01 ≦ 1), for example: 0.5-1, or 0.7-1; the ratio of the sum of the thickness T21 of the second cut crack surface 166 and the thickness T22 of the second intermediate crack surface 167 to the thickness T02 of the sidewall 164 of the second substrate 103 may be between 0.3 and 1 (0.3 ≦ T21+ T22)/T02 ≦ 1), for example: between 0.5 and 1, or between 0.7 and 1. Therefore, the optimal cutting and cracking performance is realized, the substrate breaking probability is reduced, and the yield of the display device is greatly improved. In addition, the first fracture surface 158 may have a thickness T13, and the second fracture surface 168 may have a thickness T23.

Referring to fig. 12A, a cross-sectional view of the display device 100 along a cut line E-E' in fig. 10 is shown. A first included angle θ 1 may be formed between the first cutting crack surface 156 and the first intermediate crack surface 157, wherein the first included angle θ 1 may be greater than 90 degrees and less than 270 degrees; a second included angle θ 2 may be formed between the second cut crack surface 166 and the second median crack surface 167, wherein the second included angle θ 2 may be greater than 90 degrees and less than 270 degrees; a third included angle θ 3 may be formed between the first intermediate crack surface 157 and the first fracture surface 158, wherein the third included angle θ 3 may be greater than 90 degrees and less than 270 degrees; and, a fourth included angle θ 4 may be formed between the second median crack surface 167 and the second fracture surface 168, wherein the fourth included angle θ 4 may be greater than 90 degrees and less than 270 degrees.

Referring again to fig. 12A, it should be understood that any desired components may be disposed on the first substrate 101 and the second substrate 103 as desired, and a liquid crystal layer 215 is disposed between the first substrate 101 and the second substrate 103. For example, the first substrate 101 may be an array substrate, and the second substrate 103 may be a filter substrate. In the cutting stable region 160 (e.g., in the third stable region 160C), at least one spacer 161 has a distance D9 (i.e., the shortest distance between the spacer 161 and the sidewall 164 of the first substrate 103) from the sidewall 164 of the second substrate 103, wherein the distance D9 is between 0 μm and 200 μm. On the other hand, at least one spacer 161 may have a distance D10 (i.e., the shortest distance between the spacer 161 and the sidewall 154 of the first substrate 101) from the sidewall 154 of the first substrate 101, and the distance D10 is greater than the distance D9.

Referring to fig. 10 and 12A, the plurality of spacers 161 may occupy between 1% and 5% of the area of the scribe line 160. Here, the area of the plurality of spacers 161 occupying the cutting stable region 160 is the sum of the upper surface area a1 of each spacer 161, and in this embodiment, the upper surface of the spacer 161 is closer to the first substrate 101. Referring to fig. 12B, in other embodiments, the spacer 161 may also be disposed on the first substrate 101, i.e., the upper surface of the spacer 161 is closer to the second substrate 103. According to an embodiment of the present invention, the plurality of spacers 161 may have the same or different upper surface areas a 1. In addition, according to some embodiments of the present invention, the spacers 161 in the cutting stabilizing zone 160 can also be disposed exactly on the predetermined cutting lines, so that a portion of the spacers 161 is remained, as shown in fig. 12C. In addition, according to another embodiment of the present invention, the spacers 161 can also be exposed outside the sealant 120, as shown in fig. 12D.

Referring to fig. 13, according to another embodiment of the present invention, a planarization layer 162 can be disposed on the first substrate 101 and located in the cutting stable region 160, wherein the spacer 161 is not disposed in the cutting stable region 160, and a portion of the planarization layer 162 is filled with the sealant 120. The spacers 161 are disposed between the planarization layer 162 and the second substrate 103. According to some embodiments of the present invention, the planarization layer 162 can be a patterned film layer or have trenches, such that at least a portion of the sealant 120 is separated from the first substrate 101 by the planarization layer 162, and at least a portion of the second substrate 103 is separated from the planarization layer 162 by the spacers 161. The planarization layer 162 is a film with insulating properties, and may be a dielectric material or a photosensitive resin, for example.

Fig. 14 is a schematic top view of a display device motherboard 201, wherein the display device 100 shown in fig. 10 can be obtained by performing a cutting process on the display device motherboard 201. The cutting process can be, for example, a single or multiple blade cutting process, or a cutting wheel knife cutting process. As shown in fig. 14, the scribe stabilizing area 160 (including the first stabilizing area 160A, the second stabilizing area 160B, and the third stabilizing area 160C) of the display mother board 201 is disposed along a first predetermined scribe line 124A and a second predetermined scribe line 124B. In an embodiment of the present invention, the second predetermined scribe line 124B may be an axis of symmetry with respect to the scribe stability region 160, i.e., the areas of the scribe stability region 160 separated by the second predetermined scribe line 124B are equal and symmetrical to each other. According to other embodiments of the present invention, the predetermined scribe line 124B of the second substrate may also be asymmetric with respect to the scribe stabilizing area 160.

According to an embodiment of the present invention, the surface of the plurality of spacers 161 in the cutting stable region 160, which is in contact with the first substrate 101 (or the second substrate), may have a circular shape, an elliptical shape, a square shape, a rectangular shape, or a combination thereof. Fig. 15A to 15F are enlarged schematic views of the second stable region 160B of the mother board 201 of the display device according to the embodiment of the invention. As shown in fig. 15A, the plurality of spacers 161 may be disposed in the cutting stable region in an aligned array. In addition, the plurality of spacers 161 may also be disposed in the cutting stable region in a staggered array, as shown in fig. 15B. According to another embodiment of the present invention, the predetermined scribe line 124B of the second substrate may also pass through a portion of the plurality of spacers 161, as shown in fig. 15C. Further, referring to fig. 15A, the width W0 and the width W0' of the predetermined scribe line 124B of the second substrate on both sides of the scribe stable region 160 (e.g., the second stable region 160B) may be between 50 μm and 150 μm, respectively.

In addition, the surface of the spacers 161 contacting the first substrate 101 (or the second substrate) may be rectangular, having a short side 163 and a long side 165, and the long side 165 may be substantially perpendicular to the second predetermined scribe line 124B (as shown in fig. 15D) or substantially parallel to the second predetermined scribe line 124B (as shown in fig. 15E). According to other embodiments of the present invention, the plurality of spacers 161 may be disposed in the dicing stabilizing area 160 in a manner of being asymmetric to the second predetermined scribe line 124B, in addition to being disposed in the dicing stabilizing area 160 with the second predetermined scribe line 124B as a symmetry axis, as shown in fig. 15F. According to other embodiments of the present invention, the display panel may be non-rectangular, and the scribe lines may be adjusted according to the panel shape without being limited to be perpendicular or parallel.

Referring to fig. 16, according to an embodiment of the invention, due to the trend of the narrow frame, in addition to the width of the non-display area on the first boundary 122A and the third boundary 122C being reduced, the width of the non-display area on the second boundary 122B is smaller and smaller, and thus the sealant is closer to the display area. To avoid that the section of the sealant 120 adjacent to the corners of the second boundary 122B and the third side 122C is too close to the display region 104 during the formation of the sealant 120, the sealant 120 may be designed to be composed of a straight portion 120A and a U-shaped portion 120B, wherein the straight portion 120A is adjacent to the second boundary 122B, and the U-shaped portion 120B is adjacent to the first boundary 122A, the boundary 123, and the third boundary 122C, so that the distance D12 between the section of the sealant 120 adjacent to the corners of the second boundary 122B and the third boundary 122C and the display region 104 is far from the distance D11 between the sealant 120 adjacent to the second boundary 122B and the display region 104. In other words, the straight portion 120A has a distance D11 (i.e., the shortest horizontal distance between the straight portion 120A and the display area 104) from the display area 104, and the boundary 127 of the straight portion 120A and the U-shaped portion 120B has a distance D12 (i.e., the shortest horizontal distance between the boundary 127 and the display area 104) from the display area 104, wherein the distance D12 is greater than or equal to the distance D11.

On the other hand, the display device of the invention may further comprise a test circuit located outside the display area. Referring to fig. 17, the display device 100 may include a first contact pad 172 and a second contact pad 174 disposed on the first substrate 101 and outside the display region 104. The display device 100 further includes a test line 170 disposed substantially along the coincident peripheral boundary 122 (including a first boundary 122A, a second boundary 122B, and a third boundary 122C) of the first substrate 101 and the second substrate 103, wherein the first contact pad 172 and the second contact pad 174 are electrically connected through the test line.

Still referring to fig. 17, the test line 170 is not disposed along the interface 123. Thus, after the display device 100 shown in fig. 8 is obtained by performing the cutting process, the voltage, the resistance, and the pulse waveform between the first contact pad 172 and the second contact pad 174 are measured and compared with a reference voltage, resistance, and pulse waveform, so as to determine whether the resulting display device has the phenomenon of the deviation of the cutting line. For example, when a mother board of a display device is subjected to a cutting process and a cutting line is deviated, since the test circuit is disposed along the overlapped peripheral boundary of the first substrate and the second substrate (between the display area and the predetermined cutting line), the test circuit is damaged by the cutting tool if the cutting line is deviated, and thus the measured resistance is increased compared with a reference resistance, and thus, whether the cutting line is deviated or not can be determined.

The test line 170, the first contact pad 172, and the second contact pad 174 may be made of a single layer or multiple layers of metal conductive materials (e.g., aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), or alloys thereof), metal compound conductive materials, metal alloys (e.g., aluminum (Al) containing alloys, copper (Cu) containing alloys, molybdenum (Mo) containing alloys, titanium (Ti) containing alloys, platinum (Pt) containing alloys, iridium (Ir) containing alloys, nickel (Ni) containing alloys, chromium (Cr) containing alloys, silver (Ag) containing alloys, gold (Au) containing alloys, tungsten (W) containing alloys, magnesium (Mg) containing alloys, or combinations thereof), the material of the test circuit 170 and the first contact pad 172 (or the second contact pad 174) may be the same or different. In addition, a protection layer (not shown) may be formed on the testing circuit 170 to prevent the testing circuit 170 from being deteriorated due to the direct contact between the testing circuit 170 and the sealant 120. The material of the passivation layer may be organic insulating material (photosensitive resin) or inorganic insulating material (silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or a combination thereof).

Referring to fig. 18, according to another embodiment of the present invention, a circuit board 180 is electrically connected to the first contact pad 172 and the second contact pad 174 through a first circuit 176 and a second circuit 178, respectively, for providing a test signal to the first contact pad 172 and the second contact pad 174 to determine whether the display device has a phenomenon of a deviation of the cutting line. The circuit board may be, for example, a flexible substrate, a rigid substrate, or a metal core printed circuit board.

In addition, referring to fig. 19, according to another embodiment of the present invention, a driving unit 106 may be further disposed on the first substrate 101 outside the display region 104. The driving unit 106 can utilize a first circuit 176 and a second circuit 178 to electrically connect to the first contact pad 172 and the second contact pad 174, respectively, for providing a test signal to the first contact pad 172 and the second contact pad 174 to determine whether the display device has a phenomenon of a deviation of the cutting line. It is noted that the test signal may be a common electrode voltage signal or a ground voltage signal. The driving unit 106 is connected to the display region 104 through a plurality of signal lines, and provides signals to a plurality of pixels of the display region 104 to generate an image. The driving unit 106 may be an Integrated Circuit (IC).

In summary, in the display device according to the embodiment of the invention, the spacer is disposed in the cutting stable region, so that the supporting effect required during cutting is increased, and the yield of the display device is greatly improved. In addition, the display device of the invention can also comprise a test circuit arranged along the preset cutting line, so that after the cutting manufacturing process is carried out, whether the cutting line deviation phenomenon occurs in the obtained display device can be known by using the test circuit.

In addition, the embodiment of the invention changes the configuration of the circuit in the display device to reduce the occupied area of the circuit in the integrated circuit. In addition, the embodiment of the invention also uses a patterned test pad to improve the manufacturing process reliability and the manufacturing process yield of the display device.

First, a display device known to the inventor includes a gate driving circuit, a driving unit, a test pad, and a line. The driving unit includes a gate signal Output pad (Output Bump), and the gate signal Output pad is electrically connected to the gate driving circuit through a line and to the test pad through another line. As can be seen, the two lines occupy two regions (corresponding to the

regions

113A and 113B in fig. 20B) in the drive unit. When the resolution of the panel is increased, the signal output contacts required by the chip (e.g., the driving unit) are increased, and the area of the panel where the circuit is originally formed is reduced, which also causes a problem that the space for accommodating the circuit below the chip is insufficient when the circuit passes below the chip.

Therefore, in order to reduce the area occupied by the circuit, the present invention provides another configuration of the circuit in the display device. Referring to fig. 20A, a top view of a display device according to an embodiment of the present invention is shown. As shown in fig. 20A, the display device 100 includes a display region 104 and a non-display region 105 adjacent to the display region 104, wherein the display region 104 refers to a region of the display device 100 where pixels including transistors are disposed, and the transistors may be thin film transistors, for example. Accordingly, the display region 104 may also be referred to as a display pixel region 104. The non-display area 105 is an area of the display device other than the display area 104. In this embodiment, the non-display area 105 surrounds the display area 104, and includes Gate Driver on Panel (GOP) 107 located at both sides of the display area 104, and a driving unit 106 and a test pad 109 located in an external Lead Bonding (OLB) 115. In addition, the non-display area 105 further includes a wire 110, and a portion of the wire 110 is disposed in the external pin connection area 115. In other embodiments, the gate driving circuit 107 may be located on only a single side of the display region 104.

The display device 100 may be a liquid crystal display, such as a thin film transistor liquid crystal display. The driving unit 106 can be used for providing a source signal to a pixel (not shown) of the display region 104 or providing a gate signal to the gate driving circuit 107. The gate driving circuit 107 is used for providing a scan pulse signal to the pixels of the display region 104, and controlling each pixel (not shown) in the display region 104 in cooperation with the source signal to enable the display device 100 to display a picture. The Gate driving circuit 107 may be, for example, a Gate On Panel (GOP) or any other suitable Gate driving circuit.

In addition, the driving unit 106 is electrically connected to the gate driving circuit 107 through the testing pad 109. The test pad 109 can be electrically connected to the gate driving circuit 107 and the driving unit 106 by any suitable method, for example, in one embodiment, as shown in fig. 20A, the test pad 109 can be electrically connected to the gate driving circuit 107 and the driving unit 106 by a wire 110.

The present invention can reduce the area occupied by the circuit 110 in the driving unit 106 by electrically connecting the driving unit 106 to the gate driving circuit 107 through the test pad 109. In detail, refer to fig. 20B, which is a partially enlarged view of the display device of fig. 20A. As shown in the figure, the gate signal Output terminal Output Bump)111 of the driving unit 106 is electrically connected to the test pad 109 through a line 110B, and then the test pad 109 is electrically connected to the gate driving circuit 107 through another line 110A. Compared to the display device known by the inventor, in the conventional display device, the

lines

110A and 110B are respectively output from the

regions

113A and 113B, and thus the

areas

113A and 113B are provided below the driving unit 106, but in the case where the line 110 of the present invention only occupies the area of the region 113B in the driving unit 106, but does not occupy the region 113A, as the panel resolution is higher, and the number of output lines of the driving unit 106 is more and more, the region 113A can be used for other output lines, so that the problem of insufficient line space in a chip (e.g., a driving unit) can be solved.

Furthermore, in order to improve the reliability and yield of the manufacturing process of the display device 100 shown in fig. 20A, the test pad 109 of the display device 100 of the present invention may be a patterned test pad. In detail, in the testing step for testing the performance of the display device 100, the probe contacts the testing pad 109, and the probe leaves a hole on the conductive layer of the testing pad 109 when contacting the testing pad 109, and the hole on the conductive layer is easily corroded and enlarged by water, oxygen and other factors over time, which causes an abnormal or open circuit between the driving unit 106 and the gate driving circuit 107, thereby reducing the reliability of the display device 100 and the yield of the manufacturing process. In order to solve the above technical problems, the test pad according to the embodiment of the invention may be patterned into a plurality of functional blocks with conductive layers separated from each other, and the functional blocks are electrically connected through other connection layers.

Referring to fig. 21 and 22A, fig. 21 is a top view of the test pad 109 according to the embodiment of the invention, and fig. 22A is a cross-sectional view of the test pad 109 of fig. 21 taken along line 3-3. As shown in the above two figures, the test pad 109 includes a conductive layer M disposed on the substrate 102, and the conductive layer M includes a first region 300 and a second region 302. The conductive layer of the first area 300 is used to transmit signals between the two wires 110, and the conductive layer of the second area 302 is used to touch the probe in the testing step. The conductive layer of the first region 300 directly contacts the circuit 110, and the conductive layer of the second region 302 is separated from the conductive layer of the first region 300, i.e. when only the conductive layer M is observed, the first region 300 and the second region 302 are not connected or contacted, for example, the conductive layer of the first region 300 and the conductive layer of the second region 302 can be separated by a main gap 304. In addition, the conductive layer of the second region 302 is also separated from the wiring 110. In other words, only the conductive layer M is observed, and the conductive layer of the second region 302 does not directly contact the conductive layer of the first region 300 and the wiring 110. The first region 300 and the second region 302 are electrically connected to each other through a contact hole and another connection layer.

In the present invention, the conductive layer of the second area 302, which is touched by the probe, is separated from the conductive layer of the first area 300, which is used for transmitting signals, and the circuit 110, so that the corrosion phenomenon after the testing step is limited to the conductive layer of the second area 302, and the conductive layer of the first area 300 and the circuit 110 are not corroded. Therefore, even if corrosion occurs after the testing step, the patterned test pad 109 of the present invention can still transmit signals through the conductive layer of the first region 300 and the circuit 110 well, and thus the patterned test pad 109 can improve the reliability and the manufacturing process yield of the display device 100.

In addition, the ratio of the area of the first region 300 to the second region 302 of the conductive layer M ranges from 2 to 1000, for example, from 4 to 10. If the area ratio of the first area 300 to the second area 302 is too large, for example, greater than 1000, the area of the conductive layer of the second area 302 for contacting with the probe is too small, which makes the testing step difficult. However, if the area ratio of the first region 300 to the second region 302 is too small, for example, less than 2, the area of the conductive layer of the first region 300 for transmitting signals is too small, which may increase the resistance. In addition, the test pad 109 has a size of 100 μm to 1000 μm, for example, 500 μm to 800 μm. The dimension of the test pad 109 may be the length L or the width W of the test pad 109.

Referring to fig. 22A, a conductive layer M is provided on a substrate 102. The conductive layer M may be a metal layer, and the material thereof may be a single layer or multiple layers of copper, aluminum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys thereof, combinations thereof, or other metal materials with good conductivity. In other embodiments, the conductive layer M may be a non-metallic material, as long as the material used has conductivity and the corrosion will diffuse after being corroded. For example, in the embodiment shown in fig. 22A, the conductive layer M is a double-layer conductive layer including a first conductive layer M1 and a second conductive layer M2. In one embodiment, the first conductive layer M1 and the second conductive layer M2 are made of the same material. However, in other embodiments, the materials of the first conductive layer M1 and the second conductive layer M2 may be different. A dielectric layer (ILD)206A is disposed between the two conductive layers M1, M2. The first conductive layer M1 and the second conductive layer M2 have the same pattern, and the corresponding patterns are electrically connected through a via V1 disposed in the dielectric layer 206A. The dielectric layer 206A may be silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin-on glass (SOG), any other suitable dielectric material, or a combination thereof. The material electrically connecting the first conductive layer M1 and the second conductive layer M2 through the via V1 may be the first conductive layer M1 or the second conductive layer M2 itself or a combination thereof, or may include copper, aluminum, tungsten, doped polysilicon, any other suitable conductive material, or a combination thereof.

In addition, in an embodiment, as shown in fig. 22A, the conductive layer of the first region 300 and the conductive layer of the second region 302 can be electrically connected through the connection layer 211, and since the connection layer 211 has a higher corrosion resistance than the conductive layer, the first region 300 and the second region 302 which are not in contact are electrically connected through the connection layer 211, and the conductive layer is also protected from corrosion due to water and oxygen. The material of the connection layer 211 may be a transparent conductive material, such as Indium Tin Oxide (ITO), Tin Oxide (TO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Antimony Tin Oxide (ATO), Antimony Zinc Oxide (AZO), combinations thereof, or other suitable transparent conductive oxide materials with high corrosion resistance. The connection layer 211 may be electrically connected to the first conductive layer M1 or the second conductive layer M2 through a via V2 provided in the dielectric layer 206B, and thereby electrically connect the conductive layer of the first region 300 and the conductive layer of the second region 302.

In addition, the conductive layer M may be a single conductive layer. For example, as shown in fig. 22B, only a single conductive layer M is formed on the substrate 102, and the conductive layer of the first region 300 and the conductive layer of the second region 302 can also be electrically connected through the via hole by the connection layer 211. For example, the connection layer 211 can be electrically connected to the conductive layer M through a via V3 provided in the dielectric layer 206 to electrically connect the conductive layer of the first region 300 and the conductive layer of the second region 302.

Referring again to fig. 21, in the embodiment shown in fig. 21, the main gap 304 may surround the conductive layer of the second region 302. The width of the main gap 304 may be 10 μm to 100 μm, for example 20 μm to 40 μm. In addition, the ratio of the width of the main gap 304 to the width W of the test pad 109 is 0.01 to 0.25, for example, 0.025 to 0.1. If the width of the main gap 304 is too wide, for example, it is wider than 100 μ M, or the ratio of the width W of the test pad 109 to the width W of the main gap 304 is greater than 0.25, the main gap 304 will occupy too much area of the test pad 109, so that the area of the conductive layer M is reduced, and the resistance is increased. However, if the width of the main gap 304 is too narrow, for example, it is narrower than 10 μm, or the ratio of the width W of the test pad 109 is less than 0.01, the main gap 304 cannot effectively prevent the conductive layer of the first region 300 from being corroded. For example, when the width of the main gap 304 is too narrow, if the probe touches the main gap 304 due to the offset, the conductive layer of the first region 300 may be exposed, so that the conductive layer of the first region 300 may be corroded.

In addition, the conductive layer of the first area 300 also surrounds the conductive layer of the second area 302, and the conductive layer of the first area 300 can be further separated into a plurality of blocks separated from each other by one or more first gaps 306, i.e. the plurality of blocks are not in direct contact with each other, such as the

blocks

300A and 300B shown in fig. 21. The plurality of

blocks

300A, 300B separated from each other may further improve the manufacturing process reliability and the manufacturing process yield of the display device 100. In detail, in the testing step, the probe may touch the conductive layer of the first area 300 due to the offset, so the conductive layer of the first area 300 may be corroded after the testing step. The now separated

areas

300A, 300B confine the corrosion phenomenon to the areas touched by the probes, while the signals can still be transmitted through the other areas of the conductive layer of the first area 300 that are not corroded. For example, if a probe touches the block 300A, since the

blocks

300A, 300B are separated from each other, the corrosion phenomenon is confined to the block 300A, and the signal can still be transmitted through the non-corroded block 300B. Therefore, the conductive layer of the first region 300 is separated into a plurality of blocks separated from each other by one or more first gaps 306, so that the reliability and the manufacturing process yield of the display device 100 can be further improved.

The width of the first gap 306 may be 3 μm to 50 μm, for example, 10 μm to 20 μm. Alternatively, the ratio of the width of the first gap 306 to the width W of the test pad 109 is 0.0033 to 0.1, for example 0.01 to 0.02. If the width of the first gap 306 is too wide, for example, it is wider than 50 μ M, or the ratio of the width W of the test pad 109 to the width W of the test pad 109 is greater than 0.1, the first gap 306 will occupy too much area of the test pad 109, so that the area of the conductive layer M is reduced, and the resistance is increased. However, if the width of the first gap 306 is too narrow, for example, narrower than 3 μm, or the ratio of the width W of the test pad 109 is less than 0.0033, the first gap 306 cannot effectively separate the block 300A from the block 300B.

Furthermore, the plurality of

blocks

300A, 300B of the first area 300, which are separated from each other, may further include one or more intra-block gaps 308 to divide the

blocks

300A, 300B into a plurality of sub-blocks. The sub-blocks are substantially separated from each other and are connected to each other only by a small portion. For example, the block 300A may be partitioned into a plurality of sub-blocks 300Aa, 300Ab by a plurality of intra-block gaps 308, and the sub-blocks 300Aa, 300Ab are substantially separated from each other and physically connected to each other only by a small portion of the upper left and lower left portions of the figure. The plurality of sub-blocks 300Aa and 300Ab separated from each other can further improve the manufacturing process reliability and the manufacturing process yield of the display device 100. For example, when the probe touches the sub-block 300Ab due to the offset, since the sub-blocks 300Aa and 300Ab are connected only by a small portion, the corrosion phenomenon is easily confined to the sub-block 300Ab, and even if the sub-block 300Ab is damaged due to the corrosion, the signal can be transmitted through the non-corroded block 300 Aa. Therefore, the plurality of

blocks

300A and 300B are separated into a plurality of sub-blocks (e.g., sub-blocks 300Aa and 300Ab) by the intra-block gaps 308, which further improves the reliability and the manufacturing process yield of the display device 100.

The width of the intra-block gap 308 may be 3 μm to 50 μm, for example, 10 μm to 20 μm. Alternatively, the ratio of the width of the intra-block gap 308 to the width W of the test pad 109 is 0.0033 to 0.1, for example, 0.01 to 0.02. If the width of the intra-block gap 308 is too wide, for example, it is wider than 50 μ M, or the ratio of the width W of the test pad 109 to the width W of the intra-block gap 308 is greater than 0.1, the intra-block gap 308 occupies too much area of the test pad 109, so that the area of the conductive layer M is reduced, and the resistance is increased. However, if the width of the intra-block gap 308 is too narrow, e.g., narrower than 3 μm, or the ratio of the width W of the test pad 109 is less than 0.0033, the sub-blocks 300Aa, 300Ab are too close, and the intra-block gap 308 cannot effectively isolate the effects of corrosion.

With continued reference to fig. 21, the material of the line 110 may be a single layer or multiple layers of cu, al, w, au, cr, ni, pt, ti, ir, rh, alloys thereof, combinations thereof, or other metal materials with good conductivity, and the line 110 may also have one or more inter-line gaps 310. In one embodiment, the at least one in-line gap 310 is connected to the at least one first gap 306. The in-line gap 310 may further improve the reliability and yield of the display device 100. In detail, if the corrosion phenomenon extends from the block 300A of the first area 300 to the first block line 110C, the inter-line gap 310 may limit the corrosion phenomenon to the first block line 110C, so that the second block line 110D may not be corroded. Therefore, since the circuit 110 is not completely corroded, the manufacturing process reliability and the manufacturing process yield of the display device 100 can be improved. In other embodiments, the connection layer 211 may also cover the wires 110.

The width of the inter-line gap 310 may be 3 μm to 50 μm, for example, 10 μm to 20 μm. Alternatively, the ratio of the width of the intra-line gap 310 to the width of the line 110 is 0.02 to 0.5, for example, 0.05 to 0.2. If the width of the intra-line gap 310 is too wide, for example, it is wider than 50 μm, or the ratio of the width of the intra-line gap 310 to the width of the line 110 is greater than 0.5, it means that the risk of line 110 disconnection is increased if the intra-line gap 310 is too large. However, if the width of the inter-circuit gap 310 is too narrow, for example, it is narrower than 3 μm, or the ratio of the width of the inter-circuit gap 310 to the width of the circuit 110 is less than 0.02, the inter-circuit gap 310 cannot effectively separate the first block circuit 110C and the second block circuit 110D on both sides of the inter-circuit gap 310 from the mutual corrosion effect. In addition, the ratio of the length of the in-line gap 310 to the length L of the test pad 109 is 0.03 to 3. The length of the in-line gap 310 may be at least 3 μm, or the ratio of the length of the in-line gap 310 to the length L of the test pad 109 may be at least 0.03. The length of the intra-trace gap 310 may be at most equal to the length of the trace 110 in the external pin connection area 115. If the intra-line gap 310 is too short, for example, its length is shorter than 3 μm, or the ratio of its length to the length L of the test pad 109 is less than 0.03, the intra-line gap 310 cannot effectively separate the first block lines 110C from the second block lines 110D. However, the length of the intra-trace gap 310 may not be longer than the length of the trace 110 in the external pin connection area 115.

It should be noted that the test pad of the present invention may have other patterns in addition to the embodiment shown in fig. 21 described above, as shown in the embodiments of fig. 14-17. The scope of the present invention is not limited to the embodiment shown in fig. 21.

Referring to fig. 23, a top view of a test pad according to another embodiment of the present invention is shown. The embodiment shown in fig. 23 is different from the embodiment shown in fig. 21 in that the conductive layer of the second region 302 is also separated into a plurality of

blocks

302A, 302B separated from each other by one or more second gaps 312. In other words, the plurality of

blocks

302A, 302B are not in direct contact with each other. In addition, in this embodiment, the conductive layer of the first region 300 has no intra-block gap.

The plurality of

blocks

302A, 302B separated from each other may further improve the manufacturing process reliability and the manufacturing process yield of the display device 100. For example, when the probe touches only the block 302A, the corrosion phenomenon is limited to the block 302A, and the non-corroded block 302B can also transmit signals through the connecting layer via the via hole, so that the reliability and the manufacturing process yield of the display device 100 can be improved, and the resistance can be reduced.

The width of the second gap 312 may be 10 μm to 100 μm, for example, 30 μm to 50 μm. Alternatively, the ratio of the width of the second gap 312 to the width W of the test pad 109 is 0.01 to 0.25, such as 0.05 to 0.1. If the width of the second gap 312 is too wide, for example, it is wider than 100 μ M, or the ratio of the width W of the test pad 109 to the width W of the test pad 109 is greater than 0.25, the second gap 312 occupies too much area of the test pad 109, so that the area of the conductive layer M is reduced, and the resistance is increased. However, if the width of the second gap 312 is too narrow, for example, it is narrower than 10 μm, or the ratio of the width W of the test pad 109 is less than 0.01, the second gap 312 cannot effectively separate the block 302A from the block 302B.

Referring to fig. 24, a top view of a test pad according to yet another embodiment of the present invention is shown. In the embodiment shown in fig. 24, the conductive layer of the second region 302 is also separated into a plurality of

blocks

302A, 302B separated from each other by second gaps 312. The difference between this embodiment and the aforementioned embodiment of fig. 23 is that the second gap 312 of this embodiment is aligned with the first gap 306 and the in-line gap 310.

Referring to fig. 25, a top view of a test pad according to another embodiment of the present invention is shown. The difference between the embodiment shown in fig. 25 and the aforementioned embodiment shown in fig. 24 is that the conductive layer of the second region 302 is separated into four

blocks

302A, 302B, 302C and 302D separated from each other by three second gaps 312. In addition, the line 110 has two in-line gaps 310, and the conductive layer of the first region 300 does not have a first gap.

Referring to fig. 26, a top view of a test pad according to another embodiment of the present invention is shown. The difference between the embodiment shown in fig. 26 and the embodiments shown in fig. 21 and fig. 14 to 16 is that the conductive layer of the first region 300 is not disposed around the conductive layer of the second region 302, but disposed on one side of the conductive layer of the second region 302. And the conductive layer of the second region 302 is separated into seven

blocks

302A, 302B, 302C, 302D, 302E, 302F and 302G separated from each other by six second gaps 312. In other embodiments, the shape of the second gap 312 is not limited to a straight line, nor to the division manner of the above embodiments, as long as the conductive layer of the second region 302 can be divided into several blocks separated from each other.

In summary, by electrically connecting the driving unit to the gate driving circuit through the testing pad, the area occupied by the circuit in the driving unit can be reduced, and the problem of insufficient circuit space in the driving unit caused by the improvement of the panel resolution can be solved. In addition, by using the patterned test pad, the corrosion after the test step can be limited to a partial area of the patterned test pad, so that the manufacturing process reliability and the manufacturing process yield of the display device are improved.

In addition, an embodiment of the invention further provides a display device, which improves the integration level of wires in the wiring area to reduce the area occupied by the wiring area in the display device, so that the resolution of the display device can be improved on the premise of not increasing the size of the display device.

In addition, according to the embodiment of the invention, the display device can further comprise a first conductive ring which is positioned outside the display area and is composed of a plurality of conductive blocks, so that the display device can be prevented from being damaged due to static electricity accumulation in the manufacturing process of the display device.

Furthermore, according to the embodiment of the present invention, the display device of the present invention may further include a second conductive ring located outside the display area, wherein a sealant is disposed on the second conductive ring and located within a peripheral boundary of the display device, so as to ensure an anti-electrostatic discharge capability of the second conductive ring.

First, referring to fig. 27, a top view of a display device 100 according to an embodiment of the invention is shown. The display device 100 includes a display area 104 and a driving unit 106 disposed on a substrate 102. The display device 100 may be a liquid crystal display (e.g., a thin film transistor liquid crystal display) or an organic electroluminescent device (e.g., an active full color organic electroluminescent device). The display area 104 has a plurality of pixels (not shown), and the driving unit 106 is connected to the display area 104 through a plurality of signal line groups (signal line pairs)110, and provides signals to the plurality of pixels of the display area 110 to generate an image. The display region 104 and the driving unit 106 are separated by a routing region 108(fanout area), and the plurality of signal line groups 110 are disposed in the routing region 108(fanout area). Each signal line group 110 includes a first conductive line 112 and a second conductive line 114, and the first conductive line 112 and the second conductive line 114 are electrically insulated from each other and used for transmitting different signals. For example, each pixel in the display region 104 may be composed of a plurality of sub-pixels (e.g., a red sub-pixel, a blue sub-pixel, and a green sub-pixel; or a red sub-pixel, a blue sub-pixel, a green sub-pixel, and a white sub-pixel), and the first conductive lines 112 and the second conductive lines 114 of the plurality of signal line groups 110 are used for transmitting signals generated by the driving unit 106 to different sub-pixels. In addition, in the routing area 108, the first conductive line 112 and the second conductive line 114 of each signal line group 110 at least partially overlap.

Still referring to fig. 27, the routing area 108(fanout area) can be further defined as being composed of a first circuit area 108a, a second circuit area 108b, and a third circuit area 108c, wherein the first circuit area 108a is adjacent to the display area 104, the third circuit area 108c is adjacent to the driving unit 106, and the second circuit area 108b is located between the first circuit area 108a and the third circuit area 108 c.

According to an embodiment of the present invention, any two adjacent first conductive lines 112 and second conductive lines 114 in the first circuit region 108a are separated by a distance (i.e. the shortest horizontal distance) Da, and any two adjacent first conductive lines 112 and second conductive lines 114 in the third circuit region 108c are separated by a distance (i.e. the shortest horizontal distance) Dc. Wherein the distance Da may be between about 3 μm to 40 μm, the distance Dc may be between about 3 μm to 18 μm, and the distance Da is greater than the distance Dc.

Referring to fig. 28A, a cross-sectional view of the display device of fig. 27 along a cut line a-a' is shown. As shown in fig. 28A, in the second circuit area 108b, the first conductive line 112 of at least one of the signal line groups 110 may overlap the second conductive line 114, so as to reduce the area of the first conductive line 112 and the second conductive line 114 projected on a horizontal plane and increase the integration level of the routing area 108.

Still referring to fig. 28A, the first conductive line 112 can be disposed on the substrate 102. A dielectric layer 116 is disposed on the substrate 102 and covers the first conductive lines 112. The second conductive line 114 is disposed on the dielectric layer 116, and the first conductive line 112 of the signal line group 110 overlaps the second conductive line 114. A passivation layer 118 is disposed on the dielectric layer 116 and covers the second conductive lines 114. Wherein the substrate 102 may be quartz, glass, silicon, metal, plastic, or ceramic material; the first conductive line 112 and the second conductive line 114 may be made of a single-layer or multi-layer metal conductive material (e.g., aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), or an alloy thereof), a metal compound conductive material, a metal alloy (e.g., an aluminum (Al) -containing alloy, a copper (Cu) -containing alloy, a molybdenum (Mo) -containing alloy, a titanium (Ti) -containing alloy, a platinum (Pt) -containing alloy, an iridium (Ir) -containing alloy, a nickel (Ni) -containing alloy, a chromium (Cr) -containing alloy, a silver (Ag) -containing alloy, a gold (Au) -containing alloy, a tungsten (W) -containing alloy, a magnesium (Mg) -containing alloy, or a combination thereof), and the first conductive line 112 and the second conductive line 114 may be made of the same or different materials; the material of the dielectric layer 116 may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or a combination thereof; the passivation layer 118 may be made of an organic insulating material (photosensitive resin) or an inorganic insulating material (silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or a combination thereof) for isolating the first conductive lines 112 and the second conductive lines 114 from air or moisture. In addition, according to an embodiment of the present invention, the first conductive lines 112 and the second conductive lines 114 have inclined sidewalls, as shown in fig. 28A, wherein an included angle between the sidewalls and a horizontal plane is between about 15 degrees and 90 degrees, and the inclination amplitude of the sidewalls of the first conductive lines and the inclination amplitude of the sidewalls of the second conductive lines are the same or different.

According to an embodiment of the invention, the line width W1 of the first conductive line 112 may be between about 2 μm and 10 μm, the line width W2 of the second conductive line 114 may be between about 2 μm and 10 μm, and the line width W1 of the first conductive line 112 and the line width W2 of the second conductive line 114 may be the same (as shown in fig. 28A) or different (as shown in fig. 28B). In other words, the ratio of the line width W1 of the first conductive line 112 to the line width W2 of the second conductive line 114 may be between 1 and 5. For example, referring to fig. 28B, the line width W1 of the first conductive line 112 may be greater than the line width W2 of the second conductive line 114. In addition, referring to fig. 28A to 28B, the first conductive line 112 and the second conductive line 114 may completely overlap (i.e., the projection of the first conductive line 112 to the horizontal plane and the projection of the second conductive line 112 to the horizontal plane completely overlap).

According to an embodiment of the present invention, any two adjacent first wires 112 in the second circuit region 108b are separated by a distance (i.e. the shortest horizontal distance between two adjacent first wires in the second circuit region 108 b) D1, and any two adjacent second wires 114 in the second circuit region 108b are separated by a distance (i.e. the shortest horizontal distance between two adjacent second wires in the second circuit region 108 b) D2, wherein the distance D1 may be between about 2 μm and 30 μm, and the distance D2 may be between about 2 μm and 30 μm.

According to an embodiment of the invention, in the second circuit area 108b, a sum (W1+ D1) of the line width W1 of the first conductive line 112 and the distance D1 is equal to a sum (W2+ D2) of the line width W2 of the second conductive line 114 and the distance D2. In addition, the ratio (D1/(W1+ D1)) of the distance D1 to the sum (W1+ D1) of the distance D1 and the line width W1 of the first conductive line 112 may be between 0.1 and 0.66. When the ratio (D1/(W1+ D1) is greater than or equal to 0.1, it is beneficial to completely fix a sealant (not shown) formed on the second circuit region 108b in a fixing process (applying energy from the substrate 102), and when the ratio (D1/(W1+ D1) is less than or equal to 0.66, it is beneficial to improve the wire integration level in the second circuit region 108 b.

On the other hand, the ratio of the width W3 of the overlapping portion of the first conductive line 112 and the second conductive line 114 (the minimum overlapping width of the projection of the first conductive line 112 to the horizontal plane and the projection of the second conductive line 112 to the horizontal plane) to the line width W1 of the first conductive line 112 may be between 0.3 and 1. In other words, in the second circuit area 108b, the first conductive line 112 and the second conductive line 114 of the signal line group 110 may partially overlap (i.e. the projection of the first conductive line 112 to the horizontal plane and the projection of the second conductive line 112 to the horizontal plane only partially overlap), as shown in fig. 28C, when the line width W1 of the first conductive line 112, the line width W2 of the second conductive line 114, and the width W3 of the overlapping portion of the first conductive line 112 and the second conductive line 114 satisfy the following formula:

(W1+W2-W3)/W1≧1

fig. 29 is a top view of a display device 100 according to another embodiment of the invention. The display device 100 may further include a first conductive loop (conductive loop)116 disposed on the substrate 102 and outside the display region 104, in addition to the display region 104, the driving unit 106, and the routing region 108. As shown in fig. 29, the first conductive loop 116 can be disposed on the substrate 102, surround the display area 104, and be connected to the driving unit 106. The driving unit 106 can provide a voltage to the first conductive ring 116, so that the first conductive ring 116 has a reference potential. It should be noted that the first conductive loop 116 overlaps the signal line groups 110 in the routing area 108, and the overlapping portion can be formed by transferring other conductive layers to the first conductive loop 116 or the signal line groups 110 to avoid short circuit, which will not be described in detail herein.

According to an embodiment of the invention, at least a portion of the first conductive ring 116 is composed of a plurality of first conductive blocks 202 and a plurality of second conductive blocks 204, and the first conductive blocks 202 are electrically connected to the second conductive blocks 204, as shown in fig. 30A, a schematic cross-sectional structure of the display device 100 shown in fig. 29 along a tangent line B-B' of the first conductive ring 116 is shown. According to the embodiment of the invention, the first conductive loop 116 composed of the plurality of first conductive blocks 202 and the plurality of second conductive blocks 204 is disposed on two sides of the display area 104 perpendicular to a first direction X (i.e. two sides parallel to a second direction Y), and it should be noted that in the embodiment, since a plurality of data lines (not shown) are disposed on two sides parallel to the first direction X, it is not easy to configure the first conductive loop 116 by the plurality of first conductive blocks 202 and the plurality of second conductive blocks 204, but not limited thereto.

As can be seen from fig. 30A, the plurality of first conductive blocks 202 can be disposed on the substrate 102. A dielectric layer 206 may be disposed on the substrate 102 and cover the first conductive blocks 202. The second conductive blocks 204 may be disposed on the dielectric layer 206. A passivation layer 208 may be disposed on the dielectric layer 206 and cover the second conductive blocks 204. In addition, a plurality of first through holes 205 penetrate the dielectric layer 206 and the protection layer 208 to expose the first conductive blocks 202. A plurality of second through holes 207 penetrate the passivation layer 208 to expose the second conductive block 204. A conductive layer 210 disposed on the passivation layer 208 and filling the first through hole 205 and the second through hole 207, such that the plurality of first conductive blocks 202 and the plurality of second conductive blocks 204 are electrically connected through the conductive layer 210.

According to an embodiment of the present invention, the first conductive block 202 and the second conductive block 204 may be made of a single layer or multiple layers of metal conductive materials (e.g., aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), or alloys thereof), metal compound conductive materials, metal alloys (e.g., aluminum (Al) -containing alloys, copper (Cu) -containing alloys, molybdenum (Mo) -containing alloys, titanium (Ti) -containing alloys, platinum (Pt) -containing alloys, iridium (Ir) -containing alloys, nickel (Ni) -containing alloys, chromium (Cr) -containing alloys, silver (Ag) -containing alloys, gold (Au) -containing alloys, tungsten (W) -containing alloys, magnesium (Mg) -containing alloys, or combinations thereof), and the materials of the first conductive block 202 and the second conductive block 204 may be the same or different. According to an embodiment of the present invention, the first conductive block 202 and the first conductive line 112 may be formed of the same material in the same manufacturing process step; and/or the second conductive block 204 and the second conductive line 114 can be formed of the same material in the same manufacturing process step. The material of the dielectric layer 206 may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or a combination thereof, and the dielectric layer 206 and the dielectric layer 116 may be formed of the same material in the same process step. The passivation layer 208 may be made of an organic insulating material (photosensitive resin) or an inorganic insulating material (silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or a combination thereof), and the passivation layer 208 and the passivation layer 118 may be formed of the same material in the same process step. The conductive layer 210 may be a single-layer or multi-layer transparent conductive layer, and the material thereof may be, for example, Indium Tin Oxide (ITO), indium zirconium oxide (IZO, indium zinc oxide), aluminum zirconium oxide (AZO, aluminum zirconium oxide), zirconium oxide (ZnO, zinc oxide), tin oxide (SnO)₂) Indium oxide (In)₂O₃) Or a combination of the foregoing.

Still referring to fig. 30A, to prevent the display device 100 from being damaged due to the accumulation of static electricity during the manufacturing process of the display device, the length L1 of the first conductive block 202 may be between about 10 μm and 10000 μm, and the length L2 of the second conductive block 204 may be between about 10 μm and 10000 μm. In addition, any two adjacent first conductive blocks 202 are separated from each other by a distance D3, any two adjacent second conductive blocks 204 are separated from each other by a distance D4, and any two adjacent first conductive blocks 202 and second conductive blocks 204 are separated by a distance D5. Wherein the distance D3 is between 16 μm and 100 μm, the distance D4 is between 16 μm and 100 μm, and the distance D5 is between 3 μm and 40 μm.

According to another embodiment of the present invention, any two adjacent first conductive blocks 202 can be electrically connected directly through the second conductive block 204. Referring to fig. 30B, the plurality of first conductive blocks 202 are disposed on the substrate 102. The dielectric layer 206 is disposed on the substrate 102 and covers the first conductive blocks 202. A plurality of third vias 209 extend through the dielectric layer 206 to expose the first conductive block 202. The second conductive blocks 204 are disposed on the dielectric layer 206 and filled in the third through hole 209, so that any two adjacent first conductive blocks 202 and second conductive blocks 204 are partially overlapped, and thus, the conductive layer 210 does not need to be additionally formed.

In accordance with another embodiment of the present invention, referring to fig. 30C, a planarization layer 212 may be further formed on the protection layer 208. A plurality of fourth vias 211A pass through the dielectric layer 206, the passivation layer 208, and the planarization layer 212 to expose the first conductive block 202. A plurality of fifth through holes 213 penetrate the passivation layer 208 and the planarization layer 212 to expose the second conductive block 204. The conductive layer 210 is formed on the planarization layer 212 and fills the fourth through hole 211A and the fifth through hole 213, so that the first conductive blocks 202 and the second conductive blocks 204 are electrically connected through the conductive layer 210. The planarization layer 212 is a film with insulating property, and may be a dielectric material or a photosensitive resin, for example.

Fig. 31 is a top view of a display device 100 according to another embodiment of the invention. The display device 100 includes a second conductive loop 118 disposed on the substrate 102 and outside the display region 104 and the first conductive loop 116, in addition to the display region 104, the driving unit 106, the routing region 108, and the first conductive loop 116. As shown in fig. 31, the first conductive ring 116 can be disposed on the substrate 102, surround the display area 104, and be connected to the driving unit 106. The second conductive ring 118 can be used as an Electrostatic Discharge (ESD) protection unit, so that the pixels in the display region 104 cannot be directly damaged by the Electrostatic surge. In addition, a sealant 120 is disposed on the substrate 102 and covers a portion of the second conductive ring 118. The area of the sealant 120 projected onto the substrate 102 is defined as a package region (not shown), and the second conductive ring 118 in the package region is covered by the sealant 120.

The second conductive ring 118 may be made of a single-layer or multi-layer metal conductive material (e.g., aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), or an alloy thereof), a metal compound conductive material, a metal alloy (e.g., an aluminum (Al) -containing alloy, a copper (Cu) -containing alloy, a molybdenum (Mo) -containing alloy, a titanium (Ti) -containing alloy, a platinum (Pt) -containing alloy, an iridium (Ir) -containing alloy, a nickel (Ni) -containing alloy, a chromium (Cr) -containing alloy, a silver (Ag) -containing alloy, a gold (Au) -containing alloy, a tungsten (W) -containing alloy, a magnesium (Mg) -containing alloy, or a combination thereof), or a combination thereof. According to an embodiment of the present invention, the second conductive loop 118 can be formed simultaneously when the first conductive block 202 and the second conductive block 204 are formed. In addition, the frame glue can be resin.

Still referring to fig. 31, the display device 100 has a peripheral boundary 122. In the encapsulation region, there is no distance (distance is 0) between the sealant 120 and the peripheral boundary 122. Referring to fig. 32, a cross-sectional view of the display device 100 along the tangent line C-C' of fig. 31 is shown. As shown in fig. 32, the second conductive ring 118 is separated from the outer periphery 122 by a distance D6, and the sealant 120 is disposed on the second conductive ring 118 and located inside the outer periphery 122 (the space between the second conductive ring 118 and the outer periphery 122 is filled with the sealant 12). It is noted that the distance D6 is between 50 μm and 300 μm to prevent the second conductive ring 118 from corroding due to water or air, and reduce its Electrostatic Discharge (ESD) protection capability.

To ensure that the second conductive ring 118 is not exposed out of the sealant 120 due to manufacturing process errors when the sealant 120 is formed. Fig. 33 is a schematic diagram of a display device mother board 201, and the display device mother board 201 is subjected to a cutting process to form the display device shown in fig. 31. As shown in fig. 33, when forming the sealant 120 on the substrate 102, the sealant 120 is required to cover a predetermined scribe line 124. Therefore, when a cutting process (such as a single or multiple blade cutting process or a laser cutting process) is performed along the predetermined scribe line 124, it is ensured that there is no distance (distance is 0) between the peripheral edge of the display device 100 (as shown in fig. 31) and the sealant 120. Thus, the sealant of the second conductive ring 118 is separated from the peripheral boundary 122 by the distance D6. As shown in fig. 33, the sealant 120 can be applied to contact the peripheral border 122.

In addition, according to an embodiment of the invention, when the sealant 120 is formed on the substrate 102, even though the sealant 120 is not coated to be in contact with the peripheral boundary 122, the sealant 120 is still covered on the predetermined scribe line 124 (see fig. 34), and when the cutting process is performed along the predetermined scribe line 124, the display device 100 shown in fig. 31 can still be obtained.

In summary, the present invention reduces the area occupied by the wire routing area in the display device by the integration level of the wires in the wire routing area, so as to improve the resolution of the display device without increasing the size of the display device. In addition, the display device of the invention can further comprise a first conductive ring which is positioned outside the display area and is composed of a plurality of conductive blocks, so that the display device can be prevented from being damaged due to static accumulation in the manufacturing process of the display device. Moreover, the display device of the invention can further comprise a second conductive ring positioned outside the display area, wherein a frame glue is arranged on the second conductive ring and positioned in the peripheral boundary of the display device, so that the antistatic discharge capability of the second conductive ring can be ensured.

In the embodiment of the invention, a partition wall (photo wall) arranged between the display pixel area and the frame glue is used for preventing the frame glue from contacting the liquid crystal material of the display pixel area, so that the distance between the frame glue and the display pixel area can be further shortened to narrow the non-display area of the display device.

First, see fig. 35A and 35B. FIG. 35A is a top view and FIG. 35B is a cross-sectional view taken along line 1B-1B of FIG. 35A, in accordance with an embodiment of the present invention. As shown in fig. 35A, the display device 100 includes a first substrate 101 and a second substrate 103 disposed opposite to the first substrate 101. In addition, as shown in fig. 35A and 35B, the display device 100 includes a display pixel region 104 and a non-display region 105 adjacent to the display pixel region. In other words, the first substrate 101 and the second substrate 103 can be divided into a display pixel region 104 and a non-display region 105 adjacent to the display pixel region. In addition, the non-display area 105 includes an Outer Lead Bonding (OLB) 115, as shown in fig. 35A.

The display device 100 may be a liquid crystal display, such as a thin film transistor liquid crystal display. Alternatively, the liquid crystal display may be a Twisted Nematic (TN) type liquid crystal display, a Super Twisted Nematic (STN) type liquid crystal display, a Double layer Super Twisted Nematic (DSTN) type liquid crystal display, a Vertical Alignment (VA) type liquid crystal display, an In-Plane Switching (IPS) type liquid crystal display, a cholesterol (cholesterol) type liquid crystal display, a Blue Phase (Blue Phase) type liquid crystal display, or any other suitable liquid crystal display.

Referring to fig. 35B, the first substrate 101 includes a first transparent substrate 126, an opaque layer 128 disposed on the first transparent substrate 126, and a color filter layer 130 disposed on the opaque layer 128. In addition, the first substrate 101 may further include a planarization layer 132 covering the color filter layer 130 and a portion of the light-shielding layer 128.

The first transparent substrate 126 may be, for example, a glass substrate, a ceramic substrate, a plastic substrate, or any other suitable transparent substrate. The light-shielding layer 128 is used to shield components other than the pixels in the non-display area 105 and the display pixel area 104. In addition, the material of the light-shielding layer 128 may be black photoresist, black printing ink, black resin, or any other suitable light-shielding material and color. The color filter layer 130 may include color filter layers 130A, 130B, and 130C disposed in the display pixel region 104 and a color filter layer 130D disposed in the non-display region 105. And the color filter layers 130A, 130B, and 130C may be each independently a red color filter layer, a green color filter layer, a blue color filter layer, or any other suitable color filter layer. In addition, the material of the planarization layer 132 may be an organic silicon oxide, a photoresist, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure thereof.

With continued reference to fig. 35B, the second substrate 103 includes a second transparent substrate 134, which may be made of the same material as the first transparent substrate 126, and the materials of the first transparent substrate 126 and the second transparent substrate 134 may be the same or different. In addition, transistors (not shown), such as thin film transistors, for controlling the pixels are disposed in or on the second transparent substrate 134. The second substrate 103 may further include an insulating layer 136 covering the second transparent substrate 134 and the transistors. The insulating layer 136 is used to electrically insulate the second substrate 103 from the components disposed between the first substrate 101 and the second substrate 103. The material of the insulating layer 136 may be silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or any other suitable material.

With continued reference to fig. 35A and 35B, the display device 100 further includes sealant 120(sealant) and liquid crystal material 138 disposed between the first substrate 101 and the second substrate 103. The sealant 120 is used to seal the liquid crystal material 138 between the first substrate 101 and the second substrate 103. The sealant 120 can be an insulating transparent resin or any other suitable sealant material, and the liquid crystal material 138 can be nematic liquid crystal (nematic), smectic liquid crystal (cholesteric), Blue phase liquid crystal (Blue phase) or any other suitable liquid crystal material.

As shown in fig. 35A and 35B, the sealant 120 is located outside the display pixel region 104, and in other words, the sealant 120 is located in the non-display region 105. In some embodiments, the sealant 120 may surround the display pixel region 104. In addition, the width W4 of the sealant 120 is about 200 μm to 900 μm, for example, about 500 μm to 800 μm. It should be noted that if the width W4 of the sealant 120 is too large, for example, greater than about 900 μm, the non-display area 105 of the display device 100 is too wide to make the display device 100 lighter, thinner, and shorter. However, if the width W4 of the sealant 120 is too small, for example, less than about 200 μm, some of the sealant 120 may be broken and may not effectively seal the liquid crystal material 138.

With reference to fig. 35A and 35B, the display device 100 further includes a spacer wall 140(photo wall) disposed between the first substrate 101 and the second substrate 103, and the spacer wall 140 is disposed between the display pixel region 104 and the sealant 120 to further prevent the sealant 120 from contacting the liquid crystal material 138 of the display pixel region 104. In addition, the partition wall 140 has a first side S1 close to the display pixel region 104 and a second side S2 close to the sealant 120, and the height H1 of the first side S1 is greater than the height H2 of the second side S2. For example, in the illustration, the height of the partition wall 140 gradually decreases from H1 on the S1 side (closer to the display region 104) to H2 on the S2 side (closer to the sealant 120). It should be noted that although the spacer 140 is disposed on the planarization layer 132 of the first substrate 101 in the embodiment shown in fig. 35A and 35B, the spacer 140 may be disposed on the second substrate 103 in other embodiments, which will be described in detail later. In addition, although in the embodiment shown in fig. 35A, the partition wall 140 completely surrounds the display pixel region 104. However, it should be understood that the partition wall 140 may not only have one circle, but also have multiple circles, or only partially surround the display pixel region 104, and therefore, the scope of the present invention is not limited to the embodiment shown in fig. 35A.

In addition, the material of the spacer walls 140 may include photoresist, such as positive photoresist or negative photoresist. The spacers 140 may be formed by a photolithography or photolithography etching process. In an embodiment, the photolithography process includes a photoresist patterning process, and the photoresist patterning process further includes a photoresist coating process, a soft baking process, a photomask alignment process, an exposure pattern process, a post-exposure baking process (post-exposure baking process), a photoresist developing process, and a hard baking process. The etching step may include Reactive Ion Etching (RIE), plasma etching, or other suitable etching steps.

With reference to fig. 35B, the partition wall 140 (or the first alignment layer 148 subsequently disposed on the top surface of the partition wall 140) does not directly contact the second substrate 103, so that a first gap G1 is formed between the partition wall 140 (or the first alignment layer 148 subsequently disposed on the top surface of the partition wall 140) and the second substrate 103, and the height H5 of the first gap G1 may be about 0.1 μm to 1.5 μm, for example, about 0.3 μm to 0.8 μm. The height H5 of the first gap G1 is defined as the average of the maximum distance H6 and the minimum distance H7 from the second alignment layer 150 to the top surface of the partition wall 140 (or the first alignment layer 148 subsequently disposed on the top surface of the partition wall 140) (i.e., H5 ═ H6+ H7)/2). In addition, the sealant 120 may directly contact the spacer wall 140, and a portion of the sealant 120 may further extend from the second side S2 to the first side S1 by a distance D8, where the distance D8 may be about 20% to 90%, for example about 40% to 70%, of the width W5 of the spacer wall 140. It should be noted that if the distance D8 is too large, for example, greater than about 90% of the width W5 of the partition wall 140, the probability of defects caused by the sealant 120 contacting the liquid crystal material 138 contaminating the display pixel region 104 is increased, and the yield of the manufacturing process is reduced. In addition, if the height H5 of the first gap G1 is too large, for example, greater than about 1.5 μm, the spacer 140 cannot effectively prevent the sealant 120 from extending into the display pixel region 104 through the first gap G1, and the height difference between the spacer 140 and the subsequent main spacer 142 is too large or the sealant 120 contacts to contaminate the liquid crystal material 138 in the display pixel region 104, which may cause the display device 100 to generate the problem of uneven display, such as frame mura. However, if the height H5 of the first gap G1 is too small, for example, less than about 0.1 μm, the top surface of the partition wall 140 is too close to the second substrate 103, so that the sealant 120 extending into the first gap G1 may push the second substrate 103 away from the first substrate 101, which may cause the display device 100 to have a problem of gap mura (gap mura) and other display problems, resulting in a decrease in the yield of the manufacturing process.

Since the spacer 140 prevents the sealant 120 from contacting the liquid crystal material 138 of the display pixel region 104, the distance between the sealant 120 and the display pixel region 104 can be further shortened to narrow the non-display region 105 of the display device 100, so that the display device 100 is lighter, thinner and shorter. In addition, since the height H1 of the first side S1 of the sealant 120 is greater than the height H2 of the second side S2, even though the sealant 120 extends into the first gap G1 between the partition wall 140 and the second substrate 103 as described above, the higher height H2 of the second side S2 can prevent the sealant 120 from extending into the display pixel region 104 through the first gap G1, so that the sealant 120 can be further prevented from contacting the liquid crystal material 138 of the display pixel region 104 to cause defects of the display device 100. As shown in fig. 35B, the distance between the sealant 120 and the display pixel region 104 is the total distance (i.e., W5+2xT1+ D7) obtained by summing the width W5 of the partition wall 140, the thickness T1 of the first alignment layer 148 subsequently located at the two sides S1 and S2 of the partition wall 140, and the distance D7 from the first side S1 of the partition wall 140 to the display pixel region 104, without considering that the sealant 120 extends into the first gap G1.

The difference between the height H1 of the first side S1 and the height H2 of the second side S2 of the partition wall 140 may be about 0.01 μm to 0.3 μm, for example, about 0.05 μm to 0.1 μm. It should be noted that if the difference between the first side S1 and the second side S2 is too large, for example, greater than about 0.3 μm, the height H2 of the second side S2 is too low, which may cause the spacer 140 to effectively prevent the sealant 120 from contacting the liquid crystal material 138 of the display pixel region 104. However, if the difference between the first side S1 and the second side S2 is too small, for example, less than about 0.01 μm, the spacer 140 cannot effectively utilize the height difference between the first side S1 and the second side S2 to prevent the sealant 120 from extending into the display pixel region 104 through the first gap G1.

With continued reference to FIG. 35B, the width W5 of the spacer 140 is about 10 μm to 200 μm, for example about 60 μm to 110 μm. It should be noted that if the width W5 of the partition wall 140 is too wide, for example, wider than about 200 μm, the non-display area 105 of the display device 100 is too wide to make the display device 100 lighter, thinner and shorter. However, if the width W5 of the partition wall 140 is too narrow, for example, narrower than about 10 μm, the partition wall 140 cannot effectively prevent the sealant 120 from contacting the liquid crystal material 138 of the display pixel region 104.

In addition, the distance D7 from the first side S1 of the partition wall 140 to the display pixel region 104 is 20 μm to 200 μm, for example, about 50 μm to 100 μm. It should be noted that if the distance D7 is too wide, for example, wider than about 200 μm, the non-display area 105 of the display device 100 is too wide to make the display device 100 lighter, thinner and shorter. However, if the distance D7 is too short, for example, less than about 20 μm, the sealant 120 may contact the liquid crystal material 138 in the display pixel region 104, which may increase the probability of defects and reduce the yield of the manufacturing process.

In addition, the height H3 of the partition wall 140 can be adjusted by changing the distance D7 from the first side S1 of the partition wall 140 to the display pixel area 104. In detail, if the distance D7 is smaller, the flow effect of the partition wall 140 is smaller, which allows the partition wall 140 to have a higher height. Conversely, if the distance D7 is greater, the greater the leveling effect of the partition wall 140, the lower the height of the partition wall 140 may be allowed. Therefore, the height difference between the main spacers 142 and the partition walls 140 (i.e., H4-H3) can be adjusted to be within the preferred range (i.e., about 0.1 μm to 1.5 μm) by adjusting the distance D7.

With reference to fig. 35B, the display device 100 further includes a main spacer 142(main photo spacer) disposed between the first substrate 101 and the second substrate 103, and the main spacer 142 is disposed in the display pixel region 104. The main spacers 142 may be defined by the same photolithography and etching process as the spacers 140, however, the main spacers 142 may be formed by another photolithography and etching process.

In addition, the height H4 of the main spacer 142 is higher than the height H3 of the spacer 140. In the above description, the height H3 of the partition wall 140 is defined as the average of the height H1 of the first side S1 and the height H2 of the second side S2 of the partition wall 140 (i.e., H3 ═ H1+ H2)/2). In some embodiments, the height H4 of the primary spacers 142 is about 0.1 μm to 1.5 μm, such as about 0.3 μm to 0.8 μm, above the height H3 of the spacer walls 140. It should be noted that if the height difference between the main spacers 142 and the partition walls 140 is too large, for example, greater than about 1.5 μm, the display device 100 may have a problem of non-uniform display, such as frame mura. However, if the height difference between the main spacers 142 and the spacers 140 is too small, for example, less than about 0.1 μm, the top surfaces of the spacers 140 are too close to the second substrate 103, so that the sealant 120 extending into the first gap G1 may push the second substrate 103 away from the first substrate 101, which may cause the display device 100 to have a problem of gap mura (gap mura) and other display problems, resulting in a decrease in the yield of the manufacturing process.

Next, returning to fig. 35A, the partition wall 140 includes a corner region 144 and a strip region 146, and the width W6 of the corner region 144 is different from the width W7 of the strip region 146. For example, in the embodiment shown in fig. 35A, the width W6 of corner region 144 is greater than the width W7 of elongate region 146.

However, the width of the corner region may also be less than the width of the elongate region. For example, fig. 36 shows another embodiment of the present invention, which is different from the aforementioned embodiment shown in fig. 1-4 mainly in that the width W6 of the corner region 144 is smaller than the width W7 of the long strip region 146. In addition, as one skilled in the art will recognize, the width of the corner region may be equal to the width of the strip region, and the scope of the present invention is not limited to the embodiments shown in fig. 1 and 2. It should be noted that the same or similar components or layers are denoted by the same or similar reference numerals, and the materials, manufacturing methods and functions thereof are the same or similar to those described above, so that the detailed description thereof will not be repeated.

Referring back to fig. 35B, the display device 100 may further include a first alignment layer 148 disposed on the planarization layer 132 and covering the spacers 140 and the main spacers 142, and a second alignment layer 150 disposed on the insulating layer 136. The first alignment layer 148 and the second alignment layer 150 are thin layers for inducing alignment of liquid crystal molecules, and may be polyimide (polyimide) or any other suitable alignment layer material. In addition, the first alignment layer 148 disposed on the top surface of the main spacer 142 may directly contact the second alignment layer 150. The thickness of the first alignment layer 148 may be about 300 to 1000 angstroms, such as about 400 to 700 angstroms, and the thickness T1 of the first alignment layer 148 on the planarization layer 132 is greater than or equal to the thickness T2 of the first alignment layer 148 on the partition walls 140.

With reference to fig. 35B, as mentioned above, the color filter layer 130 of the first substrate 101 may include the first color filter layer 130D disposed in the non-display area 105, and the first color filter layer 130D is disposed under the partition wall 140. Further, as shown in fig. 35B, the width W8 of the first color filter layer 130D is greater than the width W5 of the partition wall 140. However, it should be noted that the width of the first color filter layer may also be smaller than the width of the partition wall. For example, in another embodiment shown in fig. 37, the width W8 of the first color filter layer 130D is smaller than the width W5 of the partition wall 140. In addition, as one skilled in the art will recognize that the width of the first color filter layer may also be equal to the width of the partition wall, and the scope of the present invention is not limited to the embodiments shown in fig. 1, fig. 2 and fig. 3.

The height H3 of the partition wall 140 may be adjusted by changing the width W8 of the first color filter layer 130D disposed thereunder. In detail, if the width W8 of the first color filter layer 130D is smaller, the flow effect of the partition wall 140 is larger, which allows the partition wall 140 to have a lower height. Conversely, if the width W8 of the first color filter layer 130D is larger, the leveling effect of the partition wall 140 is smaller, which allows the partition wall 140 to have a higher height. Therefore, the height difference between the main spacers 142 and the spacers 140 (i.e., H4-H3) can be within the aforementioned preferred range (i.e., about 0.1 μm to 1.5 μm) by adjusting the width W8 of the first color filter layer 130D.

Further, referring to fig. 38, a cross-sectional view of another embodiment of the present invention is shown. The difference between the embodiments shown in fig. 1-3 is that the color filter layer 130 of the first substrate 101 further includes a second color filter layer 130E corresponding to the lower portion of the partition wall 140, the second color filter layer 130E is different from the first color filter layer 130D, and the boundary S3 between the first color filter layer 130D and the second color filter layer 130E corresponds to the lower portion of the partition wall 140. However, it should be noted that the boundary S3 between the first color filter layer 130D and the second color filter layer 130E may also correspond to the first side S1 of the partition wall 140 or an area other than the first side S1, and the scope of the invention is not limited to the embodiment shown in fig. 38. Further, similarly to the first color filter layer 130D, the height H3 of the partition wall 140 may be adjusted by changing the width W9 of the second color filter layer 130E disposed corresponding thereto therebelow.

Fig. 39 shows another embodiment of the present invention, which is different from the embodiment shown in fig. 1-4 in that the spacer 140 is located on the insulating layer 136 of the second substrate 103, instead of the embodiment shown in fig. 1-4, which is located on the planarization layer 132 of the first substrate 101. In addition, as shown in fig. 39, the display device 100 may further include a second alignment layer 150 disposed on the insulating layer 136 and covering the partition wall 140, the material of the second alignment layer 150 is the same as that of the first alignment layer 148, and the second alignment layer 150 disposed on the top surface of the main spacer 142 may directly contact the first alignment layer 148. In addition, the thickness T3 of the second alignment layer 150 on the insulating layer 136 is greater than or equal to the thickness T4 of the second alignment layer 150 on the partition wall 140.

In addition, the partition wall 140 (or the second alignment layer 150 disposed on the top surface of the partition wall 140) does not directly contact the first substrate 101, so that a second gap G2 is formed between the partition wall 140 and the first substrate 101, and the height H8 of the second gap G2 is 0.1 μm to 1.5 μm, for example, about 0.3 μm to 0.8 μm. The height H8 of the second gap G2 is defined as the average of the maximum distance H9 and the minimum distance H10 from the first alignment layer 148 to the top surface of the partition wall 140 (or the second alignment layer 150 disposed on the top surface of the partition wall 140) (i.e., H8 ═ H9+ H10)/2). It should be noted that if the height H8 of the second gap G2 is too large, for example, greater than about 1.5 μm, the frame sealant 120 cannot be effectively prevented from extending into the display pixel region 104 through the second gap G2 by the partition walls 140, and the height difference between the partition walls 140 and the main spacers 142 is too large, which may cause the display device 100 to generate frame mura (frame mura) and other display non-uniformity problems. However, if the height H8 of the second gap G2 is too small, for example, less than about 0.1 μm, the top surface of the partition wall 140 is too close to the first substrate 101, so that the sealant 120 extending into the second gap G2 may push the first substrate 101 away from the second substrate 103, which may cause the display device 100 to generate a problem of gap mura (gap mura) and other display problems, thereby reducing the yield of the manufacturing process.

In summary, the spacer wall of the present invention can prevent the sealant from contacting the liquid crystal material of the display pixel region, so that the distance between the sealant and the display pixel region can be further shortened to narrow the non-display region of the display device, thereby making the display device lighter, thinner and shorter. In addition, because the height of the side of the partition wall close to the display area is relatively high, the sealant still cannot enter the display pixel area even if the sealant extends into the partition wall, and the defect of the display device caused by the fact that the sealant contacts the liquid crystal material can be further prevented.

In the embodiment of the invention, the shading layer is provided with the enlarged part to further shade the area of the display device which is likely to generate the light leakage phenomenon so as to improve the contrast ratio of the device, and the enlarged part can prevent the phenomenon of uneven development (mura display) from being generated, so that the display quality can be further improved.

Referring first to fig. 40A, a top view of a display device 100 according to an embodiment of the invention is shown. As shown in fig. 40A, the display device 100 includes a display pixel region 104 and a non-display region 105 adjacent to the display pixel region. In this embodiment, the non-display area 105 surrounds the display pixel area 104. The display pixel region 104 refers to a region of the display device 100 where a pixel including a transistor is disposed. In addition, the non-display area 105 may include an external lead Bonding (OLB) 115.

Next, refer to fig. 40B, which is an enlarged view of the display device 100 of fig. 40A in the area 1B. As shown in fig. 40B, the display pixel region 104 includes at least two pixels 400 and a light-shielding layer 128. The pixel 400 includes a plurality of sub-pixels 402, for example, in the embodiment shown in fig. 40B, each pixel 400 includes three sub-pixels 402. The material of the light-shielding layer 128 may be black photoresist, black printing ink, black resin, or any other suitable light-shielding material and color. The light-shielding layer 128 includes a matrix portion 404 and an enlarged portion 406. The matrix portion 404 defines the sub-pixel 402, and the enlarged portion 406 is disposed at an intersection 408 of two adjacent sub-pixels 402, and the enlarged portion 406 is adjacent to the matrix portion 404. The matrix portion 404 of the light-shielding layer 128 is used to shield components other than the pixels in the non-display area 105 and the display pixel area 104, and the enlarged portion 406 is used to shield an area of the sub-pixel 402 of the display device 100 where a light leakage phenomenon may occur.

As shown in fig. 40B, the matrix portion 404 of the light-shielding layer 128 includes a plurality of matrix portion columns 404C and a plurality of matrix portion rows 404R, and the matrix portion columns 404C and the matrix portion rows 404R define a plurality of sub-pixels 402 of the pixel 400. The enlarged portion 406 of the light-shielding layer 128 is disposed at the intersection 408 of the matrix column 404C and the matrix row 404R, and covers a portion of the sub-pixels 402. For example, as shown in FIG. 40B, the enlarged portion 406 covers a portion of the four subpixels 402 adjacent to the intersection 408. In other words, the four sub-pixels 402 adjacent to the intersection 408 are partially covered by the enlarged portion 406. In one embodiment, the edge of the enlarged portion 406 is rounded.

Referring to fig. 40B and 40C, fig. 40C is a schematic view of the display device 100 of fig. 40B without the enlarged portion 406. In fig. 40C, the sum of the areas of the six sub-pixels 402 is the first area, and the ratio of the area of the enlarged portion 406 to the first area in fig. 40B is about 1.5% to 6%, preferably 2.5% to 5%. Specifically, as shown in fig. 40B and 40C, the four fan-shaped regions of the light-shielding layer 128 around the intersection 408 constitute an enlarged portion 406. The four fan-shaped regions are disposed entirely within the sub-pixel 402 and all block a portion of the sub-pixel 402. In addition, the two adjacent pixels 400 of fig. 40B include six sub-pixels 402, wherein four sub-pixels 402 adjacent to the intersection 408 are partially covered by the enlarged portion 406 (i.e., the four fan-shaped regions), and the other two sub-pixels 402 are not covered by the enlarged portion 406. The ratio of the area of the enlarged portion 406 (i.e., the four fan-shaped regions) between two adjacent pixels 400 to the area of the six sub-pixels 402 of the two adjacent pixels 400 (i.e., the area of the six sub-pixels 402 shown in fig. 40C) when the enlarged portion 406 does not cover is about 1.5% to 6%, preferably 2.5% to 5%.

The enlarged portion 406 with a specific area ratio can shield the area of the display device where light leakage may occur to improve the contrast of the device, and can prevent the occurrence of uneven display (mura) to further improve the display quality.

In detail, in the display device 100, at the intersection 408 of two adjacent sub-pixels 402 (i.e. the intersection 408 of the matrix portion column 404C and the matrix portion row 404R), a light leakage phenomenon is easily generated due to the arrangement of a spacer (photo spacer), so that the alignment light leakage and the scratch light leakage caused by the spacer can be shielded by the enlarged portion 406 disposed at the intersection 408 to improve the contrast of the device. However, if the area of the enlarged portion 406 is too large, for example, the ratio is greater than about 6%, the display device 100 may have uneven display. However, if the ratio is too small, for example, less than about 1.5%, the area of the enlarged portion 406 is too small to effectively block light leakage.

Next, referring to fig. 41A, a cross-sectional view of the display device 100 according to the embodiment of the present invention is shown. As shown in fig. 41A, the display device 100 further includes a first substrate 101, a second substrate 103 disposed opposite to the first substrate 101, and a main spacer 142 and a sub-spacer 410 disposed on the first substrate 101. In addition, the display device 100 further includes a first alignment layer 148 disposed on the first substrate 101 and a second alignment layer 150 disposed on the second substrate 103.

In the embodiment shown in fig. 41A, the first substrate 101 is a color filter layer substrate, and the second substrate 103 is a transistor substrate. In detail, the first substrate 101 as a color filter substrate may include a first transparent substrate 126, a light-shielding layer 128 disposed on the first transparent substrate 126, and a color filter layer 130 disposed on the light-shielding layer 128. The first transparent substrate 126 may be, for example, a glass substrate, a ceramic substrate, a plastic substrate, or any other suitable transparent substrate, and the color filter layer 130 may include a red filter layer, a green filter layer, a blue filter layer, or any other suitable color filter layer. In addition, the second substrate 103 as a transistor substrate may be a transparent substrate, and the material thereof may be the same as the material of the first transparent substrate 126. However, in other embodiments, the material of the transparent substrate of the second substrate 103 may be different from the material of the first transparent substrate 126. In addition, transistors (not shown), such as thin film transistors, for controlling the pixels are disposed in or on the transparent substrate of the second substrate 103.

The main spacers 142 and the sub-spacers 410 disposed on the first substrate 101 are used to space the first substrate 101 from the second substrate 103, so that the liquid crystal material 318 can be filled between the first substrate 101 and the second substrate 103. In addition, since the main spacers 142 are a main structure for spacing the first substrate 101 and the second substrate 103, and the sub spacers 410 are mainly a structure for preventing the first substrate 101 and the second substrate 103 from contacting when the display device is pressed, the height of the main spacers 142 is higher than that of the sub spacers 410. In addition, the primary spacer 142 has a top surface 142T away from the first substrate 101 and a bottom surface 142B adjacent to the first substrate 101, and the secondary spacer 410 also has a top surface 410T away from the first substrate 101 and a bottom surface 410B adjacent to the first substrate 101. The material of the main spacers 142 and the sub-spacers 410 may include a photoresist, such as a positive photoresist or a negative photoresist. And the primary spacers 142 and the secondary spacers 410 may be defined by the same photolithography or photolithography etching process. However, the primary spacers 142 and the secondary spacers 410 may be defined by different photolithography or photolithography etching processes, respectively. The photolithography process includes photoresist patterning, which further includes steps of photoresist coating, soft baking, photomask alignment, pattern exposure, post-exposure baking, photoresist development, hard baking, and the like. The etching step may include Reactive Ion Etching (RIE), plasma etching, or other suitable etching steps.

The first alignment layer 148 and the second alignment layer 150 are thin layers for inducing alignment of liquid crystal molecules, and each of the materials may independently include polyimide (polyimide) or any other suitable alignment layer material. The first alignment layer 148 covers the first substrate 101, the main spacer 142 and the sub-spacer 410. And the first alignment layer 148 disposed on the top surface 142T of the main spacer 142 may directly contact the second alignment layer 150.

Referring to fig. 41A to 41C, fig. 41B and 41C are top and side views of a display device 100 according to an embodiment of the invention. As shown in fig. 41A-41C, during the alignment or transportation, since the first alignment layer 148 on the top surface 142T of the main spacer 142 directly contacts the second alignment layer 150, a rugged region 412 is formed in the region of the second alignment layer 150 corresponding to the top surface 142T of the main spacer 142, and the area of the rugged region 412 may be larger than the area of the top surface 142T of the main spacer 142. In other words, the second alignment layer 150 includes a rough region 412, and the rough region 412 is disposed corresponding to the main spacer 142. The roughness of the roughened region 412 of the second alignment layer 150 is different from the roughness of the other regions of the second alignment layer 150. In addition, the distance D13 from the top surface 142T of the main spacer 142 to the edge of the rough region 412 is 0 μm to 12 μm, which is less than about 11.5 μm. In detail, the distance D13 is a distance between the projected edge 142TE of the first substrate 101 and the edge 412E of the rough region 412 by the top surface 142T of the primary spacer 142.

Since the alignment degree of the rugged regions 412 of the second alignment layer 150 is different from that of other regions of the second alignment layer 150, the arrangement of the liquid crystal molecules corresponding to the rugged regions 412 is different from that of the other liquid crystal molecules, which causes light leakage of the display device 100 and reduces the contrast ratio. Therefore, the enlarged portion of the light shielding layer is disposed in the area of the display device 100 corresponding to the rough area 412 to shield the area of the display device that may generate light leakage and improve the contrast of the device.

As shown in fig. 41B-41C, the enlarged portion 406 of the light-shielding layer 128 includes a main enlarged portion 406A and a sub-enlarged portion 406B, and the main spacer 142 is disposed corresponding to the main enlarged portion 406A, and the sub-spacer 410 is disposed corresponding to the sub-enlarged portion 406B. In addition, the main enlarged portion 406A and the sub-enlarged portion 406B are disposed at the intersection 408 of two adjacent sub-pixels 402. In other words, the main enlarged portion 406A and the sub-enlarged portion 406B are disposed at the intersection 408 of the matrix portion column 404C and the matrix portion row 404R.

In the present invention, the main spacer 142 is disposed corresponding to the main enlarged portion 406A, so that the main enlarged portion 406A can shield the light leakage phenomenon caused by the rough region 412 corresponding to the main spacer 142. In one embodiment, the light-shielding layer 128 including the main enlarged portion 406A can completely shield the rough region 412.

In addition, in order to effectively shield the light leakage phenomenon from the main enlarged portion 406A, the maximum distance D14 between the projected edge 142BE of the bottom surface 142B of the main spacer 142 on the first substrate 101 and the edge 406AE of the main enlarged portion 406A is about 5 μm to 15 μm, preferably 11.5 μm to 12.5 μm. If the distance D14 is too large, for example, greater than about 15 μm, it may cause the pixel opening area of the display device 100 to be too small or display non-uniformly. However, if the distance D14 is too small, for example, less than about 5 μm, the area of the main enlarged portion 406A is too small to effectively block light leakage. In addition, as shown in FIG. 41B, the distance D14 should be greater than the distance D13 so that the light-shielding layer 128 including the main enlarged portion 406A can completely shield the rough region 412.

The enlarged portion 406B can shield the display device 100 from light leakage to improve the contrast ratio of the device. For example, in one embodiment, the distance D15 corresponding to the first side S4 of the sub spacer 410 in the display device 100 is 5.5 μm, and the distance D16 corresponding to the second side S5 of the sub spacer 410 opposite to the first side S4 is 8.5 μm. If the distance D15 corresponding to the first side S4 of the sub spacer 410 is increased to 8.75 μm and the distance D16 corresponding to the second side S5 of the sub spacer 410 is increased to 10.75 μm, the contrast of the display device 100 is improved from 881 to 994.

With continued reference to fig. 41A-41C, in one embodiment, the first alignment layer 148 and the second alignment layer 150 are aligned by a rubbing process. However, when the first alignment layer 148 is aligned by the rubbing process, the first alignment layer 148 around the bottom edges 142BE and 410BE of the main spacer 142 and the sub-spacer 410 is difficult to BE aligned effectively. Therefore, the degree of alignment of the first alignment layer 148 around the bottom side edges 142BE and 410BE is different from that of the other regions of the first alignment layer 148.

This difference in alignment causes the arrangement of the liquid crystal molecules around the bottom edges 142BE and 410BE of the main spacers 142 and the sub spacers 410 to BE different from the arrangement of the liquid crystal molecules corresponding to the other liquid crystal molecules, which results in light leakage of the display device 100 and a decrease in contrast. Therefore, in the display device 100 of the present invention, the main enlarged portion 406A is disposed corresponding to the main spacer 142, and the sub-enlarged portion 406B of the light shielding layer is disposed corresponding to the region around the bottom edge 410BE of the sub-spacer 410, so as to shield the region of the display device that may generate the light leakage phenomenon and improve the contrast of the device.

With continued reference to fig. 41B-41C, the sub-spacer 410 of the present invention may BE disposed corresponding to the sub-enlarged portion 406B, such that the sub-enlarged portion 406B may shield the light leakage phenomenon caused by the area around the bottom edge 410BE of the corresponding sub-spacer 410.

In order to effectively shield the light leakage phenomenon from the sub-enlarged portion 406B, the sub-spacer 410 includes a bottom surface 410B adjacent to the first substrate 101, as shown in fig. 41A. And referring to fig. 41B-41C, the distance D15 or D16 between the edge 410BE of the bottom surface 410B of the secondary spacer 410 and the edge 406BE of the secondary enlarged portion 406B is about 5 μm to 10 μm. In detail, the distance D15 or D16 is the maximum distance between the projected edge 410BE of the bottom surface 410B of the sub spacer 410 on the first substrate 101 and the projected edge 406BE of the sub enlarged portion 406B on the first substrate 101. If the distance D15 or D16 is too large, such as greater than about 10 μm, the pixel opening area of the display device 100 may be too small or display non-uniformly. However, if the distance D15 or D16 is too small, for example, less than about 5 μm, the area of the enlarged portion 406B is too small to effectively block light leakage.

In addition, the first alignment layer 148 around the bottom edges 142BE and 410BE of the main spacer 142 and the sub-spacer 410 may have different alignment degrees at opposite sides of the main spacer 142 and the sub-spacer 410 due to a rubbing process. In detail, if the rubbing process includes a plurality of rubbing steps, the rubbing direction of the last rubbing step is taken as the standard (for example, the rubbing direction 414 in fig. 41B-41C). The side of the sub-spacer 410 facing the rubbing direction 414 is the first side S4 (also referred to as windward side), and the side of the sub-spacer 410 facing away from the rubbing direction 414 is the second side S5 (also referred to as leeward side). The first side S4 (windward side) and the second side S5 (leeward side) are opposite to each other. Since the first alignment layer 148 around the bottom edge 410BE of the first side S4 (windward side) faces the rubbing direction 414, and the first alignment layer 148 around the bottom edge 410BE of the second side S5 (leeward side) faces away from the rubbing direction 414, the first alignment layer 148 of the first side S4 (windward side) is aligned to a better degree than the first alignment layer 148 of the second side S5 (leeward side). The different alignment degrees may cause the light leakage of the display device 100 around the bottom edge 410BE of the sub-spacer 410 to BE different between the first side S4 (windward side) and the second side S5 (leeward side).

Therefore, the distance D15 or D16 between the edge 410BE of the bottom surface 410B of the sub spacer 410 and the edge 406BE of the sub enlarged portion 406B may BE different between the first side S4 (windward side) and the second side S5 (leeward side) to correspond to different light leakage degrees. In one embodiment, the distance D15 between the edge 410BE of the bottom surface 410B of the sub-spacer 410 and the edge 406BE of the sub-enlarged portion 406B at the first side S4 (windward side) is about 5 μm to 8 μm, and the distance D16 between the edge 410BE of the bottom surface 410B of the sub-spacer 410 and the edge 406BE of the sub-enlarged portion 406B at the second side S5 (leeward side) is about 5 μm to about 10 μm. If the distance D15 or D16 is too large, such as greater than about 10 μm, the pixel opening area of the display device 100 may be too small or display non-uniformly. However, if the distance D15 or D16 is too small, for example, less than about 5 μm, the area of the enlarged portion 406B is too small to effectively block light leakage.

The sub-enlarged portion 406B can shield the display device 100 from light leakage to improve the contrast ratio of the device. For example, in one embodiment, the distance D15 corresponding to the first side S4 of the sub spacer 410 in the display device 100 is 5 μm, and the distance D16 corresponding to the second side S5 of the sub spacer 410 opposite to the first side S4 is also 5 μm. If the distance D15 corresponding to the first side S4 of the sub spacer 410 is increased to 5.5 μm and the distance D16 corresponding to the second side S5 of the sub spacer 410 is also increased to 5.5 μm, the contrast ratio of the display device 100 is greatly increased from 393 to 847.

Referring to fig. 42A-42B, a top view and a side view of a display device 100 according to another embodiment of the invention are shown. In this embodiment, the first alignment layer 148 and the second alignment layer 150 are aligned by photo alignment process (photo alignment process), or the first alignment layer 148 is aligned by photo alignment process (photo alignment process), and the second alignment layer 150 is aligned by rubbing process (rubbing process), rather than both of them. The photo-alignment process irradiates the alignment layer with linearly polarized light to generate alignment effect. The direction of the linearly polarized light determines the alignment direction of the alignment layer, and the included angle between the linearly polarized light and the alignment layer affects the pre-tilt angle of the liquid crystal molecules when the liquid crystal molecules are aligned.

Since the alignment degree of the first alignment layer 148 around the bottom edges 142BE and 410BE of the main spacer 142 and the sub-spacer 410 is not different from that of other regions of the first alignment layer 148 when the alignment is performed by the photo-alignment process. Therefore, the light-shielding layer 128 disposed in the area corresponding to the sub-spacer 410 in the display pixel region 104 is not provided with the sub-enlarged portion 406B or any enlarged portion 406, as shown in fig. 42A-42B.

However, since the size and position of the sub-spacers 410 may vary between different manufacturing process lots and may be shifted when assembling the first substrate 101 and the second substrate 103, the sub-spacers 410 still need to be kept at a certain distance from the adjacent sub-pixels 402. For example, in one embodiment, the shortest distance D17 from the projection edge 410BE of the sub-spacer 410B to the sub-pixel 402 on the first substrate 101 is about 3 μm to 8 μm. If the distance D17 is too large, such as greater than about 8 μm, the pixel opening area of the display device 100 may be too small or the display may be non-uniform. However, if the distance D17 is too small, for example, less than about 3 μm, the sub-spacers 410 may be exposed in the sub-pixels 402 due to the variation of the manufacturing process, thereby deteriorating the display quality.

In addition, since the excessive number of the sub-spacers 410 makes the aperture ratio of the pixels 400 of the display device 100 difficult to increase and makes the transmittance of the display device 100 difficult to improve, in an embodiment of the invention, as shown in fig. 43, each pixel 400 of the display device 100 includes three sub-pixels 402, and the ratio of the number of the sub-spacers 410 to the number of the sub-pixels 402 is 1: 3. if the number of sub-spacers 410 is too large, for example, the ratio of the number of sub-spacers 410 to the number of sub-pixels 402 is higher than 1: 3 (i.e., more than one sub-spacer 410 for every three sub-pixels 402), the aperture ratio of the pixel 400 of the display device 100 is difficult to increase and the transmittance is difficult to improve. However, if the number of sub-spacers 410 is too small, for example, the ratio of the number of sub-spacers 410 to the number of sub-pixels 402 is lower than 1: 3 (i.e., less than one sub-spacer 410 per three sub-pixels 402), it is difficult to provide good structural stability of the display device 100.

In addition, the ratio of the number of sub-spacers 410 to the number of sub-pixels 402 also affects the contrast and transmittance of the display device 100. For example, in one embodiment, the ratio of the number of sub-spacers 410 to the number of sub-pixels 402 is determined by the ratio of 1: 1 is changed into 1: 3, the contrast of the display device 100 is increased from 909 to 998, and the transmittance is increased from 2.8% to 3.1%. It can be seen that the specific ratio of the number of sub-spacers 410 to the number of sub-pixels 402 (i.e. 1: 3) of the present invention has unexpected effects compared to the ratio of the number of sub-spacers 410 to the number of sub-pixels 402 (i.e. 1: 1) of the conventional display device.

In addition, with continued reference to FIG. 43, any sub-spacer 410 is separated from the nearest sub-spacer 410 by three columns of sub-pixels 402, which prevents the occurrence of a mura display mura.

In addition, the embodiment of fig. 43 differs from the previously described embodiments of fig. 40A-42B in that the inclination direction of the adjacent sub-pixel columns 402R is different. In detail, as shown in fig. 43, all the subpixels 402 in the subpixel row 402R1 are inclined to the left side of fig. 43, and all the subpixels 402 in the subpixel row 402R2 adjacent to the subpixel row 402R1 are inclined to the right side of fig. 43. This configuration may further reduce parallax problems for the display device 100.

In addition, the enlarged parts 406 with specific number ratio or specific arrangement mode can be adjusted to further prevent the occurrence of the phenomenon of uneven display of visual fringe feeling caused by the enlarged parts 406, so that the display quality can be further improved. In detail, in an embodiment, each pixel of the display device includes three sub-pixels, the light-shielding layer includes a plurality of enlarged portions, and a ratio of the number of the enlarged portions to the number of the sub-pixels is about 1: 12 to 1: 18, the specific ratio of the amounts further prevents the development unevenness.

If the number of enlarged portions is too large, for example, the ratio of the number of enlarged portions to the number of sub-pixels is greater than about 1: 12 (i.e., more than one enlarged portion per 12 sub-pixels) may result in insufficient transmittance of the display device 100. However, if the number of the enlarged portions is too small, for example, the ratio of the number of the enlarged portions to the number of the sub-pixels is less than about 1: 18 (i.e., less than one enlarged portion per 18 sub-pixels), the enlarged portions tend to cause the display device 100 to have a visual streaking effect.

The present invention will be described in two embodiments below to describe the enlarged portions with a specific number ratio and a specific arrangement. Referring first to fig. 44, a top view of a display device 100 according to an embodiment of the invention is shown. FIG. 44 shows a sub-pixel region 416 consisting of 108 sub-pixels 402, where the sub-pixel region 416 has 18 sub-pixel columns 402C and 6 sub-pixel rows 402R. In this sub-pixel region 416, the ratio of the number of enlarged portions 406 to the number of sub-pixels 402 is 1: 18. the enlarged portion 406 is disposed between the two sub-pixel columns 402C and between the two sub-pixel rows 402R.

In the sub-pixel region 416, the number of enlarged portions 406 between every two adjacent sub-pixel columns 402C is 1 or less, and the number of enlarged portions 406 between every two adjacent sub-pixel rows 402R is 1 or less. In other words, only one enlarged portion 406 is disposed between every two adjacent sub-pixel columns 402C, and only one enlarged portion 406 is disposed between every two adjacent sub-pixel rows 402R. And any one of the enlarged portions 406 is separated from the nearest other enlarged portion 406 by three sub-pixel columns 402C.

Furthermore, the display device 100 of fig. 44 includes at least one main spacer 142, and all the main spacers 142 have the enlarged portions 406 in the corresponding regions. In addition, the display device 100 of fig. 44 further includes at least one secondary spacer 410, and the region corresponding to the partially enlarged portion 406 is disposed with the secondary spacer 410. However, the other part of the enlarged portion 406 corresponds to a region without the main spacers 142 and the sub spacers 410. In addition, the enlarged portion 406 is not provided in the region corresponding to a part of the sub-spacers 410.

The enlarged portions 406 with specific number ratios and specific arrangement shown in fig. 44 can further prevent the occurrence of the phenomenon of uneven display (mura) and further improve the display quality.

Next, referring to fig. 45, a top view of the display device 100 according to an embodiment of the invention is shown. FIG. 45 shows a sub-pixel region 416 consisting of 12 sub-pixels 402, and the sub-pixel region 416 has 6

sub-pixel columns

402C and 2 sub-pixel rows 402R. The ratio of the number of the summing parts 406 to the number of the sub-pixels 402 in this sub-pixel region 416 is 1: 12. the enlarged portion 406 is disposed in one of the corners of each sub-pixel region 416.

Furthermore, the display device 100 of fig. 45 includes at least one main spacer 142, and all the main spacers 142 have the enlarged portions 406 in the corresponding regions. In addition, the display device 100 of fig. 45 further includes at least one secondary spacer 410, and the region corresponding to the partially enlarged portion 406 is disposed with the secondary spacer 410. However, the other part of the enlarged portion 406 corresponds to a region without the main spacers 142 and the sub spacers 410. In addition, the enlarged portion 406 (not shown in fig. 45) is not disposed in the region corresponding to a part of the sub-spacers 410.

The enlarged portions 406 with a specific number ratio and a specific arrangement shown in fig. 45 can further prevent the occurrence of the phenomenon of uneven display (mura) and further improve the display quality.

In addition, it should be noted that although in the above embodiments of fig. 40A-42B and fig. 44-45, all the sub-pixels in the adjacent sub-pixel columns are arranged in the same direction, the sub-pixels of the display device of the present invention may be arranged in the arrangement shown in fig. 43, that is, in the arrangement in which the inclination directions of the adjacent sub-pixel columns are different. The scope of the present invention is not limited to the embodiments shown in fig. 40A-42B and fig. 44-45.

In addition, although in the above embodiments of fig. 40A to 45, the first substrate is used as the color filter substrate, and the second substrate is used as the transistor substrate. However, it can be understood by those skilled in the art that the first substrate is also a transistor substrate, and the second substrate is a color filter substrate, as shown in fig. 46. The scope of the present invention is not limited to the embodiments shown in fig. 40A-45.

Referring to fig. 46, the first substrate 101 of the display device 100 is a transistor substrate, and the second substrate 103 is a color filter substrate. The main spacer 142 and the sub-spacer 410 are disposed on the first substrate 101 as a transistor substrate, and the first alignment layer 148 covers the first substrate 101, the main spacer 142 and the sub-spacer 410. The second substrate 103 as a color filter substrate includes a second transparent substrate 134, a light-shielding layer 128 disposed on the second transparent substrate 134, and a color filter layer 130 disposed on the light-shielding layer 128. The second alignment layer 150 is disposed on the color filter layer 130. The material of the second transparent substrate 134 can be the same as the material of the first transparent substrate 126.

Although the present invention has been disclosed in conjunction with the above embodiments, it should be understood that many modifications, substitutions and alterations may be made thereto without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but it is to be understood that any process, machine, manufacture, composition of matter, means, method and steps, presently existing or later to be developed, that will be obvious to one skilled in the art from this disclosure may be utilized according to the present application as many equivalents of the presently available embodiments of the present application are possible. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, or steps described in the specification. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes combinations of the respective claims and embodiments.

Claims

1. A display device, comprising:

a substrate;

a data line disposed on the substrate and extending in one direction;

another substrate disposed opposite to the substrate;

the frame glue is arranged between the substrate and the other substrate;

the first spacer is arranged in the frame glue;

the common electrode is arranged on the substrate and provided with a first opening, wherein the first opening is provided with an arc shape and has a first width in the direction;

a pixel electrode disposed on the substrate, wherein the pixel electrode has an overlap with the first opening and the overlap has a second width in the direction, and the first width is greater than the second width;

a main spacer and a sub spacer between the substrate and the other substrate; and

and a light shielding layer disposed on the other substrate and having a plurality of enlarged portions, wherein at least one of the enlarged portions does not correspond to the primary spacer and the secondary spacer.

2. The display device of claim 1, further comprising a planarization layer disposed on the substrate and having a second opening, wherein the second opening overlaps the first opening.

3. The display device of claim 2, further comprising a first passivation layer disposed between the planarization layer and the substrate and having a third opening, wherein the third opening overlaps the first opening and the second opening.

4. The display device of claim 1, further comprising an active layer disposed on the substrate and overlapping the first opening.

5. The display apparatus of claim 4, wherein an area of the active layer overlapping the first opening is smaller than an area of the active layer.

6. The display device of claim 1, further comprising a conductive ring disposed on the substrate, wherein the conductive ring comprises a first conductive block and a second conductive block, and the first conductive block and the second conductive block partially overlap.

7. The display device of claim 1, further comprising:

the first alignment layer is arranged on the substrate, wherein the first alignment layer is aligned by a photo-alignment manufacturing process.

8. The display apparatus of claim 1, wherein at least one of the enlarged portions corresponds to the main spacer.

9. The display apparatus of claim 1, wherein the enlarged portions do not correspond to the main spacers.

10. The display apparatus of claim 1, wherein the substrate has a sidewall and the another substrate has a sidewall, wherein the sidewall of the substrate and the sidewall of the another substrate are non-planar.

11. The display apparatus of claim 2, wherein a first distance between the first opening and the data line is different from a second distance between the second opening and the data line, wherein the first opening has a first bottom near the substrate and the second opening has a second bottom near the substrate, wherein the first distance is a distance from the first bottom to the data line and the second distance is a distance from the second bottom to the data line.

12. The display device according to claim 2, further comprising a second protective layer disposed between the common electrode and the pixel electrode and having a fourth opening, wherein a center line position of a bottom of the second opening is different from a center line position of a bottom of the fourth opening.

13. A display device, comprising:

a substrate;

another substrate disposed opposite to the substrate;

the frame glue is arranged between the substrate and the other substrate;

the first spacer is arranged in the frame glue;

14. The display device of claim 13, further comprising a second spacer disposed in the sealant and having a distance from the first spacer.

15. The display device of claim 13, further comprising a conductive loop disposed on the substrate, wherein the conductive loop comprises a first conductive block and a second conductive block and the first conductive block and the second conductive block partially overlap.

16. The display device of claim 13, further comprising:

17. The display apparatus of claim 13, wherein the enlarged portions do not correspond to the main spacers.

18. The display apparatus of claim 13, wherein the substrate has a sidewall and the another substrate has a sidewall, the sidewall of the substrate and the sidewall of the another substrate being non-planar.

19. The display device of claim 13, further comprising:

a data line disposed on the substrate and extending in one direction;

a common electrode disposed on the substrate and having a first opening; and

the flat layer is disposed on the substrate and has a second opening, wherein a first distance between the first opening and the data line is different from a second distance between the second opening and the data line, the first opening has a first bottom portion near the substrate, and the second opening has a second bottom portion near the substrate, wherein the first distance is a distance from the first bottom portion to the data line and the second distance is a distance from the second bottom portion to the data line.

20. The display device according to claim 19, further comprising a protective layer provided between the common electrode and the pixel electrode and having a third opening, wherein a center line position of a bottom of the second opening is different from a center line position of a bottom of the third opening.