TWI471663B - Display panel - Google Patents

Description

Display panel

The present invention relates to a display panel, and more particularly to a display panel having a barrier pattern layer that prevents spacers from moving.

A display panel, such as a liquid crystal display panel, is mainly composed of an array substrate, a counter substrate, and a liquid crystal layer disposed therebetween. The thickness of the liquid crystal layer (generally referred to as a liquid crystal gap) has a great influence on the brightness, contrast, and reaction time of the liquid crystal display panel. Therefore, if the thickness of the liquid crystal layer varies depending on the preset value, the display quality is seriously affected. Since the liquid crystal layer is in a liquid state, the thickness of the liquid crystal layer is mainly controlled by a spacer provided between the array substrate and the opposite substrate. However, in the conventional liquid crystal display panel, during the assembly, handling or use, the spacer may move to cause the liquid crystal gap to mutate or cause the alignment film to be damaged, so that the display quality is degraded.

One of the objects of the present invention is to provide a display panel having a barrier pattern layer for blocking the movement of spacers to improve the display quality of the display panel.

An embodiment of the present invention provides a display panel including a first substrate, a gate line, a data line, an active switching element, a pixel electrode, a dielectric layer, a common electrode, and a conductive pattern layer. a second substrate, a display medium layer and a spacer. The gate line, the data line, and the active switching element are disposed on the first substrate. The pixel electrode is disposed on the first substrate, and the pixel electrode is electrically connected to the gate line and the data line by the active switching element. The dielectric layer is disposed on the first substrate and covers the gate line, the data line, and the active switching element. The common electrode is disposed on the dielectric layer, and the common electrode has a first resistance value. The conductive pattern layer is disposed on the dielectric layer, and the conductive pattern layer has a second resistance value lower than the first resistance value of the common electrode. The conductive pattern layer includes a common line electrically connected to the common electrode, and a barrier pattern layer is located above the gate line. The second substrate is disposed facing the first substrate. The display medium layer is disposed between the first substrate and the second substrate. The spacer is disposed between the first substrate and the second substrate. The barrier pattern layer is disposed on at least one side of the spacer to block the spacer from moving.

Another embodiment of the present invention provides a display panel including a first substrate, a gate line, a data line, an active switching element, a protective layer, a flat layer, a common electrode, a conductive pattern layer, and a a dielectric layer, a pixel electrode, a second substrate, a display dielectric layer, and a spacer. The gate line, the data line, and the active switching element are disposed on the first substrate. The protective layer is disposed on the first substrate and covers the gate line, the data line, and the active switching element. The flat layer is disposed on the protective layer. The common electrode is disposed on the first substrate, and the common electrode has a first resistance value. The conductive pattern layer is disposed on the flat layer, and the conductive pattern layer has a second resistance value lower than the first resistance value of the common electrode. The conductive pattern layer includes a common line electrically connected to the common electrode; and the barrier pattern layer is located above the gate line. The dielectric layer is disposed on the flat layer and covers the conductive pattern layer. The pixel electrode is disposed on the dielectric layer, and the pixel electrode is electrically connected to the gate line and the data line by the active switching element. The second substrate is disposed facing the first substrate. Display medium layer is set at first base Between the board and the second substrate. The spacer is disposed between the first substrate and the second substrate. The barrier pattern layer is disposed on at least one side of the spacer to block the spacer from moving.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figure 1 and Figure 2. Fig. 1 is a top plan view showing a display panel according to a first embodiment of the present invention, and Fig. 2 is a cross-sectional view taken along line A-A' and line B-B' of Fig. 1; In order to simplify the description, FIGS. 1 and 2 only show a single pixel of the display panel. In addition, the display panel of the present invention may be various non-self-luminous display panels such as liquid crystal display panels, and is not limited thereto. As shown in FIGS. 1 and 2, the display panel 1 of the present embodiment includes a first substrate 10, a gate line GL, a data line DL, an active switching element SW, a pixel electrode 12, and a dielectric layer 14 (first (not shown), the common electrode 26, the conductive pattern layer 16, the second substrate 30 (not shown in FIG. 1), the display medium layer 18 (not shown in FIG. 1), and a spacer 20 (not shown in FIG. 1) ). The first substrate 10 and the second substrate 30 are disposed facing each other, and the first substrate 10 and the second substrate 30 may respectively comprise a rigid substrate such as a glass substrate or a flexible substrate such as a plastic substrate, but limit. In the present embodiment, the first substrate 10 is used as an array substrate (also referred to as a thin film transistor substrate), and the second substrate 30 is used as a counter substrate. The gate line GL, the data line DL, and the active switching element SW are disposed on the first substrate 10. The active switching element SW can be implemented by a thin film transistor element, and the active switching element SW includes a gate G, The gate insulating layer 22 (not shown in FIG. 1), the semiconductor layer 24, the source S, and the drain D. The gate G is electrically connected to the gate line GL. The gate insulating layer 22 is located between the gate G and the semiconductor layer 24. The source S and the drain D are disposed on the gate insulating layer 22, and are respectively located on both sides of the semiconductor layer 24, and the source S and the drain D The semiconductor layer 24 is electrically connected to each other. The source S is electrically connected to the data line DL, and the drain D is electrically connected to the pixel electrode 12 via the opening 22A of the gate insulating layer 22. The material of the semiconductor layer 24 may be, for example, an amorphous semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, a single crystal semiconductor, a nanocrystalline semiconductor, an organic semiconductor, or a metal oxide semiconductor layer, or other suitable semiconductor material, or the above semiconductor material. The combination. In this embodiment, the thin film transistor element is a bottom gate thin film transistor element, and thus the gate line GL and the gate G may be composed of a first metal layer (generally referred to as metal 1), and the data line DL, source S and drain D may be formed by a second metal layer (generally referred to as metal 2), but are not limited thereto. In other variant embodiments, the thin film transistor element can also be a top gate type (thin gate) or other type of thin film transistor element.

The pixel electrode 12 is disposed on the first substrate 10, and the pixel electrode 12 is electrically connected to the gate line GL and the data line DL by the active switching element SW. The pixel electrode 12 is preferably a transparent electrode, and the material thereof may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO) or other suitable transparent conductive material. Alternatively, the pixel electrode 12 may optionally include a patterned metal material layer (not shown) to further reduce the resistance value of the pixel electrode 12. The pixel electrode 12 of this embodiment is located between the first substrate 10 and the gate insulating layer 22. The dielectric layer 14 is disposed on the first substrate 10 and covers the gate line GL, the data line DL, and the active switching element SW. The dielectric layer 14 of this embodiment may be an inorganic dielectric layer such as a hafnium oxide layer or nitrided. The ruthenium layer or the ruthenium oxynitride layer, and it may be a conformal layer, but is not limited thereto. The common electrode 26 is disposed on the dielectric layer 14. The common electrode 26 is preferably a transparent electrode, and the material thereof may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO) or other suitable transparent conductive material. The common electrode 26 has a plurality of slits 26S, and the pixel electrode 12 is a planar electrode, but is not limited thereto. The conductive pattern layer 16 is disposed on the dielectric layer 14. In this embodiment, the common electrode 26 has a first resistance value, and the conductive pattern layer 16 has a second resistance value lower than the first resistance value of the common electrode 26, and the second resistance value can be, for example, the first resistance value. 1/5~1/10000, etc., but not limited to this. The conductive pattern layer 16 may be an opaque conductive pattern layer such as a metal pattern layer or an alloy pattern layer, or the conductive pattern layer 16 may be a transparent conductive pattern layer formed, for example, by laminating a thin metal and a transparent conductive material. The conductive pattern layer 16 includes a common line CL electrically connected to the common electrode 26, and the barrier pattern layer 28 is located above the gate line GL. In this embodiment, the common line CL may be a strip-shaped conductor structure that is disposed in parallel with the data line DL and partially overlaps, but is not limited thereto. In other variant embodiments, the common line CL may be a grid-like conductor structure that partially overlaps the data line DL and the gate line GL. The common electrode 26 is electrically connected to the common line CL in direct contact with the common line CL, and the common electrode 26 is preferably formed after the common line CL, whereby the common electrode 26 can be directly overlapped on the common line CL to form an electrical connection. In other variant embodiments, the common line CL may be formed before the common electrode 26, whereby the common line CL may be directly overlapped on the common electrode 26 to form an electrical connection. In addition, in the embodiment, the barrier pattern layer 28 is not connected to the common line CL, but is not limited thereto. In other variant embodiments, the barrier pattern layer 28 can also be connected to the common line CL.

The display medium layer 18 is disposed between the first substrate 10 and the second substrate 30. Display The layer 18 may include a liquid crystal layer, but may be other display medium layers depending on the type of display panel, such as an organic light emitting material layer, a reflective electrophoretic material layer, or an electrowetting material layer. The spacer 20 is disposed between the first substrate 10 and the second substrate 30. The structure of the spacer 20 may be a cylindrical structure, a corner column structure or a structure of other shapes. The spacer 20 is preferably disposed on the second substrate 30 and faces the first substrate 10, and the spacer 20 is in contact with the first substrate 10 to maintain a gap between the first substrate 10 and the second substrate 30. That is, the spacer 20 is fixed to the second substrate 30, but only contacts the first substrate 10 and is not completely fixed to the first substrate 10. The display panel 1 further includes a light shielding pattern layer 32, a color filter 34 and an overcoat layer 36, a surface of the second substrate 30 facing the first substrate 10, and a transparent shielding layer (not shown). And disposed on an outer surface of the second substrate 30. The light shielding pattern layer 32 may be, for example, a black matrix pattern. The color filter 34 may include color filter patterns of different colors such as a red filter pattern, a green filter pattern, a blue filter pattern, and the like.

The barrier pattern layer 28 is disposed on at least one side of the spacer 20. For example, in the embodiment, the barrier pattern layer 28 is disposed on one side of the spacer 20, and specifically, the barrier pattern layer 28 is disposed on the side of the spacer 20 near the pixel electrode 12, but is not limited thereto. . For example, the barrier pattern layer 28 can be disposed on either side of the spacer 20, on either side, on any three sides, or around the spacer 20. When the spacer 20 moves toward the barrier pattern layer 28, it is restricted by the barrier pattern layer 28 such that the displacement amount of the spacer 20 is within an acceptable range, thus not affecting the first substrate 10 and the second The gap of the substrate 30 may not cause damage to the alignment film (not shown). The thickness d of the barrier pattern layer 28 should be sufficient to limit the movement of the spacer 20, for example, the thickness of the barrier pattern layer 28. The degree d may be substantially between 0.1 micrometers and 10 micrometers, but is not limited thereto. In addition, a gap g is formed between the barrier pattern layer 28 and the spacer 20, and the size of the gap g can be adjusted by the assembly error of the first substrate 10 and the second substrate 30 or other factors. For example, the gap g between the barrier pattern layer 28 and the spacer 20 is about 3 micrometers, but not limited thereto. Furthermore, since the barrier pattern layer 28 and the common line CL are both formed of the conductive pattern layer 16, they can be formed using the same film layer and the lithography process without increasing the manufacturing cost. In addition, in the embodiment, the spacers 20 are preferably overlapped with the light shielding pattern layer 32 in the vertical projection direction, and the spacers 20 may also be in the vertical projection direction with the gate lines GL, the data lines DL or the active switching elements SW. The overlapping, whereby the spacer 20 does not affect the aperture ratio of the display panel 1. In addition, the barrier pattern layer 28 preferably overlaps the light-shielding pattern layer 32 in the vertical projection direction, whereby the barrier pattern layer does not affect the aperture ratio of the display panel 1.

The display panel of the present invention is not limited to the above embodiment. Hereinafter, the electroluminescent display panel of other preferred embodiments or modified embodiments of the present invention will be sequentially described, and the same symbols are used in the following embodiments in order to facilitate the comparison of the differences of the embodiments and simplify the description. The same elements are denoted by the same, and the differences between the embodiments are mainly explained, and the repeated parts will not be described again.

Please refer to Figure 3. Fig. 3 is a schematic view showing a display panel of a first variation of the first embodiment of the present invention. As shown in FIG. 3, the barrier pattern layer 28 of the display panel 2 of the first variation embodiment is disposed on the side of the spacer 20 away from the pixel electrode 12.

Please refer to Figure 4. Fig. 4 is a schematic view showing a display panel of a second variation of the first embodiment of the present invention. As shown in FIG. 4, the barrier pattern layer 28 of the display panel 3 of the second variation embodiment is disposed on opposite sides of the spacer 20. To be precise, the barrier pattern layer 28 is disposed on the side of the spacer 20 adjacent to the pixel electrode 12 and the other side away from the pixel electrode 12.

Please refer to Figure 5. Fig. 5 is a schematic view showing a display panel of a third variation of the first embodiment of the present invention. As shown in FIG. 5, the barrier pattern layer 28 of the display panel 4 of the third variation embodiment is disposed on the side of the spacer 20 adjacent to the active switching element SW and the other side away from the active switching element SW.

Please refer to Figure 6. Fig. 6 is a view showing a display panel of a fourth variation of the first embodiment of the present invention. As shown in FIG. 6, the barrier pattern layer 28 of the display panel 5 of the fourth variation embodiment surrounds the spacer 20. In addition, in the fourth variation embodiment, the common line CL may be a grid-like conductor structure and electrically connected to the barrier pattern layer 28. In other implementations, the barrier pattern layer 28 can surround the spacer 20 but is not electrically connected to the common line CL.

The above embodiment discloses different shapes and configurations of the barrier pattern layer 28. However, the shape and configuration of the barrier pattern layer 28 are not limited to the above, and the visual design is different.

Please refer to Figure 7. Figure 7 is a schematic view showing a display panel of a second embodiment of the present invention. As shown in FIG. 7 , unlike the first embodiment, the pixel electrode 12 of the display panel 6 of the present embodiment is disposed between the gate insulating layer 22 and the dielectric layer 14 , and the pixel electrode 12 can directly The bungee D is in contact and electrically connected. For example, the pixel electrode 12 may be overlapped on the drain D, or the drain D may be overlapped on the pixel electrode 12. In this embodiment, the barrier pattern layer 28 is disposed on the side of the spacer 20 adjacent to the pixel electrode 12, but is not limited thereto. The configuration of the barrier pattern layer 28 may be selected from any of the different variations of the modes disclosed in Figures 3 through 6 or other configurations depending on the blocking capability of the spacers 20 or other factors.

Please refer to Figure 8. Figure 8 is a schematic view showing a display panel of a third embodiment of the present invention. As shown in FIG. 8, the display panel 7 of the present embodiment further includes a flat layer 38 and a protective layer 40, unlike the first and second embodiments. The protective layer 40 is disposed on the first substrate 10 and covers the gate line GL, the data line DL, and the active switching element SW. The flat layer 38 is disposed between the dielectric layer 14 and the protective layer 40, and the pixel electrode 12 is located. Between the flat layer 38 and the dielectric layer 14. The protective layer 40 has an opening 40A exposing a portion of the drain D, the flat layer 38 has an opening 38A exposing a portion of the drain D, and the pixel electrode 12 is in contact with and electrically connected to the drain D through the opening 38A and the opening 40A. In this embodiment, the dielectric layer 14 and the protective layer 40 may preferably be an inorganic dielectric layer such as a hafnium oxide layer, a tantalum nitride layer or a hafnium oxynitride layer, but not limited thereto; the planar layer 38 is preferably It can be an organic dielectric layer such as an acryl layer. In this embodiment, the barrier pattern layer 28 is disposed on the side of the spacer 20 adjacent to the pixel electrode 12, but is not limited thereto. The configuration of the barrier pattern layer 28 may be selected from the blocking ability of the spacer 20 or other factors. Any of the different variations of the implementations disclosed in FIG. 6 or other configurations.

Please refer to Figure 9. Figure 9 is a schematic view showing a display panel of a fourth embodiment of the present invention. As shown in FIG. 9, unlike the first, second, and third embodiments, the display panel 8 of the present embodiment includes a first substrate 10, a gate line GL, a data line DL, an active switching element SW, and a pixel electrode. 12. A dielectric layer 14, a protective layer 40, a planarization layer 38, a common electrode 26, a conductive pattern layer 16, a second substrate 30 (not shown in FIG. 1), a display dielectric layer 18, and a spacer 20. The protective layer 40 is disposed on the first substrate 10 and covers the gate line GL, the data line DL, and the active switching element SW. The flat layer 38 is disposed on the protective layer 40. The common electrode 26 is disposed on the first substrate. To be precise, the common electrode 26 is disposed between the flat layer 38 and the dielectric layer 14. The pixel electrode 12 is disposed on the dielectric layer 14. The protective layer 40 has an opening 40A exposing a portion of the drain D, the flat layer 38 has an opening 38A exposing a portion of the drain D, the dielectric layer 14 has an opening 14A exposing a portion of the drain D, and the pixel electrode 12 is opened through the opening 40A, the opening 38A and the opening 14A are in contact with and electrically connected to the drain D. In addition, the pixel electrode 12 is electrically connected to the gate line GL and the data line DL by the active switching element SW. In this embodiment, the pixel electrode 12 has a plurality of slits 12S, and the common electrode 26 is a planar electrode, but is not limited thereto. The common electrode 26 has a first resistance value, and the conductive pattern layer 16 has a second resistance value lower than the first resistance value of the common electrode 26, and the second resistance value can be, for example, 1/5~1 of the first resistance value. /10000, etc., but not limited to this. The barrier pattern layer 28 is disposed on at least one side of the spacer 20. For example, in the embodiment, the barrier pattern layer 28 is disposed on the side of the spacer 20 adjacent to the pixel electrode 12, but is not limited thereto. The configuration of the barrier pattern layer 28 may be selected depending on the blocking ability of the spacer 20 or other factors. Any of the different variations of the embodiment disclosed in Figures 3 through 6 or other configurations.

In summary, the display panel of the present invention utilizes the barrier pattern layer to block the spacer from moving, thereby avoiding the problem that the gap between the first substrate and the second substrate is changed or the alignment film is damaged due to the movement of the spacer. In turn, the display quality is improved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1‧‧‧ display panel

10‧‧‧First substrate

GL‧‧‧ gate line

DL‧‧‧ data line

SW‧‧‧active switching elements

12‧‧‧ pixel electrodes

14‧‧‧Dielectric layer

16‧‧‧conductive pattern layer

18‧‧‧ Display media layer

20‧‧‧ spacers

22‧‧‧ gate insulation

24‧‧‧Semiconductor layer

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

22A‧‧‧ openings

26‧‧‧Common electrode

26S‧‧‧Slit

CL‧‧‧Common line

28‧‧‧Block pattern layer

30‧‧‧second substrate

32‧‧‧Lighting pattern layer

34‧‧‧Color filters

36‧‧‧ Coverage

D‧‧‧thickness

g‧‧‧Void

38‧‧‧flat layer

40‧‧‧Protective layer

12S‧‧‧Slit

38A‧‧‧ openings

40A‧‧‧ openings

14A‧‧‧ openings

3‧‧‧ display panel

2‧‧‧ display panel

4‧‧‧ display panel

5‧‧‧ display panel

6‧‧‧ display panel

7‧‧‧ display panel

8‧‧‧ display panel

FIG. 1 is a top plan view showing a display panel according to a first embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view taken along line A-A' and line B-B' of Fig. 1.

Fig. 3 is a schematic view showing a display panel of a first variation of the first embodiment of the present invention.

Fig. 4 is a schematic view showing a display panel of a second variation of the first embodiment of the present invention.

Fig. 5 is a schematic view showing a display panel of a third variation of the first embodiment of the present invention.

Fig. 6 is a view showing a display panel of a fourth variation of the first embodiment of the present invention.

Figure 7 is a schematic view showing a display panel of a second embodiment of the present invention.

Figure 8 is a schematic view showing a display panel of a third embodiment of the present invention.

Figure 9 is a schematic view showing a display panel of a fourth embodiment of the present invention.

1‧‧‧ display panel

10‧‧‧First substrate

DL‧‧‧ data line

CL‧‧‧Common line

SW‧‧‧active switching elements

12‧‧‧ pixel electrodes

14‧‧‧Dielectric layer

16‧‧‧conductive pattern layer

18‧‧‧ Display media layer

20‧‧‧ spacers

22‧‧‧ gate insulation

24‧‧‧Semiconductor layer

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

22A‧‧‧ openings

26‧‧‧Common electrode

26S‧‧‧Slit

28‧‧‧Block pattern layer

30‧‧‧second substrate

32‧‧‧Lighting pattern layer

34‧‧‧Color filters

36‧‧‧ Coverage

g‧‧‧Void

D‧‧‧thickness

GL‧‧‧ gate line

Claims (24)

A display panel includes: a first substrate; a gate line, a data line, and an active switching element disposed on the first substrate; a pixel electrode disposed on the first substrate, wherein the pixel The electrode is electrically connected to the gate line and the data line by the active switching element; a dielectric layer is disposed on the first substrate and covers the gate line, the data line and the active switching element; a common electrode Provided on the dielectric layer, the common electrode has a first resistance value; a conductive pattern layer is disposed on the dielectric layer, the conductive pattern layer has a second resistance value lower than the common electrode a first resistance value, the conductive pattern layer includes: a common line electrically connected to the common electrode; and a barrier pattern layer located above the gate line; a second substrate facing the first substrate; a display medium layer disposed between the first substrate and the second substrate; and a spacer disposed between the first substrate and the second substrate; wherein the barrier pattern layer is disposed on the At least one of the spacers , To block movement of the spacer was produced. The display panel of claim 1, wherein the active switching element comprises a gate, a gate insulating layer, a semiconductor layer, a source and a drain, the gate insulating layer is located at the gate and the semiconductor Between the layers, the source and the drain are located on opposite sides of the semiconductor layer, and the source and the drain are electrically connected to the semiconductor layer, respectively. The display panel of claim 2, wherein the pixel electrode is located between the first substrate and the gate insulating layer. The display panel of claim 2, wherein the pixel electrode is between the gate insulating layer and the dielectric layer. The display panel of claim 2, further comprising a flat layer and a protective layer, wherein the protective layer is disposed on the first substrate and covers the gate line, the data line, and the active switching element, the flat layer And disposed between the dielectric layer and the protective layer, and the pixel electrode is located between the planar layer and the dielectric layer. The display panel of claim 1, wherein the barrier pattern layer and the gate line overlap in a vertical projection direction. The display panel of claim 1, further comprising a light shielding pattern layer disposed on the second substrate, wherein the spacer and the light shielding pattern layer overlap in a vertical projection direction. The display panel of claim 7, wherein the barrier pattern layer and the light shielding pattern layer overlap in the vertical projection direction. The display panel of claim 1, wherein the barrier pattern layer is disposed at the interval The opposite side of the object. The display panel of claim 1, wherein the barrier pattern layer surrounds the spacer. The display panel of claim 1, wherein the barrier pattern layer is electrically connected to the common line. The display panel of claim 1, wherein the barrier pattern layer has a gap between the spacer and the spacer. The display panel of claim 1, wherein the barrier pattern layer has a thickness substantially between 0.1 micrometers and 10 micrometers. The display panel of claim 1, wherein the spacer is disposed on the second substrate and faces the first substrate. A display panel includes: a first substrate; a gate line, a data line, and an active switching element disposed on the first substrate; a protective layer disposed on the first substrate and covering the gate line The data line and the active switching element; a flat layer disposed on the protective layer; a common electrode disposed on the first substrate, the common electrode having a first resistance a conductive pattern layer disposed on the flat layer, the conductive pattern layer having a second resistance value lower than the first resistance value of the common electrode, the conductive pattern layer comprising: a common line, common to the common An electrode is electrically connected; and a barrier pattern layer is disposed above the gate line; a dielectric layer is disposed on the planar layer to cover the conductive pattern layer; and a pixel electrode is disposed on the dielectric layer, wherein The pixel electrode is electrically connected to the gate line and the data line by the active switching element; a second substrate is disposed facing the first substrate; a display medium layer is disposed on the first substrate and the first substrate Between the two substrates; and a spacer disposed between the first substrate and the second substrate; wherein the barrier pattern layer is disposed on at least one side of the spacer to block the spacer from being generated mobile. The display panel of claim 15, wherein the barrier pattern layer and the gate line overlap in a vertical projection direction. The display panel of claim 15, further comprising a light shielding pattern layer disposed on the second substrate, wherein the spacer and the light shielding pattern layer overlap in a vertical projection direction. The display panel of claim 17, wherein the barrier pattern layer and the light shielding pattern layer overlap in the vertical projection direction. The display panel of claim 15, wherein the barrier pattern layer is disposed on opposite sides of the spacer. The display panel of claim 15, wherein the barrier pattern layer surrounds the spacer. The display panel of claim 15, wherein the barrier pattern layer is electrically connected to the common line. The display panel of claim 15, wherein the barrier pattern layer has a gap between the spacer and the spacer. The display panel of claim 15, wherein the barrier pattern layer has a thickness substantially between 0.1 micrometers and 10 micrometers. The display panel of claim 15, wherein the spacer is disposed on the second substrate and faces the first substrate.