TWI571682B - Display device - Google Patents

Description

Display device

The present invention relates to display devices, and more particularly to a display device having a partition wall.

With the development of digital technology, display devices have been widely used in various aspects of daily life, for example, they have been widely used in modern information equipment such as televisions, notebooks, computers, mobile phones, smart phones, etc., and are constantly moving toward light. , thin, short and fashion development.

The display device generally includes a display pixel area and a non-display area, and the sealant disposed in the non-display area must be spaced apart from the display pixel area by a certain distance to prevent the frame glue from contacting the liquid crystal material of the display pixel area to cause defects of the display device. . However, the above distance limits the narrowing of the non-display area of the display device, making the display device impossible to be lighter, thinner, and shorter.

Therefore, there is a need in the industry for a display device that can further narrow the non-display area.

The present invention provides a display device comprising: a first substrate comprising a display pixel region; a second substrate disposed opposite the first substrate; a sealant disposed between the first substrate and the second substrate and located Displaying the outside of the pixel area; and a photo spacer wall disposed between the first substrate and the second substrate and located at the display Between the pixel area and the frame glue, the first side of the partition wall is close to the display pixel area, and the second side of the partition wall is close to the frame glue, and the height of the first side is greater than the height of the second side.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below.

100‧‧‧ display device

101‧‧‧First substrate

102‧‧‧Substrate

103‧‧‧second substrate

104‧‧‧ Displaying the pixel area

105‧‧‧Non-display area

106‧‧‧Drive unit

107‧‧‧ gate drive circuit

108‧‧‧Drop area

108a‧‧‧First line area

108b‧‧‧second line area

109‧‧‧Test pad

110‧‧‧Line/Signal Line Group

110A‧‧‧ lines

110B‧‧‧ lines

110C‧‧‧First block line

110D‧‧‧Second block circuit

111‧‧‧gate signal output contact

112‧‧‧First wire

113A‧‧‧Area

113B‧‧‧Area

114‧‧‧Second wire

115‧‧‧External pin connection area

116‧‧‧First conductive ring

118‧‧‧second conductive ring

120‧‧‧Box glue

122‧‧‧ peripheral border

124‧‧‧ Scheduled cutting road

126‧‧‧First transparent substrate

128‧‧‧ shading layer

130‧‧‧Color filter layer

130A‧‧‧Color filter layer

130B‧‧‧Color filter layer

130C‧‧‧Color filter layer

130D‧‧‧First color filter layer

130E‧‧‧Second color filter layer

132‧‧‧flat layer

134‧‧‧Second transparent substrate

136‧‧‧Insulation

138‧‧‧Liquid crystal materials

140‧‧‧ partition wall

142‧‧‧Main spacer

144‧‧‧ corner area

146‧‧‧Long strip area

148‧‧‧First alignment layer

150‧‧‧Second alignment layer

202‧‧‧First conductive block

204‧‧‧Second conductive block

205‧‧‧ first through hole

206‧‧‧Dielectric layer

206A‧‧‧ dielectric layer

206B‧‧‧ dielectric layer

207‧‧‧second through hole

208‧‧‧protection layer

209‧‧‧Through hole

210‧‧‧ Conductive layer

210‧‧‧fourth hole

211‧‧‧Connection layer

212‧‧‧flat layer

213‧‧‧5th through hole

300‧‧‧First District

300A‧‧‧ Block

300B‧‧‧ Block

300Aa‧‧‧ sub-block

300Ab‧‧‧ sub-block

302‧‧‧Second District

302A‧‧‧ Block

302B‧‧‧ Block

304‧‧‧Main gap

306‧‧‧First gap

308‧‧‧Inter-block gap

310‧‧‧Internal gap

312‧‧‧Second gap

V1‧‧‧ Guide hole

V2‧‧‧ guide hole

V3‧‧‧ Guide hole

M‧‧‧ conductive layer

M1‧‧‧ first conductive layer

M2‧‧‧Second conductive layer

Da‧‧‧Distance

Dc‧‧‧ distance

D1‧‧‧ distance

D2‧‧‧ distance

D3‧‧‧ distance

D4‧‧‧ distance

D5‧‧‧ distance

D6‧‧‧Distance

D7‧‧‧ distance

D8‧‧‧ distance

W‧‧‧Width

W1‧‧‧Line width of the first wire

Line width of W2‧‧‧ second wire

W3‧‧‧The width of the overlap of the first and second conductors

W4‧‧‧Width

W5‧‧‧Width

W6‧‧‧Width

W7‧‧‧Width

W8‧‧‧Width

W9‧‧‧Width

X‧‧‧ first axis

Y‧‧‧Second axis

G1‧‧‧ first gap

G2‧‧‧Second gap

S1‧‧‧ first side

S2‧‧‧ second side

S3‧‧‧ junction

H1‧‧‧ Height

H2‧‧‧ Height

H3‧‧‧ Height

H4‧‧‧ Height

H5‧‧‧ height

H6‧‧‧ distance

H7‧‧‧ distance

H8‧‧‧ Height

H9‧‧‧ distance

H10‧‧‧ distance

T1‧‧‧ thickness

T2‧‧‧ thickness

T3‧‧‧ thickness

T4‧‧‧ thickness

L‧‧‧ length

L1‧‧‧The length of the first conductive block

L2‧‧‧ Length of the second conductive block

3-3‧‧‧ segments

A-A’‧‧‧ tangent

B-B’‧‧‧ tangent

C-C’‧‧‧ tangent

1B-1B‧‧‧ line segment

Fig. 1A is a top view of an embodiment of the present invention.

Fig. 1B is a cross-sectional view taken along line 1B-1B of Fig. 1A.

Figure 2 is a top view of another embodiment of the present invention.

Figure 3 is a cross-sectional view showing another embodiment of the present invention.

Figure 4 is a cross-sectional view showing another embodiment of the present invention.

Figure 5 is a cross-sectional view showing another embodiment of the present invention.

Fig. 6A is a top view of the display device of the embodiment of the present invention.

Fig. 6B is a partially enlarged view of the display device of Fig. 6A.

Figure 7 is a top view of the test pad of the embodiment of the present invention.

Figures 8A-8B are cross-sectional views of the test pad of Figure 7 taken along line 3-3.

Figure 9 is a top plan view of a test pad of another embodiment of the present invention.

Figure 10 is a top plan view of a test pad of another embodiment of the present invention.

Figure 11 is a top plan view of a test pad of another embodiment of the present invention.

Figure 12 is a top plan view of a test pad of another embodiment of the present invention.

Figure 13 is a top plan view of a display device according to an embodiment of the present invention.

Fig. 14A is a schematic view showing the cross-sectional structure of the display device shown in Fig. 13 along the tangential line A-A'.

14B and 14C are schematic cross-sectional views of a display device according to another embodiment of the present invention taken along a tangential line A-A'.

Figure 15 is a top plan view of a display device according to another embodiment of the present invention.

Fig. 16A is a view showing the cross-sectional structure of the display device shown in Fig. 15 along the tangential line B-B'.

16B and 16C are schematic cross-sectional views of the display device according to another embodiment of the present invention taken along a tangential line B-B'.

Figure 17 is a top plan view of a display device according to still another embodiment of the present invention.

Fig. 18 is a schematic cross-sectional view showing the display device shown in Fig. 17 along the tangential line C-C'.

19 and 20 are top views of a mother panel of a display device according to another embodiment of the present invention.

The display device of the present invention will be described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the invention. The specific elements and arrangements described below are intended to provide a brief description of the invention. Of course, these are by way of example only and not as a limitation of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not intended to represent any of the various embodiments and/or structures discussed. Relevance. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

It is important to understand that this feature can be used for components that are specifically described or illustrated. Various forms are known to the practitioner. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

In addition, relative terms may be used in the examples, such as "low" or "bottom" and "higher" or "top" to describe the relative relationship of one component to another. It will be understood that if the illustrated device is flipped upside down, the component described on the "lower" side will be the component on the "higher" side.

Here, the terms "about" and "about" usually mean a given value or Within 20% of the range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, meaning that the meaning of "about" or "about" may be implied without specific explanation.

The embodiment of the invention utilizes a layer between the display pixel area and the sealant. The photo spacer wall prevents the frame glue from contacting the liquid crystal material of the display pixel area, so that the distance between the sealant and the display pixel area can be further shortened to narrow the non-display area of the display device.

First, see Figures 1A and 1B. Figure 1A is an implementation of the present invention The upper view is taken as an example, and the 1B figure is a cross-sectional view taken along line 1B-1B of Fig. 1A. As shown in FIG. 1A, the display device 100 includes a first substrate 101 and is first The substrate 101 is oppositely disposed to the second substrate 103. Further, as shown in FIGS. 1A and 1B, the display device 100 includes a non-display area 105 that displays a pixel area 104 and an adjacent display pixel area. In other words, the first substrate 101 and the second substrate 103 can be divided into a non-display area 105 that displays a pixel area 104 and an adjacent display pixel area. In addition, the non-display area 105 includes an external lead leading area (OLB) 115, as shown in FIG. 1A.

The display device 100 may be a liquid crystal display, such as a thin film electro-crystal Body liquid crystal display. Alternatively, the liquid crystal display can be a Twisted Nematic (TN) type liquid crystal display, a Super Twisted Nematic (STN) type liquid crystal display, or a Double Layer Super Twisted Nematic (DSTN). Liquid crystal display, Vertical Alignment (VA) type liquid crystal display, In-Plane Switching (IPS) type liquid crystal display, Cholesteric type liquid crystal display, Blue Phase type liquid crystal display or the like Any suitable LCD monitor.

Referring to FIG. 1B, the first substrate 101 includes a first transparent substrate. 126. The light shielding layer 128 disposed on the first transparent substrate 126 and the color filter layer 130 disposed on the light shielding layer 128. In addition, the first substrate 101 may further include a flat layer 132 covering the color filter layer 130 and a portion of the light shielding layer 128.

The first transparent substrate 126 may be, for example, a glass substrate or a ceramic substrate. Board, plastic substrate or any other suitable transparent substrate. The light shielding layer 128 is used to shield the non-display area 105 and the elements other than the pixels in the pixel area 104. In addition, the material of the light shielding layer 128 may be black photoresist, black printing ink, black resin or any other suitable light shielding material and color. The color filter layer 130 may include The color filter layers 130A, 130B, and 130C of the pixel region 104 and the color filter layer 130D disposed in the non-display region 105 are displayed. The color filter layers 130A, 130B, and 130C can each independently be a red color filter layer, a green color filter layer, a blue color filter layer, or any other suitable color filter layer. In addition, the material of the flat layer 132 may be an organic germanium oxide compound, a photoresist, or an inorganic material such as tantalum nitride, hafnium oxide, tantalum oxynitride, tantalum carbide, aluminum oxide, tantalum oxide, or a multilayer structure of the above materials.

Continuing to refer to FIG. 1B, the second substrate 103 includes a second transparent The substrate 134 may be made of the same material as the first transparent substrate 126, and the materials of the first transparent substrate 126 and the second transparent substrate 134 may be the same or different. In addition, a transistor (not shown) for controlling pixels is provided in or on the second transparent substrate 134, for example, a thin film transistor is provided. The second substrate 103 may further include an insulating layer 136 covering the second transparent substrate 134 and the above transistor. The insulating layer 136 is used to electrically insulate the second substrate 103 from the elements disposed between the first substrate 101 and the second substrate 103. The material of the insulating layer 136 may be tantalum oxide, tantalum nitride, niobium oxynitride, a combination of the above, or any other suitable material.

Continuing to refer to FIGS. 1A and 1B, the display device 100 further includes A sealant 120 between the first substrate 101 and the second substrate 103 and a liquid crystal material 138. The sealant 120 is used to seal the liquid crystal material 138 between the first substrate 101 and the second substrate 103. The sealant 120 may be an insulating transparent resin or any other suitable sealant material, and the liquid crystal material 138 may be nematic, smectic, cholesteric, blue phase. Blue phase or any other suitable liquid crystal material.

As shown in Figures 1A and 1B, the sealant 120 is located on the display pixel. Outside of the area 104, it is easy to say that the sealant 120 is located in the non-display area 105. In some real In an embodiment, the sealant 120 can surround the display pixel region 104. Further, the sealant 120 has a width W4 of about 200 μm to 900 μm, for example, about 500 μm to 800 μm. It should be noted that if the width W4 of the sealant 120 is too large, for example, greater than about 900 μm, the non-display area 105 of the display device 100 may be too wide to make the display device 100 lighter, thinner, and shorter. However, if the width W4 of the sealant 120 is too small, for example, less than about 200 μm, the portion of the sealant 120 may be broken to effectively seal the liquid crystal material 138.

Continuing to refer to FIGS. 1A and 1B, the display device 100 further includes A spacer spacer 140 between the first substrate 101 and the second substrate 103, and the spacer 140 is located between the display pixel region 104 and the sealant 120 to further prevent the sealant 120 from contacting the display pixel. Liquid crystal material 138 of region 104. In addition, the partition wall 140 has a first side S1 adjacent to the display pixel area 104 and a second side S2 adjacent to the sealant 120, and the height H1 of the first side S1 is greater than the height H2 of the second side S2. For example, in the illustration, the height of the partition wall 140 is gradually lowered from the H1 on the S1 side (near the display area 104 side) to the S2 side (near the sealant 120 side) to H2. It should be noted that, in the embodiment shown in FIGS. 1A and 1B, the partition wall 140 is located on the flat layer 132 of the first substrate 101. However, in other embodiments, the partition wall 140 may also be located. On the second substrate 103, this portion will be described in detail later. Further, although in the embodiment shown in FIG. 1A, the partition wall 140 completely surrounds the display pixel area 104. However, the skilled person will appreciate that the partition wall 140 may be multi-turned or not only partially surrounded by the display pixel area 104. Therefore, the scope of protection of the present invention is not limited to the embodiment shown in FIG.

In addition, the material of the partition wall 140 may include a photoresist such as a positive photoresist or Negative photoresist. The spacer 140 can be formed by a lithography or lithography process. In one embodiment, the lithography process includes photoresist patterning, and the photoresist patterning further includes photoresist coating. Process steps such as cloth, soft bake, reticle alignment, exposure pattern, post-exposure baking, photoresist development, and hard bake. The etching step may include reactive ion etch (RIE), plasma etching, or other suitable etching step.

Continuing to refer to FIG. 1B, spacer wall 140 (or subsequent to spacer wall 140) The first alignment layer 148 on the top surface does not directly contact the second substrate 103, so the partition wall 140 (or the first alignment layer 148 disposed on the top surface of the partition wall 140) and the second substrate 103 have A first gap G1, and the height H5 of the first gap G1 may be about 0.1 μm to 1.5 μm, for example, about 0.3 μm to 0.8 μm. The height H5 of the first gap G1 is defined as the maximum distance H6 and the minimum distance H7 of the top surface of the second alignment layer 150 to the partition wall 140 (or the first alignment layer 148 disposed on the top surface of the partition wall 140). Average (ie H5=(H6+H7)/2). In addition, the sealant 120 can directly contact the partition wall 140, and a portion of the sealant 120 can extend from the second side S2 to the first side S1 by a distance D8, which can be about 20% of the width W5 of the partition wall 140. -90%, for example about 40% - 70%. It should be noted that if the distance D8 is too large, for example, greater than about 90% of the width W5 of the partition wall 140, the sealant 120 may be exposed to the liquid crystal material 138 contaminating the display pixel region 104, thereby increasing the probability of defects and making the process good. The rate drops. In addition, if the height H5 of the first gap G1 is too large, for example, greater than about 1.5 μm, the partition wall 140 cannot effectively prevent the sealant 120 from extending into the display pixel area 104 via the first gap G1, and the partition wall 140 is separated from the subsequent main space. If the height difference of the object 142 is too large or the sealant 120 is in contact to contaminate the liquid crystal material 138 in the display pixel region 104, the display device 100 may cause a problem of uneven display such as frame mura. However, if the height H5 of the first gap G1 is too small, for example, less than about 0.1 μm, the top surface of the partition wall 140 may be too close to the second substrate 103, so that the sealant 120 extending into the first gap G1 may be the second substrate. Pushing away from the first substrate 101 causes the display device 100 to produce gap imaging unevenness (gap) Mura) and other imaging problems, resulting in a decline in process yield.

Since the partition wall 140 prevents the sealant 120 from contacting the display pixel area The liquid crystal material 138 of 104, so that the distance between the sealant 120 and the display pixel area 104 can be further shortened to narrow the non-display area 105 of the display device 100, making the display device 100 lighter, thinner, and shorter. In addition, since the height H1 of the first side S1 of the sealant 120 is greater than the height H2 of the second side S2, even if the sealant 120 extends into the first gap G1 between the partition wall 140 and the second substrate 103 as described above, The height H2 of the second side S2 can also prevent the sealant 120 from extending into the display pixel region 104 via the first gap G1. Therefore, the sealant 120 can be further prevented from contacting the liquid crystal material 138 of the display pixel region 104 to cause the display device 100. Defects. As shown in FIG. 1B, in the case where the sealant 120 is not inserted into the first gap G1, the distance between the sealant 120 and the display pixel region 104 is the width W5 of the partition wall 140, and is subsequently located in the partition wall. The thickness T1 of the first alignment layer 148 on both sides S1 of S1 and the distance D7 from the first side S1 of the partition wall 140 to the display pixel area 104 add up the total distance (ie, W5+2xT1+D7).

The difference between the height H1 of the first side S1 of the partition wall 140 and the height H2 of the second side S2 may be about 0.01 μm to 0.3 μm, for example, about 0.05 μm to 0.1 μm. It should be noted that if the difference between the first side S1 and the second side S2 is too large, for example, greater than about 0.3 μm, it means that the height H2 of the second side S2 is too low, so that the partition wall 140 cannot effectively prevent the sealant. 120 contacts the liquid crystal material 138 of the pixel region 104. However, if the difference between the first side S1 and the second side S2 is too small, for example, less than about 0.01 μm, the partition wall 140 cannot effectively utilize the height difference between the first side S1 and the second side S2 to prevent the sealant 120 from passing through the first A gap G1 extends into the display pixel area 104.

Continuing to refer to FIG. 1B, the partition wall 140 has a width W5 of about 10 μm to 200 μm, for example, about 60 μm to 110 μm. It should be noted that if the partition wall 140 is wide If the degree W5 is too wide, for example, wider than about 200 μm, the non-display area 105 of the display device 100 may be too wide to make the display device 100 lighter, thinner, and shorter. However, if the width W5 of the partition wall 140 is too narrow, for example, narrower than about 10 μm, the partition wall 140 cannot effectively prevent the sealant 120 from contacting the liquid crystal material 138 of the display pixel region 104.

In addition, the distance from the first side S1 of the partition wall 140 to the display pixel area 104 From D7 is from 20 μm to 200 μm, for example from about 50 μm to 100 μm. It should be noted that if the distance D7 is too wide, for example, wider than about 200 μm, the non-display area 105 of the display device 100 may be too wide to make the display device 100 lighter, thinner, and shorter. However, if the distance D7 is too short, for example, less than about 20 μm, the sealant 120 is brought into contact with the liquid crystal material 138 of the pixel region 104 to cause an increase in the probability of defects, resulting in a decrease in process yield.

In addition, the height H3 of the partition wall 140 can be changed by changing the partition wall 140. The distance from the first side S1 to the display pixel area 104 is adjusted by D7. In detail, if the distance D7 is smaller, the smaller the reflow effect of the partition wall 140, the partition wall 140 can be allowed to have a higher height. Conversely, if the distance D7 is larger, the leveling effect of the partition wall 140 is larger, and the partition wall 140 can be allowed to have a lower height. Therefore, the height difference (i.e., H4-H3) between the main spacer 142 and the partition wall 140 can be made to be in a preferred range (i.e., about 0.1 μm to 1.5 μm) by adjusting the distance D7. .

Continuing to refer to FIG. 1B, the display device 100 further includes a first substrate. A main photo spacer 142 between the 101 and the second substrate 103, and the main spacer 142 is disposed in the display pixel area 104. The main spacers 142 may be defined in the same lithography or lithography process as the spacers 140. However, the main spacers 142 may also be formed by another lithography or lithography process.

Further, the height H4 of the main spacer 142 is higher than the height H3 of the partition wall 140. In the above, the height H3 of the partition wall 140 is defined as the first of the partition walls 140. The average of the height H1 of the side S1 and the height H2 of the second side S2 (i.e., H3 = (H1 + H2)/2). In some embodiments, the height H4 of the main spacer 142 is higher than the height H3 of the partition wall 140 by about 0.1 μm to 1.5 μm, for example, about 0.3 μm to 0.8 μm. It should be noted that if the height difference between the main spacer 142 and the partition wall 140 is too large, for example, greater than about 1.5 μm, the display device 100 may cause a problem of uneven imaging such as frame mura. However, if the height difference between the main spacer 142 and the partition wall 140 is too small, for example, less than about 0.1 μm, the top surface of the partition wall 140 may be too close to the second substrate 103, so that the sealant 120 extending into the first gap G1 may be Pushing the second substrate 103 away from the first substrate 101 causes the display device 100 to have a problem of development such as gap mura, resulting in a decrease in process yield.

Returning to FIG. 1A, the partition wall 140 includes a corner area 144 and a length. Strip 146, and width W6 of corner zone 144 is different from width W7 of strip zone 146. For example, in the embodiment illustrated in FIG. 1A, the width W6 of the corner region 144 is greater than the width W7 of the strip region 146.

However, the width of the corner zone may also be less than the width of the strip zone. E.g, FIG. 2 illustrates another embodiment of the present invention, which differs from the embodiment shown in the first aspect of FIG. 1A in that the width W6 of the corner region 144 is smaller than the width W7 of the elongated region 146. Moreover, those skilled in the art will recognize that the width of the corner zone may also be equal to the width of the strip zone, and the scope of protection of the present invention is not limited to the embodiments shown in Figures 1A, 1B and 2. It should be noted that elements or layers that are the same or similar to those in the foregoing will be denoted by the same or similar reference numerals, and the materials, manufacturing methods and functions thereof are the same or similar to those described above, and therefore will not be described later. Narration.

Next, returning to FIG. 1B , the display device 100 may further include a first alignment layer 148 disposed on the flat layer 132 and covering the partition wall 140 and the main spacer 142 , and A second alignment layer 150 on the insulating layer 136. The first alignment layer 148 and the second alignment layer 150 are thin layers for inducing alignment of liquid crystal molecules, and the material thereof may be polyimide or any other suitable alignment layer material. In addition, the first alignment layer 148 disposed on the top surface of the main spacer 142 may directly contact the second alignment layer 150. The first alignment layer 148 may have a thickness of about 300 angstroms to 1000 angstroms, for example, about 400 angstroms to 700 angstroms, and the first alignment layer 148 has a thickness T1 on the planar layer 132 that is greater than or equal to the first alignment layer 148. The thickness T2 on the partition wall 140.

Continuing to refer to FIG. 1B, as described above, the color of the first substrate 101 The filter layer 130 may include a first color filter layer 130D disposed in the non-display area 105, and the first color filter layer 130D is disposed below the partition wall 140. Further, as shown in FIG. 1B, the width W8 of the first color filter layer 130D is larger than the width W5 of the partition wall 140. However, it should be noted that the width of the first color filter layer may also be smaller than the width of the partition wall. For example, in another embodiment shown in FIG. 3, the width W8 of the first color filter layer 130D is smaller than the width W5 of the partition wall 140. In addition, it is known to those skilled in the art that the width of the first color filter layer can also be equal to the width of the partition wall. Therefore, the scope of protection of the present invention is not limited to the implementations shown in FIGS. 1A, 1B, 2, and 3. example.

The height H3 of the partition wall 140 can be changed by correspondingly changing the setting below The width W8 of the first color filter layer 130D is adjusted. In detail, if the width W8 of the first color filter layer 130D is smaller, the greater the reflow effect of the partition wall 140, the partition wall 140 can be allowed to have a lower height. On the contrary, if the width W8 of the first color filter layer 130D is larger, the leveling effect of the partition wall 140 is smaller, and the partition wall 140 can be allowed to have a higher height. Therefore, the height difference between the main spacer 142 and the partition wall 140 can be adjusted by adjusting the width W8 of the first color filter layer 130D (ie, H4-H3) is in the above preferred range (i.e., about 0.1 μm to 1.5 μm).

In addition, referring to FIG. 4, this figure is a cross section of another embodiment of the present invention. Figure. The difference from the embodiment shown in FIG. 1A-3 is that the color filter layer 130 of the first substrate 101 further includes a second color filter layer 130E corresponding to the lower portion of the partition wall 140, and the second color filter layer 130E and The first color filter layer 130D is different, and the boundary S3 of the first color filter layer 130D and the second color filter layer 130E corresponds to the lower portion of the partition wall 140. However, it should be noted that the boundary S3 between the first color filter layer 130D and the second color filter layer 130E may also correspond to the first side S1 of the partition wall 140 or the area other than the first side S1, and the present invention The scope of protection is not limited to the embodiment shown in FIG. Further, similar to the first color filter layer 130D, the height H3 of the partition wall 140 can be adjusted by changing the width W9 of the second color filter layer 130E disposed below it.

Figure 5 is a view showing another embodiment of the present invention, and the foregoing Figure 1A-4 The difference between the illustrated embodiments is mainly that the spacers 140 are located on the insulating layer 136 of the second substrate 103, rather than the flat layer 132 of the first substrate 101 as in the embodiment shown in the above 1A-4. In addition, as shown in FIG. 5, the display device 100 may further include a second alignment layer 150 disposed on the insulating layer 136 and covering the partition wall 140. The material of the second alignment layer 150 is the same as the material of the first alignment layer 148. The second alignment layer 150 disposed on the top surface of the main spacer 142 may directly contact the first alignment layer 148. In addition, the thickness T3 of the second alignment layer 150 on the insulating layer 136 is greater than or equal to the thickness T4 of the second alignment layer 150 on the partition wall 140.

In addition, the partition wall 140 (or the top surface of the partition wall 140) The second alignment layer 150) does not directly contact the first substrate 101, so the second gap G2 is formed between the partition wall 140 and the first substrate 101, and the height H8 of the second gap G2 is 0.1 μm to 1.5 μm, for example, about 0.3 μm to 0.8 μm. The height H8 of the second gap G2 is defined as the average distance H9 and the minimum distance H10 of the top surface of the first alignment layer 148 to the partition wall 140 (or the second alignment layer 150 disposed on the top surface of the partition wall 140). Value (ie H8=(H9+H10)/2). It should be noted that if the height H8 of the second gap G2 is too large, for example, greater than about 1.5 μm, the partition wall 140 cannot effectively prevent the sealant 120 from extending into the display pixel region 104 via the second gap G2, and the partition wall 140 and the main The height difference of the spacers 142 is too large, which causes the display device 100 to produce a problem of uneven imaging such as frame mura. However, if the height H8 of the second gap G2 is too small, for example, less than about 0.1 μm, the top surface of the partition wall 140 may be too close to the first substrate 101, so that the sealant 120 extending into the second gap G2 may be the first substrate. When the 101 is pushed away from the second substrate 103, the display device 100 causes a problem of development such as gap mura, resulting in a decrease in process yield.

In summary, the partition wall of the present invention can prevent the frame glue from contacting The liquid crystal material of the pixel region is displayed, so that the distance between the sealant and the display pixel region can be further shortened to narrow the non-display area of the display device, making the display device lighter, thinner and shorter. In addition, since the height of the partition wall adjacent to the display area is relatively high, even if the sealant extends into the partition wall, the display pixel area cannot be entered, so that the frame glue can be further prevented from contacting the liquid crystal material to cause defects of the display device.

In addition, the embodiment of the present invention utilizes changing the line in the display device. Configured to reduce the area occupied by this line in the integrated circuit. In addition, the embodiment of the present invention also uses a patterned test pad to improve the process reliability and process yield of the display device.

First, a display device known to the inventors includes a gate drive Roads, drive units, test pads and wiring. The drive unit includes a gate signal output connection Output Bump, and the gate signal output contact is electrically connected to the gate drive circuit by a line, and is electrically connected to the test pad by another line. It can be seen that the two lines occupy two areas in the driving unit (corresponding to the area 113A and the area 113B of FIG. 6B). When the resolution of the panel is increased, the signal output contact required for the chip (such as the driving unit) is increased, and the area originally formed on the panel to form the line is compressed, and when the line passes under the wafer, the line space can be accommodated under the wafer. Insufficient problems.

Therefore, in order to reduce the area occupied by the line, the present invention proposes another A way of configuring a line in a display device. Referring to Figure 6A, there is shown a top view of a display device in accordance with an embodiment of the present invention. As shown in FIG. 6A, the display device 100 includes a display area 104 and a non-display area 105 adjacent to the display area 104, wherein the display area 104 refers to an area in the display device 100 provided with a pixel display including a transistor, and This transistor can be, for example, a thin film transistor. Therefore, the display area 104 can also be referred to as a display pixel area 104. The non-display area 105 is the area other than the display area 104 in the display device. In this embodiment, the non-display area 105 surrounds the display area 104, and includes a Gate Driver on Panel (GOP) 107 on both sides of the display area 104, and an external pin connection area (Out Lead). The drive unit 106 and the test pad 109 in Bonding, OLB) 115. In addition, the non-display area 105 further includes a line 110, and a part of the line 110 is disposed in the external pin connection area 115. In other embodiments, the gate drive circuit 107 can be located on only one side of the display area 104.

The display device 100 can be a liquid crystal display, such as a thin film transistor. LCD Monitor. The driving unit 106 can be used to provide a source signal to the pixel of the display area 104 (not shown) or to provide a gate signal to the gate driving circuit 107. The gate driving circuit 107 is configured to provide a scan pulse signal to the pixel of the display area 104, and cooperate with The source signals together control respective pixels (not shown) provided in the display area 104 to cause the display device 100 to display a picture. The gate drive circuit 107 can be, for example, a Gate on Panel (GOP) or any other suitable gate drive circuit.

In addition, the driving unit 106 is electrically connected to the test pad 109 to Gate drive circuit 107. The test pad 109 can be electrically connected to the gate driving circuit 107 and the driving unit 106 by any suitable means. For example, in an embodiment, as shown in FIG. 6A, the test pad 109 can be electrically connected by the line 110. It is connected to the gate driving circuit 107 and the driving unit 106.

The present invention electrically connects the driving unit 106 via the test pad 109. To the gate drive circuit 107, the area occupied by the line 110 in the drive unit 106 can be reduced. In detail, referring to Fig. 6B, which is a partially enlarged view of the display device of Fig. 6A. As shown in the figure, the gate signal output terminal Output Bump 111 of the driving unit 106 is electrically connected to the test pad 109 through the line 110B. Then, the test pad 109 is electrically connected to the gate through another line 110A. The pole drive circuit 107. Compared with the display device known by the inventors mentioned above, in the known display device, the lines 110A and 110B are output from 113A and 113B, respectively. Therefore, under the driving unit 106, the areas of 113A and 113B must be provided simultaneously, but The line 110 of the present invention occupies only the area of the area 113B in the driving unit 106, but does not occupy the area 113A. As the panel resolution is higher and the number of output lines of the driving unit 106 is more and more, the area 113A can provide Other output lines are used, so the problem of insufficient line space in the chip (such as the drive unit) can be solved.

Furthermore, in order to improve the process of the display device 100 shown in FIG. 6A, The test pad 109 of the display device 100 of the present invention may be a pattern according to the degree of reliability and process yield. Test pad. In detail, in the test step of testing the performance of the display device 100, the probe must be contacted with the test pad 109, and the probe will leave a hole in the layer of the conductive layer of the test pad 109 when the test pad 109 is touched, and this conductive The holes in the layer are easily corroded by factors such as water and oxygen over time, causing abnormalities or disconnections between the driving unit 106 and the gate driving circuit 107, thereby reducing the reliability and process yield of the display device 100. In order to solve the above technical problem, the test pad of the embodiment of the present invention can be patterned into functional blocks in which a plurality of conductive layers are separated from each other, and the functional blocks are electrically connected by other connection layers.

See Figure 7 and Figure 8A, wherein Figure 7 is an embodiment of the present invention. Test pad 109 is viewed from above, while Figure 8A is a cross-sectional view of test pad 109 of Figure 7 along line 3-3. As shown in the above two figures, the test pad 109 includes a conductive layer M disposed on the substrate 102, and the conductive layer M includes a first region 300 and a second region 302. The conductive layer of the first region 300 is used to transmit signals between the two lines 110, and the conductive layer of the second region 302 is used to touch the probe during the testing step. The conductive layer of the first region 300 is in direct contact with the line 110, and the conductive layer of the second region 302 is separated from the conductive layer of the first region 300, that is, when only the conductive layer M is observed, the first region 300 and The second region 302 is not connected or contacted. For example, the conductive layer of the first region 300 and the conductive layer of the second region 302 may be separated by a main gap 304. In addition, the conductive layer of the second region 302 is also separated from the line 110. In other words, only the conductive layer M is observed. The conductive layer of the second region 302 does not directly contact the conductive layer of the first region 300 and the line 110. The first region 300 and the second region 302 are electrically connected by other connection layers via contact holes.

The present invention is guided by the second region 302 that will be touched with the probe The electrical layer is separated from the conductive layer and the line 110 of the first region 300 for transmitting signals, and the corrosion phenomenon after the test step can be limited to the conductive layer of the second region 302 without corroding. The conductive layer to the first region 300 and the line 110. Therefore, even if the etching phenomenon occurs after the test step, the patterned test pad 109 of the present invention can transmit the signal well through the conductive layer of the first region 300 and the line 110, so that the patterned test pad 109 can enhance the display. Reliability of the device 100 and process yield.

In addition, the ratio of the area of the first region 300 of the conductive layer M to the area of the second region 302 Values range from 2 to 1000, for example from 4 to 10. If the area ratio of the first region 300 to the second region 302 is too large, for example, greater than 1000, the area of the conductive layer of the second region 302 for contacting the probe is too small, which makes the test step difficult to perform. However, if the area ratio of the first region 300 to the second region 302 is too small, for example, less than 2, the area of the conductive layer of the first region 300 for transmitting the signal is too small, which causes the resistance to rise. Further, the test pad 109 has a size of 100 μm to 1000 μm, for example, 500 μm to 800 μm. The size of the test pad 109 can be the length L or the width W of the test pad 109.

Referring to FIG. 8A, the conductive layer M is disposed on the substrate 102. Conductive layer M may be a metal layer, and the material thereof may be single layer or multiple layers of copper, aluminum, tungsten, gold, chromium, nickel, platinum, titanium, tantalum, niobium, alloys of the above, combinations thereof or other conductive properties. metallic material. In other embodiments, the conductive layer M may be a non-metallic material as long as the material used is electrically conductive and subjected to corrosion and diffusion. For example, in the embodiment shown in FIG. 8A, the conductive layer M is a two-layer conductive layer including a first conductive layer M1 and a second conductive layer M2. In an embodiment, the first conductive layer M1 and the second conductive layer M2 are made of the same material. However, in other embodiments, the materials of the first conductive layer M1 and the second conductive layer M2 may be different. A dielectric layer (ILD) 206A is disposed between the two conductive layers M1 and M2. The first conductive layer M1 and the second conductive layer M2 have the same pattern, and the corresponding patterns are electrically connected by the via holes V1 provided in the dielectric layer 206A. The material of the above dielectric layer 206A can be It is yttria, tantalum nitride, yttrium oxynitride, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), spin on glass (SOG), any other suitable dielectric material, or a combination thereof. The material for electrically connecting the first conductive layer M1 and the second conductive layer M2 via the via hole V1 may be the first conductive layer M1 or the second conductive layer M2 itself or a combination thereof, or the material thereof may include copper, aluminum, tungsten. Doped polysilicon, any other suitable electrically conductive material, or a combination thereof.

In addition, in an embodiment, as shown in FIG. 8A, the first zone 300 The conductive layer and the conductive layer of the second region 302 can be electrically connected by the connection layer 211. Because the connection layer 211 has high corrosion resistance with respect to the conductive layer, the first region 300 and the second region 302 that are not in contact are connected by The layer 211 is electrically connected, and at the same time, the conductive layer is protected from corrosion by water and oxygen. The material of the connection layer 211 may be a transparent conductive material, such as indium tin oxide (ITO) tin oxide (TO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), Antimony tin oxide (ATO), antimony zinc oxide (AZO), combinations of the above or other suitable transparent conductive oxide materials having high corrosion resistance. The connection layer 211 can be electrically connected to the first conductive layer M1 or the second conductive layer M2 through the via hole V2 provided in the dielectric layer 206B, and thereby the conductive layer of the first region 300 and the second region 302 The conductive layer is electrically connected.

In addition, the conductive layer M may also be a single layer of conductive layer. For example, as in 8B As shown in the figure, only a single layer of conductive layer M is formed on the substrate 102, and the conductive layer of the first region 300 and the conductive layer of the second region 302 can also be electrically connected via the via hole through the connection layer 211. For example, the connection layer 211 can be electrically connected to the conductive layer M through the via hole V3 disposed in the dielectric layer 206 to electrically connect the conductive layer of the first region 300 and the conductive layer of the second region 302.

Referring again to FIG. 7, in the embodiment shown in FIG. 7, the main gap 304 The conductive layer of the second region 302 can be surrounded. The main gap 304 may have a width of 10 μm to 100 μm, for example, 20 μm to 40 μm. Further, the ratio of the width of the main gap 304 to the width W of the test pad 109 is 0.01 to 0.25, for example, 0.025 to 0.1. If the width of the main gap 304 is too wide, for example, it is wider than 100 μm, or its ratio W to the width W of the test pad 109 is greater than 0.25, the main gap 304 may occupy an area of the excess test pad 109, so that the area of the conductive layer M is reduced. Causes an increase in resistance. However, if the width of the main gap 304 is too narrow, for example, it is narrower than 10 μm, or its ratio W to the width W of the test pad 109 is less than 0.01, the main gap 304 cannot effectively prevent the conductive layer of the first region 300 from being corroded. For example, when the width of the main gap 304 is too narrow, if the probe touches the main gap 304 due to the offset, the conductive layer of the first region 300 may be exposed, causing the conductive layer of the first region 300 to be corroded.

In addition, the conductive layer of the first region 300 also surrounds the conductive region of the second region 302. a layer, and the conductive layer of the first region 300 may be separated into a plurality of blocks separated from each other by one or more first gaps 306, that is, the plurality of blocks are not in direct contact, for example, FIG. 7 Blocks 300A, 300B are shown. The plurality of blocks 300A, 300B separated from each other can further improve the process reliability and the process yield of the display device 100. In detail, in the test step, the probe may touch the conductive layer of the first region 300 due to the offset, so the conductive layer of the first region 300 may also cause corrosion after the test step. The blocks 300A, 300B separated from each other at this time can limit the corrosion phenomenon to the block touched by the probe, and the signal can still be transmitted by other blocks in the conductive layer of the first region 300 that are not corroded. . For example, if the probe touches the block 300A, since the blocks 300A, 300B are separated from each other, the corrosion phenomenon is confined to the block 300A, and the signal can still be transmitted by the block 300B which is not corroded. Therefore, the conductive layer of the first region 300 can be further divided by a plurality of blocks separated by one or more first gaps 306. The reliability and process yield of the display device 100 are improved in one step.

The width of the first gap 306 may be 3 μm to 50 μm, for example 10 μm to 20 μm. Alternatively, the ratio of the width of the first gap 306 to the width W of the test pad 109 is 0.0033 to 0.1, for example, 0.01 to 0.02. If the width of the first gap 306 is too wide, for example, it is wider than 50 μm, or its ratio W to the width W of the test pad 109 is greater than 0.1, the first gap 306 may occupy the area of the excess test pad 109, so that the area of the conductive layer M Reduced, causing an increase in resistance. However, if the width of the first gap 306 is too narrow, for example, it is narrower than 3 μm, or its ratio W to the width W of the test pad 109 is less than 0.0033, the first gap 306 cannot effectively separate the block 300A from the block 300B.

Furthermore, the plurality of blocks 300A, 300B of the first zone 300 separated from each other One or more intra-block gaps 308 may be included to divide the blocks 300A, 300B into a plurality of sub-blocks. The plurality of sub-blocks are largely separated from each other and are connected to each other only by a small portion. For example, the block 300A can be separated into a plurality of sub-blocks 300Aa, 300Ab by a plurality of intra-block gaps 308. The sub-blocks 300Aa, 300Ab are separated from each other by a small portion of the upper left and lower left in the drawing. Physically connected to each other. The plurality of sub-blocks 300Aa, 300Ab separated from each other can further improve the process reliability and the process yield of the display device 100. For example, when the probe touches the sub-block 300Ab due to the offset, since the sub-blocks 300Aa, 300Ab are connected by only a small portion, the corrosion phenomenon is easily confined to the sub-block 300Ab even if the sub-block The 300Ab is destroyed by corrosion and the signal can still be transmitted by the unetched block 300Aa. Therefore, dividing the plurality of blocks 300A, 300B into a plurality of sub-blocks (for example, sub-blocks 300Aa, 300Ab) by the intra-block gap 308 can further improve the reliability and process yield of the display device 100.

The width of the gap 308 in the above block may be 3 μm to 50 μm, for example 10 μm to 20 μm. Alternatively, the ratio of the width of the gap 308 in the block to the width W of the test pad 109 is 0.0033 to 0.1, for example, 0.01 to 0.02. If the width of the gap 308 in the block is too wide, for example, it is wider than 50 μm, or its ratio W to the width W of the test pad 109 is greater than 0.1, the gap 308 in the block may occupy the area of the excess test pad 109, so that the conductive layer M The area is reduced, resulting in an increase in resistance. However, if the width of the gap 308 in the block is too narrow, for example, it is narrower than 3 μm, or its ratio W to the width W of the test pad 109 is less than 0.0033, the sub-blocks 300Aa, 300Ab are too close, and the inner gap 308 cannot effectively separate the corrosion. influences.

Continuing to refer to Figure 7, the material of line 110 can be single or multiple layers. Copper, aluminum, tungsten, gold, chromium, nickel, platinum, titanium, niobium, tantalum, alloys of the above, combinations thereof, or other highly conductive metal materials, and the line 110 may also have one or more inter-line gaps 310. . In an embodiment, at least one in-line gap 310 is coupled to at least one first gap 306. The in-line gap 310 can further improve the process reliability and process yield of the display device 100. In detail, if the corrosion phenomenon extends from the block 300A of the first zone 300 to the first block line 110C, the in-line gap 310 can limit the corrosion phenomenon to the first block line 110C, so that the second block Line 110D will not be corroded. Therefore, since the line 110 is not completely corroded, the process reliability and the process yield of the display device 100 can be improved. In other embodiments, the connection layer 211 can also be overlaid on the line 110.

The width of the line gap 310 may be 3 μm to 50 μm, for example 10 μm to 20 μm. Alternatively, the ratio of the width of the in-line gap 310 to the width of the line 110 is 0.02 to 0.5, for example, 0.05 to 0.2. If the width of the gap 310 in the line is too wide, for example, it is wider than 50 μm, or its ratio to the width of the line 110 is greater than 0.5, it indicates that the inner gap 310 is excessively increased to increase the risk of disconnection of the line 110. However, if this line is inside If the width of the gap 310 is too narrow, for example, it is narrower than 3 μm, or the ratio of the width to the line 110 is less than 0.02, the line gap 310 cannot effectively separate the first block line 110C and the second area on both sides of the line inner gap 310. The block lines 110D are mutually affected by corrosion. Further, the ratio of the length of the in-line gap 310 to the length L of the test pad 109 is 0.03 to 3. The length of the line gap 310 may be as short as 3 μm, or the ratio of the length of the line gap 310 to the length L of the test pad 109 may be at least 0.03. The length of the line gap 310 may be the longest than the length of the line 110 in the external pin connection area 115. If the line gap 310 is too short, for example, its length is shorter than 3 μm, or the ratio of its length to the length L of the test pad 109 is less than 0.03, the line gap 310 cannot effectively separate the first block line 110C from the second block. Line 110D. However, the length of the in-line gap 310 may not be longer than the length of the line 110 in the external pin connection region 115.

It should be noted that, in addition to the embodiment shown in FIG. 7 above, the present invention The test pad of the Ming can also have other patterns, as shown in the embodiment of Figures 9-12. The scope of the invention is not limited to the embodiment shown in Fig. 7.

Referring to Figure 9, the figure is above the test pad of another embodiment of the present invention. view. The embodiment shown in FIG. 9 differs from the embodiment of FIG. 7 in that the conductive layer of the second region 302 is also separated into a plurality of blocks 302A, 302B separated from each other by one or more second gaps 312. In other words, there is no direct contact between the plurality of blocks 302A, 302B. Moreover, in this embodiment, the conductive layer of the first region 300 does not have an inter-block gap.

The plurality of blocks 302A, 302B separated from each other may further be mentioned The process reliability and process yield of the display device 100 are increased. For example, when the probe only touches the block 302A, the corrosion phenomenon is limited to the block 302A, and the unetched block 302B can also transmit the signal through the via hole through the via hole, thereby improving the display device 100. Reliability and process yield, and reduce resistance.

The width of the second gap 312 may be 10 μm to 100 μm, for example 30 μm to 50 μm. Alternatively, the ratio of the width of the second gap 312 to the width W of the test pad 109 is 0.01 to 0.25, for example, 0.05 to 0.1. If the width of the second gap 312 is too wide, for example, it is wider than 100 μm, or its ratio W to the width W of the test pad 109 is greater than 0.25, the second gap 312 may occupy the area of the excess test pad 109, so that the area of the conductive layer M Reduced, causing an increase in resistance. However, if the width of the second gap 312 is too narrow, for example, it is narrower than 10 μm, or its ratio W to the width W of the test pad 109 is less than 0.01, the second gap 312 cannot effectively separate the block 302A from the block 302B.

Referring to FIG. 10, the figure shows a test pad according to still another embodiment of the present invention. Top view. In the embodiment shown in FIG. 10, the conductive layer of the second region 302 is also separated into a plurality of blocks 302A, 302B separated from each other by the second gap 312. The difference between this embodiment and the foregoing embodiment of FIG. 9 is that the second gap 312 of this embodiment is aligned with the first gap 306 and the in-line gap 310.

Referring to FIG. 11 , the figure shows a test pad according to another embodiment of the present invention. Top view. The difference between the embodiment shown in FIG. 11 and the first embodiment of FIG. 10 is that the conductive layer of the second region 302 is divided into four blocks 302A, 302B, 302C and 302D separated from each other by three second gaps 312. In addition, line 110 has two in-line gaps 310, and the conductive layer of first region 300 does not have a first gap.

Referring to FIG. 12, the figure shows a test pad according to another embodiment of the present invention. Top view. The difference between the embodiment shown in FIG. 12 and the foregoing embodiment of FIG. 7 and FIG. 9-11 is that the conductive layer of the first region 300 does not surround the conductive layer of the second region 302, but is disposed in the second region 302. One side of the conductive layer. And the conductive layer of the second region 302 is divided into seven blocks 302A, 302B, 302C separated from each other by six second gaps 312. 302D, 302E, 302F and 302G. In other embodiments, the shape of the second gap 312 is not limited to a straight line, and is not limited to the division manner of the above embodiment, as long as the conductive layer of the second region 302 can be divided into a plurality of blocks separated from each other.

In summary, the drive unit is electrically connected to the test pad via the test pad. The gate driving circuit can reduce the area occupied by the circuit in the driving unit, and solve the problem that the line space in the driving unit is insufficient when the resolution of the panel is improved. In addition, by using the patterned test pad, the corrosion after the test step can be limited to only a part of the patterned test pad to improve the process reliability and process yield of the display device.

In addition, an embodiment of the present invention further provides a display device to improve walking. The accumulation degree of the wires in the line area is to reduce the area occupied by the line area in the display device, so that the resolution of the display device can be improved without increasing the size of the display device.

In addition, according to an embodiment of the present invention, the display device of the present invention may Further, the first conductive coil is disposed outside the display area, and is composed of a plurality of conductive blocks, so that the static electricity is accumulated during the manufacturing process of the display device to damage the display device.

Furthermore, according to an embodiment of the present invention, the display device of the present invention can be The second conductive coil is disposed on the outer side of the display area, and a sealant is disposed on the second conductive ring and located in a peripheral boundary of the display device to ensure the antistatic discharge capability of the second conductive ring.

First, please refer to FIG. 13 for an embodiment of the present invention. A top view of the display device 100. The display device 100 includes a display area 104 and a driving unit 106 disposed on a substrate 102. The display device 100 can be a liquid crystal display (for example, a thin film transistor liquid crystal display) or an organic electroluminescent device (for example, Active full color organic electroluminescent device). The display area 104 has a plurality of pixels (not shown), and the driving unit 106 is connected to the display area 104 by a plurality of signal line pairs 110 to provide a plurality of signals to the display area 110. A pixel to produce an image. The display area 104 and the driving unit 106 are separated by a fanout area 108, and the plurality of signal line groups 110 are disposed in the fanout area 108. The first wire 112 and the second wire 114 are electrically insulated from each other and used to transmit different signals. For example, each pixel located in the display area 104 may be composed of multiple sub-pixels (eg, red sub-pixels, blue sub-pixels, and green sub-pixels; or red sub-pixels, blue The sub-pixels, the green sub-pixels, and the white sub-pixels are formed, and the first wires 112 and the second wires 114 of the plurality of signal line groups 110 are used to transmit the signals generated by the driving unit 106 to Different sub-pixels. In addition, in the routing area 108, the first wire 112 of each signal line group 110 and the second wire 114 at least partially overlap.

Still referring to Figure 13, the fanout area 108 can further It is defined as being composed of a first line region 108a, a second line region 108b, and a third line region 108c, wherein the first line region 108a is adjacent to the display region 104, and the third line region 108c is The drive unit 106 is adjacent and the second line region 108b is located between the first line region 108a and the third line region 108c.

According to an embodiment of the invention, any two in the first line area 108a The adjacent first wire 112 and the second wire 114 are separated by a distance (ie, the shortest horizontal distance between the two) Da, and the first wire 112 adjacent to the two adjacent wires in the third line region 108c and The second wire 114 is separated by a distance (ie, the shortest horizontal distance between the two) Dc. Wherein, the distance Da may be between about 3 μm and 40 μm, the distance Dc may be between about 3 μm and 18 μm, and the distance Da is greater than the distance Dc.

Please refer to Figure 14A for the display device shown in Figure 13 A schematic cross-sectional view of line A-A'. It can be seen from FIG. 14A that in the second line region 108b, the first wire 112 of at least one of the signal line groups 110 can overlap with the second wire 114 to lower the first wire 112 and The area of the second wire 114 projected on a horizontal surface increases the accumulation of the trace area 108.

Still referring to FIG. 14A, the first wire 112 can be disposed on the substrate. Above 102. A dielectric layer 116 is disposed over the substrate 102 and covers the first wire 112. The second wire 114 is disposed on the dielectric layer 116 , and the first wire 112 of the signal line group 110 overlaps the second wire 114 . A passivation layer 118 is disposed over the dielectric layer 116 and covers the second wire 114. The substrate 102 may be a quartz, glass, germanium, metal, plastic, or ceramic material; the first conductive line 112 and the second conductive line 114 may be made of a single or multiple layers of a metal conductive material (for example, aluminum (Al). ), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W (or alloy thereof), a conductive compound of a metal compound (for example, comprising aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), Chromium (Cr), silver (Ag), gold (Au), tungsten (W), magnesium (Mg), or a combination thereof, or a combination thereof, and the material of the first wire 112 and the second wire 114 The material of the dielectric layer 116 may be tantalum nitride, hafnium oxide, tantalum oxynitride, tantalum carbide, aluminum oxide, or a combination thereof; and the material of the protective layer 118 may be organic. An insulating material (photosensitive resin) or an inorganic insulating material (tantalum nitride, hafnium oxide, tantalum oxynitride, tantalum carbide, aluminum oxide, or a combination thereof) may be used to isolate the first wire 112 and the second wire 114 Contact with air or moisture. In addition, according to an embodiment of the invention, the first wire 112 and the second guide The line 114 has a slanted side wall. Please refer to FIG. 14A, wherein the angle between the side wall and a horizontal plane is between about 15 degrees and 90 degrees, and the inclination of the side wall of the first wire and the side wall of the second wire The slopes are the same or different.

According to an embodiment of the invention, the line width W1 of the first wire 112 may be between Between about 2 μm and 10 μm, the line width W2 of the second wire 114 may be between about 2 μm and 10 μm, and the line width W1 of the first wire 112 and the line width W2 of the second wire 114 may be the same ( As shown in Figure 14A) or different (as shown in Figure 14B). In other words, the ratio of the line width W1 of the first wire 112 to the line width W2 of the second wire 114 may be between 1 and 5. For example, referring to FIG. 14B, the line width W1 of the first wire 112 may be greater than the line width W2 of the second wire 114. In addition, referring to FIGS. 2A-14B, the first wire 112 and the second wire 114 may completely overlap (ie, the projection of the first wire 112 to the horizontal plane and the projection of the second wire 112 to the horizontal plane completely overlap).

According to an embodiment of the invention, any two phases in the second line region 108b The adjacent first wires 112 are separated by a distance (ie, the shortest horizontal distance between two adjacent first wires in the second line region 108b) D1, and any two adjacent ones in the second line region 108b The two wires 114 are separated by a distance (ie, the shortest horizontal distance between two adjacent second wires in the second line region 108b) D2, wherein the distance D1 can be between about 2 μm and 30 μm, and the distance D2 can be It is between about 2 μm and 30 μm.

According to an embodiment of the present invention, in the second line region 108b, the first The sum of the line width W1 of one wire 112 and the distance D1 (W1+D1) is equal to the sum of the line width W2 and the distance D2 of the second wire 114 (W2+D2). Furthermore, the ratio (D1/(W1+D1)) of the distance D1 to the sum (W1+D1) of the distance D1 and the line width W1 of the first wire 112 may be between 0.1 and 0.66. When the ratio (D1/(W1+D1) is greater than Or equal to 0.1, which facilitates the subsequent formation of a sealant (not shown) formed on the second line region 108b in a consolidation process (energy applied by the substrate 102); and when the ratio ( When D1/(W1+D1) is less than or equal to 0.66, it is advantageous to improve the degree of accumulation of the wires in the second line region 108b.

On the other hand, the width W3 of the overlapping portion of the first wire 112 and the second wire 114 (the minimum overlap width of the projection of the first wire 112 with respect to the horizontal plane and the projection of the second wire 112 with respect to the horizontal plane) and the first The ratio of the line width W1 of the wire 112 may be between 0.3 and 1. In other words, in the second line region 108b, the first wire 112 of the signal line group 110 and the second wire 114 may partially overlap (ie, the projection of the first wire 112 to the horizontal plane and the second wire 112 to the horizontal plane) The projections are only partially overlapped. As shown in FIG. 14C, the line width W1 of the first wire 112, the line width W2 of the second wire 114, and the first wire 112 and the second wire 114 overlap. The width W3 of the part conforms to the following formula: (W1+W2-W3)/W1≧1

Referring to FIG. 15, a top view of a display device 100 according to another embodiment of the present invention is shown. The display device 100 further includes a first conductive loop 116 disposed on the substrate 102 and located in the display area 104, in addition to the display area 104, the driving unit 106, and the routing area 108. Outside. As shown in FIG. 15, the first conductive ring 116 can be disposed on the substrate 102 and surround the display area 104 and connected to the driving unit 106. The driving unit 106 can provide a voltage to the first conductive ring 116 such that the first conductive ring 116 has a reference potential. It should be noted that the first conductive ring 116 overlaps the signal line groups 110 in the routing area 108, and the overlapping portion may be layered by the first conductive ring 116 or the signal line groups 110 with other conductive layers. To avoid short circuits, there is no more detail here.

According to an embodiment of the invention, at least a portion of the first conductive ring 116 is A plurality of first conductive blocks 202 and a plurality of second conductive blocks 204 are formed, and the first conductive blocks 202 are electrically connected to the second conductive blocks 204. Please refer to FIG. 16A. A schematic cross-sectional view of the display device 100 of FIG. 15 along the tangent line BB' of the first conductive ring 116 is shown. According to an embodiment of the invention, the first conductive ring 116 formed by the plurality of first conductive blocks 202 and the plurality of second conductive blocks 204 is disposed on the display area 104 and perpendicular to a first axis X. The side (ie, the two sides parallel to a second axis Y), it is worth noting that, in this embodiment, a plurality of data lines (not shown) are disposed on both sides of the parallel first axis X, if the first conductive ring 116 is not easy to be formed by a plurality of first conductive blocks 202 and a plurality of second conductive blocks 204, but is not limited thereto.

It can be seen from FIG. 16A that the plurality of first conductive blocks 202 can be matched. Placed on the substrate 102. A dielectric layer 206 can be disposed on the substrate 102 and cover the first conductive blocks 202. The second conductive blocks 204 can be disposed on the dielectric layer 206. A passivation layer 208 can be disposed on the dielectric layer 206 and cover the second conductive blocks 204. In addition, a plurality of first vias 205 extend through the dielectric layer 206 and the protective layer 208 to expose the first conductive block 202. A plurality of second through holes 207 extend through the protective layer 208 to expose the second conductive block 204. A conductive layer 210 is disposed on the protective layer 208 and filled in the first through hole 205 and the second through hole 207 to make the first conductive block 202 and the second conductive portion The block 204 is electrically connected by the conductive layer 210.

According to an embodiment of the invention, the material of the first conductive block 202 and the second conductive block 204 may be a single layer or a plurality of layers of metal conductive materials (for example, aluminum (Al), copper (Cu), molybdenum (Mo), Titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), or alloys thereof, metal compound conductive materials ( For example: including aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold ( Au), tungsten (W), magnesium (Mg), or a combination thereof, or a combination thereof, and the materials of the first conductive block 202 and the second conductive block 204 may be the same or different. According to an embodiment of the invention, the first conductive block 202 and the first conductive line 112 may be formed of the same material in the same process step; and/or the second conductive block 204 and the second conductive line 114 may be the same The process is formed in the same material. The material of the dielectric layer 206 may be tantalum nitride, hafnium oxide, tantalum oxynitride, tantalum carbide, aluminum oxide, or a combination thereof, and the dielectric layer 206 and the dielectric layer 116 may be in the same process step. Formed from the same material. The material of the protective layer 208 may be an organic insulating material (photosensitive resin) or an inorganic insulating material (tantalum nitride, cerium oxide, cerium oxynitride, tantalum carbide, aluminum oxide, or a combination thereof), and the protection Layer 208 and the protective layer 118 can be formed of the same material in the same process step. In addition, the conductive layer 210 may be a single layer or a plurality of transparent conductive layers, and the material thereof may be, for example, indium tin oxide (ITO, indium tin oxide), indium zinc oxide (IZO, indium zinc oxide), or zirconium oxide (AZO). Aluminum zinc oxide, ZnO, zinc oxide, tin oxide (SnO ₂ ), indium trioxide (In ₂ O ₃ ), or a combination thereof.

Still refer to Figure 16A, in order to avoid the display device manufacturing process, The display device 100 is damaged due to static electricity accumulation. The length L1 of the first conductive block 202 may be between about 10 μm and 10000 μm, and the length L2 of the second conductive block 204 may be between about 10 μm and 10000 μm. between. In addition, any two adjacent first conductive blocks 202 are separated from each other by a distance D3, and any two adjacent second conductive blocks 204 are separated from each other by a distance D4, and any two adjacent first conductive blocks 202 are separated from each other. And the second conductive block 204 is separated by a distance D5. Wherein the distance D3 is between 16 μm and 100 μm Between the distances D4 is between 16 μm and 100 μm, and the distance D5 is between 3 μm and 40 μm.

According to another embodiment of the present invention, any two adjacent first conductive blocks 202 can be electrically connected directly by the second conductive block 204. Referring to FIG. 16B, the plurality of first conductive blocks 202 are disposed on the substrate 102. The dielectric layer 206 is disposed on the substrate 102 and covers the first conductive blocks 202. A plurality of third vias 209 extend through the dielectric layer 206 to expose the first conductive block 202. The second conductive block 204 is disposed on the dielectric layer 206 and filled in the third through hole 209 to make any two adjacent first conductive block 202 and second conductive block 204 The portions overlap, so that it is not necessary to additionally form the conductive layer 210.

According to other embodiments of the present invention, please refer to FIG. 16C, a flat layer 212 may be further formed over the protective layer 208. A plurality of fourth through holes 211 extend through the dielectric layer 206, the protective layer 208, and the flat layer 212 to expose the first conductive block 202. A plurality of fifth through holes 213 extend through the protective layer 208 and the flat layer 212 to expose the second conductive block 204. The conductive layer 210 is formed on the flat layer 212 and fills the fourth through hole 211 and the fifth through hole 213 to borrow the first conductive block 202 and the second conductive block 204. Electrical connection is achieved by the conductive layer 210. The flat layer 212 is a film layer having an insulating property, and may be, for example, a dielectric material or a photo-sensitive resin.

Please refer to FIG. 17, which is a display according to another embodiment of the present invention. View of device 100 above. The display device 100 further includes a second conductive loop 118 disposed on the substrate 102 in addition to the display area 104, the driving unit 106, the routing area 108, and the first conductive ring 116. The display area 104 and the first conductive ring 116 are located outside. As shown in FIG. 17, the first conductive ring 116 It can be disposed on the substrate 102, surrounds the display area 104, and is connected to the driving unit 106. The second conductive coil 118 can serve as an electrostatic discharge (ESD) protection unit, so that the electrostatic surge cannot directly damage the pixels located in the display area 104. In addition, a frame glue 120 is disposed on the substrate 102 and covers a portion of the second conductive ring 118. The area in which the sealant 120 is projected onto the substrate 102 is defined as a package area (not shown), and the second conductive ring 118 in the package area is covered by the sealant 120.

The material of the second conductive ring 118 can be a single layer or multiple layers of metal guides. Electrical materials (eg, aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), Gold (Au), tungsten (W), or alloys thereof, metal compound conductive materials (for example: containing aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), bismuth ( Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), magnesium (Mg), or a combination of the above), or a combination thereof. According to an embodiment of the invention, when the first conductive block 202 and the second conductive block 204 are formed, the second conductive ring 118 can be simultaneously formed. In addition, the sealant can be a resin.

Still referring to FIG. 17, the display device 100 has a peripheral boundary 122. In the package area, there is no distance between the sealant 120 and the peripheral boundary 122 (the distance is 0). Referring to Fig. 18, there is shown a cross-sectional structural view of the display device 100 shown in Fig. 17 along a tangential line C-C'. It can be seen from FIG. 18 that the second conductive ring 118 is separated from the peripheral boundary 122 by a distance D6, and the sealant 120 is disposed on the second conductive ring 118 and located in the peripheral boundary 122 (the second conductive ring 118 The space between the peripheral boundary 122 is filled with the sealant 12). It is worth noting that the distance D6 is between 50 and 300 μm to prevent corrosion of the second conductive coil 118 due to water or air, and to reduce its electrostatic discharge (ESD) protection capability.

In order to ensure that the second conductive ring 118 does not form in the formation of the sealant 120 The path error causes the second conductive coil 118 to be exposed outside the sealant 120. Fig. 19 is a schematic view showing a display device motherboard 201. The display device mother substrate 201 is formed into a display device shown in Fig. 17 after a cutting process. As shown in FIG. 19, when the sealant 120 is formed on the substrate 102, the sealant 120 needs to be covered on a predetermined dicing street 124. Therefore, when a cutting process is performed along the predetermined scribe line 124 (for example, a single or multiple blade cutting process or a laser cutting process), the peripheral boundary of the resulting display device 100 (as shown in FIG. 17) can be ensured. There is no distance between the sealants 120 (the distance is 0). In this way, the second conductive ring 118 is glued to the peripheral boundary 122 by the distance D6. As shown in FIG. 19, the sealant 120 can be applied to contact the peripheral boundary 122.

Further, according to an embodiment of the present invention, the sealant 120 is formed on the base On the board 102, even if the sealant 120 is not applied to the peripheral boundary 122, the formed sealant 120 covers the predetermined cut track 124 (refer to Fig. 20), along the predetermined cut line. When the cutting process is performed 124, the display device 100 shown in Fig. 17 can still be obtained.

In summary, the present invention reduces the concentration of wires in the routing area. The low wiring area occupies an area occupied by the display device, so that the resolution of the display device can be improved without increasing the size of the display device. In addition, the display device of the present invention may further include a first conductive ring located outside the display area, which is composed of a plurality of conductive blocks, which can prevent the static electricity from accumulating and damage the display device during the manufacturing process of the display device. Furthermore, the display device of the present invention may further include a second conductive ring located outside the display area, wherein a sealant is disposed on the second conductive ring and located in a peripheral boundary of the display device to ensure the second conductive ring Antistatic discharge capability.

Although embodiments of the invention and its advantages have been disclosed above, It is to be understood that any person skilled in the art can make modifications, substitutions and refinements without departing from the spirit and scope of the invention. In addition, the scope of the present invention is not limited to the processes, machines, manufacture, compositions, devices, methods, and steps in the specific embodiments described in the specification. Any one of ordinary skill in the art can. The processes, machines, fabrications, compositions, devices, methods, and procedures that are presently or in the future are understood to be used in accordance with the present invention as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of the invention includes the above-described processes, machines, manufactures, compositions, devices, methods, and steps. In addition, the scope of each of the claims constitutes an individual embodiment, and the scope of the invention also includes the combination of the scope of the application and the embodiments.

100‧‧‧ display device

101‧‧‧First substrate

103‧‧‧second substrate

104‧‧‧ Displaying the pixel area

105‧‧‧Non-display area

120‧‧‧Box glue

126‧‧‧First transparent substrate

128‧‧‧ shading layer

130‧‧‧Color filter layer

130A‧‧‧Color filter layer

130B‧‧‧Color filter layer

130C‧‧‧Color filter layer

130D‧‧‧First color filter layer

132‧‧‧flat layer

134‧‧‧Second transparent substrate

136‧‧‧Insulation

138‧‧‧Liquid crystal materials

140‧‧‧ partition wall

142‧‧‧Main spacer

148‧‧‧First alignment layer

150‧‧‧Second alignment layer

D7‧‧‧ distance

D8‧‧‧ distance

W4‧‧‧Width

W5‧‧‧Width

W8‧‧‧Width

G1‧‧‧ first gap

S1‧‧‧ first side

S2‧‧‧ second side

H1‧‧‧ Height

H2‧‧‧ Height

H3‧‧‧ Height

H4‧‧‧ Height

H5‧‧‧ height

H6‧‧‧ distance

H7‧‧‧ distance

T1‧‧‧ thickness

T2‧‧‧ thickness

Claims (20)

A display device includes: a first substrate comprising a display pixel region; a second substrate disposed opposite the first substrate; a sealant disposed on the first substrate and the second substrate And a photo spacer wall disposed between the first substrate and the second substrate and between the display pixel area and the sealant, wherein In the same partition wall, a first side of the partition wall is adjacent to the display pixel area, and a second side of the partition wall is adjacent to the sealant, and the height of the first side is greater than the second side height. The display device of claim 1, wherein a difference between a height of the first side and a height of the second side is 0.01 μm to 0.3 μm. The display device of claim 1, wherein the partition wall has a width of 10 μm to 200 μm. The display device of claim 1, wherein the distance from the first side to the display pixel area is from 20 μm to 200 μm. The display device of claim 1, wherein the sealant has a width of 200 μm to 900 μm. The display device of claim 1, further comprising a main photo spacer disposed between the first substrate and the second substrate and disposed in the display pixel region, wherein the main The height of the spacer is higher than the height of the partition wall. The display device of claim 1, wherein the partition wall On the first substrate, a gap is formed between the partition wall and the second substrate, and the height of the first gap is 0.1 μm to 1.5 μm. The display device of claim 1, wherein the partition wall is located on the second substrate, the partition wall and the first substrate have a second gap, and the height of the second gap is 0.1 μm to 1.5 Mm. The display device of claim 1, wherein the sealant extends from the second side to the first side at a distance of 20% to 90% of the width of the partition wall. The display device of claim 1, wherein the partition wall comprises a corner area and a strip area, wherein the width of the corner area is different from the width of the strip area. The display device of claim 10, wherein the width of the corner area is greater than the width of the strip area. The display device of claim 10, wherein the corner area has a width smaller than a width of the strip area. The display device of claim 1, wherein the first substrate further comprises a flat layer, and the partition wall is located on the flat layer. The display device of claim 13 further comprising a first alignment layer disposed on the planar layer and covering the spacer, wherein the first alignment layer is located on the planar layer and has a thickness greater than the first The thickness of the alignment layer on the partition wall. The display device of claim 1, wherein the second substrate further comprises an insulating layer, and the spacer is located on the insulating layer. The display device according to claim 15 of the patent application, further comprising a second An alignment layer is disposed on the insulating layer and covering the partition wall, wherein a thickness of the second alignment layer on the insulating layer is greater than a thickness of the second alignment layer on the partition wall. The display device of claim 1, wherein the first substrate further comprises a first color filter layer corresponding to the lower portion of the partition wall. The display device of claim 17, wherein the width of the first color filter layer is smaller than the width of the partition wall. The display device of claim 17, wherein the width of the first color filter layer is greater than the width of the partition wall. The display device of claim 17, wherein the first substrate further comprises a second color filter layer corresponding to the lower portion of the partition wall, wherein the first color filter layer and the second color filter layer are The junction corresponds to the underside of the partition wall.