CN109378309A - A kind of nano mattisolda low pressure sintering combined power modular approach - Google Patents
A kind of nano mattisolda low pressure sintering combined power modular approach Download PDFInfo
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- CN109378309A CN109378309A CN201811079143.0A CN201811079143A CN109378309A CN 109378309 A CN109378309 A CN 109378309A CN 201811079143 A CN201811079143 A CN 201811079143A CN 109378309 A CN109378309 A CN 109378309A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The present invention provides a kind of nano mattisolda low pressure sintering combined power modular approach, it can be achieved that when sintering area differs greatly simultaneously two kinds of chips, the layer of solder paste of acquisition intensity (>=30MPa) all with higher.The method includes predrying, pressurization, sintering and reduction Four processes.Pre-drying process is that soldering paste is allowed to obtain certain viscosity, prevents soldering paste in large-area chips pressure process from excessively overflowing.Pressure process is the acceleration of sintering that pressurizes to large area Si chip, and being not pressurized to small area SiC chip prevents from damaging.Sintering process carries out under+50% nitrogen atmosphere of 50% air, guarantees that soldering paste sintering has the restricting substrate oxide on surface generation simultaneously of enough oxygen.Reduction process restores substrate surface oxide using formic acid, removes the Cu oxide of Surface Creation.Integrated artistic process of the present invention is relatively simple, and the manufacturing of biggish combined power module is differed suitable for chip area.
Description
Technical field
The present invention relates to power electronic device encapsulation field more particularly to a kind of nano mattisolda low pressure sintering combined powers
Modular approach.
Background technique
Silicon carbide (SiC) material has many advantages, such as that thermal conductivity is high, breakdown field strength is high and forbidden bandwidth is big, this makes
SiC device shows better hot properties, lower power consumption and faster switching speed.In recent years, with SiC material
The further development of technology, the SiC high power module in power electronic devices field are increasingly becoming the hot spot of research and development.
Research shows that substituting traditional Si diode using SiC Schottky diode, the combined power module with Si base IGBT composition can
To reduce the on-state loss and switching loss of power module.
Traditional combined power module connects igbt chip and copper base using the solder alloy of low melting point, but with function
The fast development of rate building block technique, it is desirable that power module can bear bigger power density and better hot operation characteristic, pass
The solder of system can no longer meet these requirements.Emerging nano mattisolda can realize low-temperature sintering, high-temperature service
Function becomes a kind of power module connecting material of preferable alternative conventional alloys solder.So being burnt using nano mattisolda
Knot encapsulation IGBT combined power module, the high-temperature service that combined power module can be improved while reducing module switch and being lost are special
Property.
But when being sintered package hybrid power module using nano mattisolda, the SiIGBT core of combined power inside modules
Piece area is larger (>=100mm2), and SiC diode chip for backlight unit area is smaller (≤25mm2), and the two area difference is larger, and SiC bis-
Pole pipe chip is easy to damage to pressurize, and art methods can not achieve on naked copper substrate while when being sintered two kinds of chips, obtain
The layer of solder paste obtained all has higher-strength, this just needs a kind of method to solve the problems, such as this, realizes nano mattisolda package hybrid function
The function of rate module.
Summary of the invention
The present invention provides a kind of packaging method of nano mattisolda low pressure sintering combined power module, realizes in naked copper substrate
When two kinds of chips that sintering area differs greatly upper simultaneously, the layer of solder paste of acquisition all has the shear strength greater than 30MPa.
To achieve the above object, technical scheme is as follows:
A kind of packaging method of nano mattisolda low pressure sintering combined power module；Including predrying, pressurization, sintering and go back
Former Four processes；Wherein predrying and pressurization carried out in air environment, be sintered and restore in closed vacuum back-flow furnace into
Row.
The pre-drying process, first predrying prints nano mattisolda and posts the base of igbt chip in air atmosphere
Then plate republishes soldering paste and is placed with diode chip for backlight unit.
90-100 DEG C of the predrying temperature, pre-drying-time 10-12min.
The pressure process is greater than 100mm to area on predrying metacoxal plate under air environment2Silicon igbt chip apply
Plus-pressure；25mm is less than to area2SiC diode chip for backlight unit be not pressurized, the phenomenon that prevents SiC chip from pressurizeing easily damaged occurs.
The pressure process applies the pressure of the preferred 2MPa of pressure.
The sintering process is sintered the chip and substrate that exert pressure, nanometer silver soldering in controlled atmosphere sealed furnace
Cream sintering atmosphere is+50% nitrogen mixture atmosphere of 50% air, 270-290 DEG C of densification temperature of sintering heating, sintering densification
Time 20-40min.
5 DEG C/the min of heating rate.
The reduction process vacuumizes after sintering densification and is passed through nitrogen formic acid mixed gas, to substrate table
The oxide that face generates is restored, recovery time 10-15min；After the completion of reduction, cooled wafer and substrate.
5 DEG C/the min of cooling rate.
A kind of packaging method of nano mattisolda low pressure sintering combined power module of the present invention, may be implemented while sintered surface
Two kinds of chips that product differs greatly, and the nano mattisolda layer intensity for obtaining two kinds of chips is all higher.This method includes four mistakes
Journey: predrying, pressurization, sintering and reduction.Pre-drying process is to prevent large area core to allow soldering paste to obtain certain viscosity
The excessive spilling of soldering paste in piece pressure process, predrying temperature and time will strict control, temperature is excessively high or overlong time,
The organic matter in small chip layer of solder paste will be caused excessively to volatilize, nano-Ag particles are largely reunited.Pressure process is to large area
Si chip pressurization acceleration of sintering, being not pressurized to small area SiC chip prevents from damaging.Sintering process is in+50% nitrogen of 50% air
It is carried out under mixed atmosphere, guarantees that soldering paste sintering has the generation of enough oxygen while restricting substrate oxide on surface.Reduction process
Substrate surface oxide is restored using formic acid, prevents oxide from having an impact to module electrical property.Entirety work of the present invention
Skill process it is relatively simple, it can be achieved that on naked copper substrate simultaneously sintering area differ greatly two kinds of chips when, the soldering paste of acquisition
Layer all has the shear strength greater than 30MPa, and the manufacturing of biggish combined power module is differed suitable for chip area.
Detailed description of the invention
Fig. 1 is the schematic diagram that the present invention uses naked copper substrate；
Fig. 2 is the schematic diagram of bottom plate of the present invention；
Fig. 3 is the overlooking structure diagram for not installing shell；
Fig. 4 is the structural schematic diagram for installing shell；
In figure: 1- bottom plate, 2- substrate, 3-SiC diode chip for backlight unit, 4-Si base igbt chip, 5- crude aluminum line, 6- electrode, 7-
Shell.
Specific embodiment
The method of the present invention is described further presently in connection with attached drawing.
A kind of packaging method of nano mattisolda low pressure sintering combined power module；Including predrying, pressurization, sintering and go back
Former Four processes；Wherein predrying and pressurization carried out in air environment, be sintered and restore in closed vacuum back-flow furnace into
Row.
The pre-drying process, first predrying prints nano mattisolda and posts the base of igbt chip in air atmosphere
Then plate, 90-100 DEG C of predrying temperature, pre-drying-time 10-12min republish soldering paste and are placed with diode chip for backlight unit.
The pressure process is greater than 100mm to area on predrying metacoxal plate under air environment2Silicon igbt chip
Apply the pressure of 2MPa；25mm is less than to area2SiC diode chip for backlight unit be not pressurized, prevent SiC chip from pressurizeing easily damaged show
As occurring.
The sintering process is sintered the chip and substrate that exert pressure, nanometer silver soldering in controlled atmosphere sealed furnace
Cream sintering atmosphere is+50% nitrogen mixture atmosphere of 50% air, 5 DEG C/min of heating rate, sintering densification temperature 270-290
DEG C, sintering densification time 20-40min.
The reduction process vacuumizes after sintering densification and is passed through nitrogen formic acid mixed gas, to substrate table
The oxide that face generates is restored, recovery time 10-15min.After the completion of reduction, cooled wafer and substrate, cooling velocity 5
℃/min。
It is described with reference to the drawings as follows
Preparation: as shown in Figure 1, selecting to cover copper ceramic substrate (2) as lining material, as shown in Fig. 2, selection nickel plating
Copper sheet as copper soleplate (1)；Then according to 9% concentration dilute hydrochloric acid-deionization ethanol-water sequence cleaning base plate (2) and copper
Bottom plate (1).
Predrying: coating one layer of nano mattisolda using the method that steel mesh prints on substrate (2), and 60 μm of thickness；Later
Si base igbt chip (4) is attached to and is aligned above soldering paste and gently squeezes, makes chip and soldering paste good wet；Then by substrate
(2) it is placed on warm table and heats, at 90-100 DEG C, heating time controls in 10-12min heating and temperature control；It is removed after heating
Substrate (2) republishes soldering paste and is placed with SiC diode chip for backlight unit (3).
Pressurization: 100mm is greater than to area on predrying metacoxal plate2Silicon igbt chip apply 2MPa pressure；To area
Less than 25mm2SiC diode chip for backlight unit (3) be not pressurized, prevent SiC diode chip for backlight unit (3) pressurize easily damaged phenomenon from occurring.
Sintering: the chip and substrate (2) that exert pressure are sintered in controlled atmosphere vacuum back-flow furnace, nano mattisolda
Sintering atmosphere is+50% nitrogen mixture atmosphere of 50% air, and 5 DEG C/min of heating rate, the control of sintering densification temperature is in 270-
290 DEG C, the sintering densification time controls in 20-40min.
Reduction: after sintering densification, vacuumizing and be passed through nitrogen formic acid mixed gas, raw to substrate (2) surface
At oxide restored, recovery time 10-15min.After the completion of reduction, cooled wafer and substrate, 5 DEG C of cooling velocity/
min。
Subsequent operation: as shown in figure 3, realizing high-power IGBT chip, diode chip for backlight unit and liner plate electricity using crude aluminum silk (5)
The connection of pole (6) area, reuses SAC305 weld tabs and substrate (2) is welded on copper soleplate (1), then installs shell (7), gluing envelope
Dress, finally fills closed dose, the complete module being illustrated in figure 4 after completing all process steps.
Embodiment 1: ultrasonic cleaning copper-clad base plate (2) and copper soleplate (1) then print nano mattisolda on substrate (2)
And patch soaks；Predrying: first sample is placed on warm table and is heated to 90 DEG C and keeps the temperature 10min completion predrying；Pressurization: right
Large area Si base igbt chip (4) applies the pressure of 2MPa, and small area SiC diode chip for backlight unit (3) is not pressurized；Sintering: and then with 5
DEG C/heating rate of min is heated to 270 DEG C and keeps the temperature 20min in+50% nitrogen mixture atmosphere of 50% air；Reduction: then
Vacuumize logical nitrogen formic acid mixed gas reduction 10min.After sinter molding, two kinds of area chip shear strengths reach 30MPa
More than.It is sintered laggard line lead bonding, shell, gluing encapsulation, the subsequent handlings such as closed dose of filling are installed in secondary weldering.
Embodiment 2: ultrasonic cleaning copper-clad base plate (2) and copper soleplate (1) then print nano mattisolda on substrate (2)
And patch soaks.Predrying: first sample is placed on warm table and is heated to 100 DEG C and keeps the temperature 12min completion predrying；Pressurization:
Apply the pressure of 2MPa to large area Si base igbt chip (4), small area SiC diode chip for backlight unit (3) is not pressurized；Sintering: then
270 DEG C are heated to the heating rate of 5 DEG C/min and keep the temperature 20min in+50% nitrogen mixture atmosphere of 50% air；Reduction:
It is subsequently vacuumed out logical nitrogen formic acid mixed gas reduction 10min.After sinter molding, two kinds of area chip shear strengths reach
30MPa or more.It is sintered laggard line lead bonding, shell, gluing encapsulation, the subsequent handlings such as closed dose of filling are installed in secondary weldering.
Embodiment 3: ultrasonic cleaning copper-clad base plate (2) and copper soleplate (1) then print nano mattisolda on substrate (2)
And patch soaks.Predrying: first sample is placed on warm table and is heated to 90 DEG C and keeps the temperature 10min completion predrying；Pressurization: right
Large area Si base igbt chip (4) applies the pressure of 2MPa, and small area SiC diode chip for backlight unit (3) is not pressurized；Sintering: and then with 5
DEG C/heating rate of min is heated to 280 DEG C and keeps the temperature 30min in+50% nitrogen mixture atmosphere of 50% air；Reduction: then
Vacuumize logical nitrogen formic acid mixed gas reduction 12.5min.After sinter molding, two kinds of area chip shear strengths reach
30MPa or more.It is sintered laggard line lead bonding, shell, gluing encapsulation, the subsequent handlings such as closed dose of filling are installed in secondary weldering.
Embodiment 4: ultrasonic cleaning copper-clad base plate (2) and copper soleplate (1) then print nano mattisolda on substrate (2)
And patch soaks.Predrying: first sample is placed on warm table and is heated to 100 DEG C and keeps the temperature 12min completion predrying；Pressurization:
Apply the pressure of 2MPa to large area Si base igbt chip (4), small area SiC diode chip for backlight unit is not pressurized；Sintering: and then with 5
DEG C/heating rate of min is heated to 280 DEG C and keeps the temperature 30min in+50% nitrogen mixture atmosphere of 50% air；Reduction: then
Vacuumize logical nitrogen formic acid mixed gas reduction 12.5min.After sinter molding, two kinds of area chip shear strengths reach
30MPa or more.It is sintered laggard line lead bonding, shell, gluing encapsulation, the subsequent handlings such as closed dose of filling are installed in secondary weldering.
Embodiment 5: ultrasonic cleaning copper-clad base plate (2) and copper soleplate (1) then print nano mattisolda on substrate (2)
And patch soaks.Predrying: first sample is placed on warm table and is heated to 90 DEG C and keeps the temperature 10min completion predrying；Pressurization: right
Large area Si base igbt chip (4) applies the pressure of 2MPa, and small area SiC diode chip for backlight unit (3) is not pressurized；Sintering: and then with 5
DEG C/heating rate of min is heated to 290 DEG C and keeps the temperature 40min in+50% nitrogen mixture atmosphere of 50% air；Reduction: then
Vacuumize logical nitrogen formic acid mixed gas reduction 15min.After sinter molding, two kinds of area chip shear strengths reach 30MPa
More than.It is sintered laggard line lead bonding, shell, gluing encapsulation, the subsequent handlings such as closed dose of filling are installed in secondary weldering.
Embodiment 6: ultrasonic cleaning copper-clad base plate (2) and copper soleplate (1) then print nano mattisolda on substrate (2)
And patch soaks.Predrying: first sample is placed on warm table and is heated to 100 DEG C and keeps the temperature 12min completion predrying；Pressurization:
Apply the pressure of 2MPa to large area Si base igbt chip (4), small area SiC diode chip for backlight unit (3) is not pressurized；Sintering: then
290 DEG C are heated to the heating rate of 5 DEG C/min and keep the temperature 40min in+50% nitrogen mixture atmosphere of 50% air；Reduction:
It is subsequently vacuumed out logical nitrogen formic acid mixed gas reduction 15min.After sinter molding, two kinds of area chip shear strengths reach
30MPa or more.It is sintered laggard line lead bonding, shell, gluing encapsulation, the subsequent handlings such as closed dose of filling are installed in secondary weldering.
Packaging method of the present invention is easy to operate, relative to the chip and substrate of conventional alloys solder connection, shows more preferable
Resistance to thermal cycle and heat fatigue ability, have higher application value in high-power mixing module field.
Claims (9)
1. a kind of packaging method of nano mattisolda low pressure sintering combined power module；It is characterized in that including predrying, pressurization, burning
Knot and reduction Four processes；Wherein predrying and pressurization carry out in air environment, are sintered and restore in closed vacuum back-flow
It is carried out in furnace.
2. packaging method as described in claim 1；It is characterized in that the pre-drying process, first predrying prints in air atmosphere
It has brushed nano mattisolda and has posted the substrate of igbt chip, then republish soldering paste and be placed with diode chip for backlight unit.
3. packaging method as claimed in claim 2；It is characterized in that 90-100 DEG C of predrying temperature, pre-drying-time 10-
12min。
4. packaging method as described in claim 1；It is characterized in that the pressure process, under air environment to predrying after base
Area is greater than 100mm on plate2Silicon igbt chip apply pressure；25mm is less than to area2SiC diode chip for backlight unit be not pressurized, prevent
The phenomenon that only SiC chip pressurizes easily damaged occurs.
5. packaging method as claimed in claim 4；It is characterized in that described apply the pressure that pressure is 2MPa.
6. packaging method as described in claim 1；It is characterized in that the sintering process, to the chip and substrate for exerting pressure
It is burnt in controlled atmosphere sealed furnace, knot nano mattisolda sintering atmosphere is+50% nitrogen mixture atmosphere of 50% air, sintering heating
270-290 DEG C of densification temperature, sintering densification time 20-40min.
7. packaging method as claimed in claim 6；It is characterized in that 5 DEG C/min of heating rate.
8. packaging method as described in claim 1；It is characterized in that the reduction process is taken out true after sintering densification
Sky is simultaneously passed through nitrogen formic acid mixed gas, and the oxide generated to substrate surface restores, recovery time 10-15min；Reduction
After the completion, cooled wafer and substrate.
9. packaging method as claimed in claim 8；It is characterized in that 5 DEG C/min of cooling velocity.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111112787A (en) * | 2019-12-13 | 2020-05-08 | 深圳市振华微电子有限公司 | Method for removing oxide of nickel-plated layer of shell |
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| WO2014156025A1 (en) * | 2013-03-26 | 2014-10-02 | 田中貴金属工業株式会社 | Semiconductor device and heat-dissipating mechanism |
| US8815648B1 (en) * | 2013-04-01 | 2014-08-26 | Texas Instruments Incorporated | Multi-step sintering of metal paste for semiconductor device wire bonding |
| CN105479026A (en) * | 2015-12-09 | 2016-04-13 | 天津大学 | Method for improving connecting strength of nano sliver paste and chemical nickel-plated gold substrate |
| CN106653627A (en) * | 2016-10-11 | 2017-05-10 | 天津大学 | Sintering method for connecting bare copper substrate or copper-clad base plate with nano silver solder paste |
| CN107516639A (en) * | 2017-08-30 | 2017-12-26 | 刘向东 | Low-temperature oxidation reduction sintering method based on copper particle |
| CN107871675A (en) * | 2017-10-13 | 2018-04-03 | 天津大学 | A kind of nano mattisolda connection naked copper DBC power model preparation method |
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| CN111112787A (en) * | 2019-12-13 | 2020-05-08 | 深圳市振华微电子有限公司 | Method for removing oxide of nickel-plated layer of shell |
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