CN109378299B

CN109378299B - Wafer packaging structure

Info

Publication number: CN109378299B
Application number: CN201811015830.6A
Authority: CN
Inventors: 王汉清
Original assignee: Yueqing Fengjie Electronic Technology Co Ltd
Current assignee: Yueqing Fengjie Electronic Technology Co Ltd
Priority date: 2016-11-27
Filing date: 2016-11-27
Publication date: 2020-05-15
Anticipated expiration: 2036-11-27
Also published as: CN106548993B; CN109378299A; CN109378300B; CN106548993A; CN109378300A

Abstract

The invention provides a wafer packaging structure, which is characterized by comprising: a semiconductor substrate having opposing upper and lower surfaces; a plurality of pads on the upper surface; a plurality of solder balls on the plurality of pads; a solder resist layer surrounding the plurality of pads and solder balls; a metal heat conduction layer surrounding the solder resist layer, the metal heat conduction layer being located only at edges of the upper surface; a heat dissipation layer located on the lower surface; and a plurality of heat conducting through holes connecting the metal heat conducting layer and the heat dissipation layer.

Description

Wafer packaging structure

Technical Field

The present invention relates to a semiconductor package, and more particularly, to a wafer package with a heat dissipation structure.

Background

The trend of manufacturing electronic products is to minimize the volume of electronic components and to improve the Integration (Integration) of the products by using packaging technology. Meanwhile, based on the functional requirements of the electronic products nowadays, the limited space in the products must be provided with the most electronic components, so the size of the position for arranging the electronic components in the electronic products is equivalent to the size of the electronic components. Therefore, the tolerance of the electronic device becomes an item to be controlled.

Taking the current 35mm × 35mm semiconductor package as an example, the one-sided tolerance of the plane of the semiconductor package should not be greater than 0.2mm, i.e., the outer distance of the semiconductor package is between 37.98mm to 35.02 mm; and even about plus or minus 0.1mm in the case of a smaller semiconductor package. Therefore, it is difficult to manually inspect the edge position of the substrate of the semiconductor package, and therefore, it is common to introduce an automatic inspection machine for inspection.

However, when the semiconductor package is inspected by an automatic inspection machine, the tray is usually black or dark, and the solder mask layer on the surface of the semiconductor package is also dark, so that the image sensor cannot distinguish the edge of the substrate of the semiconductor package, thereby causing erroneous determination.

Meanwhile, Electrostatic Discharge (ESD) may burn out, degrade a semiconductor metal layer, or cause a potential failure, so that the Electrostatic protection function of the electronic device must be emphasized.

Finally, due to the increasing integration level, a large amount of heat is generated on the wafer substrate of the high-density device, and when the heat is too high, the temperature is too high, which may cause the device to fail, and therefore, the heat dissipation performance of the package must be considered.

Disclosure of Invention

Based on solving the above problems in the package, the present invention provides a wafer package structure, including:

a semiconductor substrate having opposing upper and lower surfaces;

a plurality of pads on the upper surface;

a plurality of solder balls on the plurality of pads;

a solder resist layer surrounding the plurality of pads and solder balls;

a metal heat conduction layer surrounding the solder resist layer, the metal heat conduction layer being located only at edges of the upper surface;

a heat dissipation layer located on the lower surface; and

and the plurality of heat conduction through holes are used for connecting the metal heat conduction layer and the heat dissipation layer.

According to an embodiment of the invention, the thickness of the metallic heat conducting layer is the same as the thickness of the solder resist layer.

According to an embodiment of the present invention, an edge of the solder resist layer has a stepped shape, and an inner side of the metal heat conduction layer matches the stepped shape.

According to the embodiment of the invention, the edge of the solder mask layer and the upper surface have an included angle which is an acute angle and faces the metal heat conduction layer.

According to the embodiment of the invention, the upper surface of the solder mask layer is provided with an annular groove, the depth of the groove is less than the thickness of the solder mask layer, and the groove is arranged between the outermost solder ball and the metal heat conduction layer.

According to an embodiment of the invention, the material of the metallic heat conducting layer is selected from at least one of Cu and Ni.

According to an embodiment of the present invention, the thermally conductive via may be filled with an electrically conductive material, preferably Cu or Au.

According to an embodiment of the present invention, the thermally conductive via may be filled with a non-conductive materialPreferably Al₂O₃。

According to the embodiment of the invention, the material of the heat dissipation layer is metal.

According to an embodiment of the present invention, the heat dissipation layer is a heat dissipation fin structure.

According to the technical scheme, the metal heat conduction layer on the periphery of the upper surface is utilized for carrying out first-step heat dissipation, and then a part of heat is conducted to the heat dissipation layer on the lower surface through the heat conduction through holes, so that the heat dissipation layer is large in area and high in heat dissipation efficiency, the device on the upper surface is not easily affected, the heat dissipation efficiency is greatly improved, and the packaging reliability is ensured; the peripheral metal heat conduction layer and the heat conduction through holes have an electromagnetic shielding effect, so that the interference of other electronic parts on the packaging piece is ensured; the metal heat conduction layer at the edge is different from the solder mask in color, so that the edge position can be easily distinguished.

Drawings

FIG. 1 is a cross-sectional view of a first wafer package structure;

FIG. 2 is a top view of a first wafer package structure;

FIG. 3 is a cross-sectional view of a second wafer package structure;

FIG. 4 is a cross-sectional view of a third wafer package structure;

FIG. 5 is a cross-sectional view of a fourth wafer package structure.

Detailed Description

Referring to fig. 1, the present invention provides a first wafer packaging structure, including:

a semiconductor substrate 10 having opposing upper and lower surfaces;

a plurality of pads 11 on the upper surface;

a plurality of solder balls 13 on the plurality of pads;

a solder resist layer 12 surrounding the plurality of pads 11 and solder balls 13;

a metallic thermally conductive layer 14 surrounding the solder resist layer 12, the metallic thermally conductive layer 14 being located only at the edges of the upper surface;

a heat dissipation layer 15 on the lower surface; and

a plurality of thermally conductive vias 16 connecting the metallic thermally conductive layer 14 and the heat dissipation layer 15.

Referring to fig. 2, the solder balls 13 are distributed in an array, the solder mask surrounds the solder balls 13, the metal heat conduction layer 14 is in a shape surrounding the solder mask 12, and the plurality of heat conduction through holes are located below the metal heat conduction layer 14 and also located at the edge of the substrate.

Wherein, the thickness of the metal heat conduction layer 14 is the same as the thickness of the solder mask layer 12, and the edge of the solder mask layer 12 is in close contact with the metal heat conduction layer 14, so as to completely cover the upper surface of the substrate.

Referring to fig. 3, the edge of the solder resist 12 may have a step shape, and the inner side of the metal heat conduction layer 14 matches (closely contacts) the step shape, and at this time, it is possible to prevent an excessive metal material from covering to the solder ball position when the metal heat conduction layer 14 is manufactured.

Referring to fig. 4, the edge of the solder mask 12 has an acute angle 18 with the upper surface, and the angle is towards the metal heat conducting layer.

Referring to fig. 5, the upper surface of the solder resist layer 12 has an annular groove 19, the depth of the groove 19 is smaller than the thickness of the solder resist layer 12, and the groove 19 is between the outermost solder ball 13 and the metal heat conduction layer 14. The annular groove 19 may be adapted to the embodiment shown in fig. 1, 3, and 4 to prevent excess metal material from covering the solder ball locations during fabrication of the metallic heat conductive layer 14.

Further, according to an embodiment of the present invention, the material of the metallic heat conduction layer 14 is selected from at least one of Cu and Ni. The thermal via 16 may be filled with an electrically conductive material, preferably Cu or Au; the thermally conductive vias 16 may also be filled with a non-conductive material, preferably Al₂O₃. The heat dissipation layer 15 is made of metal or a heat dissipation bonding sheet. The heat sink layer may also be a heat sink fin structure (not shown).

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims

1. A wafer package structure, comprising: a semiconductor substrate having opposing upper and lower surfaces; a plurality of pads on the upper surface; a plurality of solder balls on the plurality of pads; a solder resist layer surrounding the plurality of pads and solder balls; a metal heat conduction layer surrounding the solder resist layer, the metal heat conduction layer being located only at edges of the upper surface; a heat dissipation layer located on the lower surface; and a plurality of heat conducting through holes connecting the metal heat conducting layer and the heat dissipation layer; the thickness of the metal heat conduction layer is the same as that of the solder mask layer; the edge of the solder mask layer is in a step shape, and the inner side of the metal heat conduction layer is matched with the step shape; the edge of the solder mask layer and the upper surface form an included angle which is an acute angle and faces the metal heat conduction layer; the heat dissipation layer is of a heat dissipation fin structure.