CN106449562B - A kind of wafer packaging method with radiator structure - Google Patents
A kind of wafer packaging method with radiator structure Download PDFInfo
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- CN106449562B CN106449562B CN201611058191.2A CN201611058191A CN106449562B CN 106449562 B CN106449562 B CN 106449562B CN 201611058191 A CN201611058191 A CN 201611058191A CN 106449562 B CN106449562 B CN 106449562B
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- solder mask
- radiator structure
- packaging method
- wafer packaging
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Abstract
The present invention provides a kind of wafer packaging methods with radiator structure, comprising: (1) provides semiconductor substrate, have opposite upper and lower surfaces, the upper surface has multiple pads；(2) solder mask for covering the upper surface is formed, the solder mask leaks out the multiple pad, and leaks out the marginal position of upper surface；(3) multiple soldered balls are formed on the multiple pad；(4) the metal heat-conducting layer for surrounding the solder mask is formed on the marginal position of the upper surface not covered by solder mask；(5) the multiple thermally conductive through-holes for connecting the metal heat-conducting layer and penetrating through the upper and lower surfaces are formed；(6) heat dissipating layer for covering the lower surface is formed；The thickness of the metallic radiating layer is less than the thickness of the solder mask.
Description
Technical field
The present invention relates to a kind of semiconductor package part, espespecially a kind of wafer packaging method with radiator structure.
Background technique
The volume of electronic component is minimized to using encapsulation technology and is improved the integrated level (Integration) of product,
It is the trend for manufacturing electronic product.Meanwhile the functional requirement based on electronic product now, the confined space in product must be set
Most electronic components is set, therefore makes the interior sizableness for the position of electronic component is arranged of electronic product in the ruler of electronic component
It is very little.Therefore, the appearance tolerance values of electronic component also become the project for needing keyholed back plate.
By taking the semiconductor package part of current 35mm × 35mm size as an example, the unilateral tolerance of the plane of the semiconductor package part is not
Be greater than 0.2mm, also that is, the external distance of the semiconductor packages between 37.98mm between 35.02mm；And it is partly led if smaller
Body packaging part, or even positive and negative 0.1mm can be arrived or so.So if checking the edge of the substrate of semiconductor package part with manpower
Position is really difficult, is checked so generally importing now and automaticly inspecting machine.
However, when application automaticly inspects machine and carries out aforesaid semiconductor packaging part, it may occur that the case where erroneous judgement, and its reason
It is that general pallet is mostly black or dark color, and the layer of refusing on semiconductor package part surface is also dark color, so that image sensor
Chang Wufa tells the edge boundary of the substrate of semiconductor package part, therefore causes to judge by accident.
Simultaneously as static discharge (Electrostatic Discharge, ESD) can generate and burn, deteriorate semiconductor
Metal layer or generation latent failure etc., so, it must quite focus on antistatic protection function for electronic component.
Finally, due to the continuous promotion of integrated level, a large amount of heat will be generated in the wafer substrate of high-density device, works as heat
Excessive, temperature is excessively high, will lead to the failure of device, thus, the heat dissipation performance of encapsulation is also the problem of must be taken into consideration.
Summary of the invention
Based on solving the problems in above-mentioned encapsulation, the present invention provides a kind of wafer packaging method with radiator structure,
Include:
(1) semiconductor substrate is provided, there are opposite upper and lower surfaces, the upper surface has multiple pads；
(2) solder mask for covering the upper surface is formed, the solder mask leaks out the multiple pad, and leaks out upper table
The marginal position in face；
(3) multiple soldered balls are formed on the multiple pad；
(4) not led by formation on the marginal position of solder mask covering around the metal of the solder mask in the upper surface
Thermosphere；
(5) the multiple thermally conductive through-holes for connecting the metal heat-conducting layer and penetrating through the upper and lower surfaces are formed；
(6) heat dissipating layer for covering the lower surface is formed；
It is characterized in that, the thickness of the metallic radiating layer is less than the thickness of the solder mask.
It is specifically included according to an embodiment of the invention, forming the solder mask: first covering entire upper surface, then carry out
Photoetching, to leak out the multiple pad and the marginal position；Second of photoetching is carried out, forms one in the marginal position
Ladder.
Specifically included according to an embodiment of the invention, forming the multiple thermally conductive through-hole: first etch perforation upper surface and
The through-hole of lower surface, is then filled conduction material, forms thermally conductive through-hole；Grind the lower surface so that thermally conductive through-hole with
The lower surface flushes.
According to an embodiment of the invention, the half with a thickness of the solder mask thickness of the ladder.
According to an embodiment of the invention, the solder mask is with a thickness of 100-200 microns.
According to an embodiment of the invention, the thermally conductive through-hole can fill conductive material, preferably Cu or Au.
According to an embodiment of the invention, the thermally conductive through-hole can fill non-conducting material, preferably Al2O3.
According to an embodiment of the invention, the material of the heat dissipating layer is metal.
According to an embodiment of the invention, the heat dissipating layer is heat radiation fin structure.
Technical solution of the present invention carries out first step heat dissipation using the metal heat-conducting layer on upper surface periphery, then by leading
Heat through-hole conducts a part of heat to the heat dissipating layer of lower surface, and heat dissipating layer area is big, and radiating efficiency is high, and is not easy to upper table
The device in face impacts, and greatly improves radiating efficiency, ensure that the reliability of encapsulation；And the metal heat-conducting layer on periphery
There is electromagnetic shielding action with thermally conductive through-hole, guarantee interference of other electronic components to packaging part；The metal heat-conducting layer at edge with
Solder mask color is different, can easily tell marginal position；Finally, the solder mask is higher than the metal heat-conducting layer, it can
To prevent influence each other (short circuit etc.) between metal heat-conducting layer and soldered ball.
Detailed description of the invention
Fig. 1 is the sectional view of wafer packaging structure of the present invention；
Fig. 2 is the top view of wafer packaging structure of the present invention；
Fig. 3 is the manufacturing flow chart of wafer packaging structure of the present invention.
Specific embodiment
Referring to Fig. 1, the present invention provides a kind of wafer level packagings with radiator structure, comprising: semiconductor substrate 10 has
Opposite upper and lower surfaces；Multiple pads 11 positioned at the upper surface；Multiple soldered balls on the multiple pad
13；The solder mask 12 of the upper surface is covered, the solder mask 12 leaks out the multiple soldered ball 13 and to cover the upper table
The marginal position in face；Around the metal heat-conducting layer 14 of the solder mask 12, the metal heat-conducting layer 14 is only located at the upper surface
Marginal position；Heat dissipating layer 15 positioned at the lower surface；And the connection metal heat-conducting layer 14 and the heat dissipating layer 15
Multiple thermally conductive through-holes 16；In the present embodiment, the thickness of the metal heat-conducting layer 14 is less than the thickness of the solder mask 12, in this way
The height that soldered ball can more be protruded can be to avoid metal heat-conducting layer 14 and weldering when connecting other electronic components or substrate outside
The short circuit of ball or short circuit with other electronic components or substrate.
Preferably, referring to Fig. 1 and Fig. 2, the edge of the solder mask 12 has a ladder 17, and the metal heat-conducting layer 14 is tight
It is affixed on the edge of the ladder 17, the ladder 17 is not more than around the welded ball array, the thickness of the metal heat-conducting layer 14
The thickness of the ladder 17, more preferably, the thickness of metal heat-conducting layer 14 are equal to the thickness of the ladder 17.The thickness of the ladder
For the half of the solder mask thickness, for example, the solder mask is with a thickness of 100-200 microns, the step-thickness is 50-100
Micron, the thickness of the metal heat-conducting layer 14 is also 50-100 microns.The setting of the ladder can be prevented in deposition or electroplating gold
When belonging to heat-conducting layer 14, the upper surface that excessive metal material spills into solder mask leads to the short circuit of soldered ball.
In addition, according to an embodiment of the invention, the material of the metal heat-conducting layer 14 is selected from least one of Cu and Ni.
The thermally conductive through-hole 16 can fill conductive material, preferably Cu or Au；The thermally conductive through-hole 16 can also fill non-conductive material
Material, preferably Al2O3.The material of the heat dissipating layer 15 is metal or heat dissipation bonding pad etc..The heat dissipating layer may be heat dissipation
Fin structure (not shown).
Its specific manufacturing method referring to Fig. 3 flow diagram, comprising:
(1) semiconductor substrate 10 is provided, there are opposite upper and lower surfaces, the upper surface has multiple pads
11；
(2) solder mask 12 for covering the upper surface is formed, the solder mask leaks out the multiple pad 11, and leaks out
The marginal position of upper surface；It forms the solder mask 12 to specifically include: first depositing welding resistance agent material and cover entire upper surface, then
Photoetching is carried out, to leak out the multiple pad 11 and the marginal position, and second of photoetching is carried out, in the solder mask 12
Marginal position forms a ladder 17, and the thickness of the ladder 17 is greater than or equal to the thickness of the metal heat-conducting layer.
(3) multiple soldered balls 13 are formed on the multiple pad 11；
(4) gold for surrounding the solder mask 12 is formed on the marginal position of the upper surface not covered by solder mask 12
Belong to heat-conducting layer 14；
(5) the multiple thermally conductive through-holes 16 for connecting the metal heat-conducting layer 14 and penetrating through the upper and lower surfaces are formed；
It forms the multiple thermally conductive through-hole 16 to specifically include: first etching the through-hole of perforation upper and lower surfaces, be then filled
Conduction material forms thermally conductive through-hole 16, grinds the lower surface, so that thermally conductive through-hole 16 is flushed with the lower surface.
(6) heat dissipating layer 15 for covering the lower surface is formed.
Finally, it should be noted that obviously, the above embodiment is merely an example for clearly illustrating the present invention, and simultaneously
The non-restriction to embodiment.For those of ordinary skill in the art, it can also do on the basis of the above description
Other various forms of variations or variation out.There is no necessity and possibility to exhaust all the enbodiments.And thus drawn
The obvious changes or variations that Shen goes out are still in the protection scope of this invention.
Claims (10)
1. a kind of wafer packaging method with radiator structure, comprising:
(1) semiconductor substrate is provided, there are opposite upper and lower surfaces, the upper surface has multiple pads；
(2) solder mask for covering the upper surface is formed, the solder mask exposes the multiple pad, and exposes upper surface
Marginal position；
(3) multiple soldered balls are formed on the multiple pad；
(4) metal heat-conducting for surrounding the solder mask is formed on the marginal position of the upper surface not covered by solder mask
Layer；
(5) the multiple thermally conductive through-holes for connecting the metal heat-conducting layer and penetrating through the upper and lower surfaces are formed；
(6) heat dissipating layer for covering the lower surface is formed；
It is characterized in that, the thickness of the metal heat-conducting layer is less than the thickness of the solder mask.
2. the wafer packaging method according to claim 1 with radiator structure, which is characterized in that form the solder mask
It specifically includes: first covering entire upper surface, carry out first time photoetching, then to expose the multiple pad and the margin location
It sets；Second of photoetching is carried out, forms a ladder in the marginal position.
3. it is specific to form the multiple thermally conductive through-hole for the wafer packaging method according to claim 1 with radiator structure
Include: the through-hole for first etching perforation upper and lower surfaces, is then filled conduction material, forms thermally conductive through-hole；Grinding
The lower surface, so that thermally conductive through-hole is flushed with the lower surface.
4. the wafer packaging method according to claim 2 with radiator structure, which is characterized in that the thickness of the ladder
For the half of the solder mask thickness.
5. the wafer packaging method according to claim 2 with radiator structure, which is characterized in that the solder mask thickness
It is 100-200 microns.
6. the wafer packaging method according to claim 1 with radiator structure, which is characterized in that the metal heat-conducting layer
Material be selected from least one of Cu and Ni.
7. the wafer packaging method according to claim 1 with radiator structure, which is characterized in that the thermally conductive through-hole is filled out
Conductive material is filled, the conductive material is Cu or Au.
8. the wafer packaging method according to claim 1 with radiator structure, which is characterized in that the thermally conductive through-hole is filled out
Non-conducting material is filled, the non-conducting material is Al2O3。
9. the wafer packaging method according to claim 1 with radiator structure, which is characterized in that the material of the heat dissipating layer
Material is metal.
10. the wafer packaging method according to claim 1 with radiator structure, which is characterized in that the heat dissipating layer is
Heat radiation fin structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201611058191.2A CN106449562B (en) | 2016-11-27 | 2016-11-27 | A kind of wafer packaging method with radiator structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611058191.2A CN106449562B (en) | 2016-11-27 | 2016-11-27 | A kind of wafer packaging method with radiator structure |
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| CN106449562A CN106449562A (en) | 2017-02-22 |
| CN106449562B true CN106449562B (en) | 2019-01-04 |
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| CN114121839A (en) * | 2020-08-28 | 2022-03-01 | 长鑫存储技术有限公司 | Semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040092092A1 (en) * | 2002-11-12 | 2004-05-13 | Siliconware Precision Industries, Ltd. | Semiconductor device with under bump metallurgy and method for fabricating the same |
| US20080237310A1 (en) * | 2007-03-26 | 2008-10-02 | Shanggar Periaman | Die backside wire bond technology for single or stacked die package |
| CN103824852A (en) * | 2014-03-10 | 2014-05-28 | 沈阳利昂电子科技有限公司 | Bare chip embedded back-light structure |
| CN104485289A (en) * | 2014-12-16 | 2015-04-01 | 南通富士通微电子股份有限公司 | Wafer packaging method |
-
2016
- 2016-11-27 CN CN201611058191.2A patent/CN106449562B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040092092A1 (en) * | 2002-11-12 | 2004-05-13 | Siliconware Precision Industries, Ltd. | Semiconductor device with under bump metallurgy and method for fabricating the same |
| US20080237310A1 (en) * | 2007-03-26 | 2008-10-02 | Shanggar Periaman | Die backside wire bond technology for single or stacked die package |
| CN103824852A (en) * | 2014-03-10 | 2014-05-28 | 沈阳利昂电子科技有限公司 | Bare chip embedded back-light structure |
| CN104485289A (en) * | 2014-12-16 | 2015-04-01 | 南通富士通微电子股份有限公司 | Wafer packaging method |
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