CN109376098A - Forward direction bypasses buffer circuit - Google Patents
Forward direction bypasses buffer circuit Download PDFInfo
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- CN109376098A CN109376098A CN201811187561.1A CN201811187561A CN109376098A CN 109376098 A CN109376098 A CN 109376098A CN 201811187561 A CN201811187561 A CN 201811187561A CN 109376098 A CN109376098 A CN 109376098A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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Abstract
The invention discloses before one kind to bypass buffer circuit, it include: Bypass control unit, cache unit and data selector, there are three input terminal and three output ends for Bypass control unit setting, there are three input terminal and three output ends for cache unit setting, there are three input terminal and an output ends for data selector setting, Bypass control unit is connect with cache unit, cache unit is connect with data selector, Bypass control unit is used to that data and reading data whether to be written according to from the signal of higher level and junior control cache unit, cache unit is used to that data to be written according to signal and reads data, data selector is for selecting data of the source of output data in outer input data or cache unit, method by changing timing with area, increase bypass caching, due to increasing this additional buffer list entry, can will after The handshake timing path of item is broken apart by chopping, to reach effective solution back-pressure sequence problem, and purpose impregnable for forward path.
Description
Technical field
The present invention relates to digital circuit the pipeline design technical fields, and in particular to bypass buffer circuit before a kind of.
Background technique
Pipelining is a basic fundamental of modern processors, and assembly line is deeper, since each level production line needs
It shakes hands, the back-pressure signal of assembly line afterbody may be crosstalked into always most previous stage and cause serious back-pressure (Back-
Pressure) sequence problem needs to solve these sequence problems using some advanced methods.It is set in modern processors
In meter, usually there are following 2 kinds of methods:
Cancellation is shaken hands: the method can prevent the generation of back-pressure, and timing performance is very good.But cancel and shaking hands, that is, it means
Every level-one in assembly line will not shake hands with its next stage, be likely to result in mistake or instruction lost.Therefore this
Method is more radical, is aided with a series of other configuration mechanisms, recommends overall complexity bigger, only it is some very
It can just be used in advanced processor design.
Ping-pong buffer is added: it is a kind of method with area also timing that ping-pong buffer (Ping-pong Buffer), which is added,
It is also in the most straightforward procedure for solving back-pressure.A common level production line is replaced by using ping-pong buffer (there are two list item)
(only one list item) can make this assembly line receive signal to shaking hands for upper level and be concerned only in ping-pong buffer whether have one
A above free list item, without shaking hands for next stage is received signal cross-talk to upper level, but forward path can be by
It influences.
Summary of the invention
In order to solve the above technical problems, the invention proposes before one kind to bypass buffer circuit, to reach effective solution
Back-pressure sequence problem, and purpose impregnable for forward path.
In order to achieve the above objectives, technical scheme is as follows: to bypass buffer circuit, the circuit packet before a kind of
Include: Bypass control unit, cache unit and data selector, there are three input terminal and three are defeated for the Bypass control unit setting
Outlet, there are three input terminal and three output ends for the cache unit setting, and there are three input terminals for the data selector setting
With an output end, the Bypass control unit is connect with cache unit, and the cache unit is connect with data selector, described
Bypass control unit is used to that data and reading data, institute whether to be written according to from the signal of higher level and junior control cache unit
Cache unit is stated for data to be written according to signal and reads data, the data selector is used to select the source of output data
Data in outer input data or cache unit.
Further, three input terminals of the Bypass control unit are respectively that higher level's signal input part, junior's signal are defeated
Enter end and bypass feedback signal input terminal, three output ends of the Bypass control unit are respectively that higher level controls signal output
End, junior's control signal output and Bypass control unit state output end；
Three input terminals of the cache unit be respectively higher level's control signal input, junior's control signal input and
Three output ends of buffering external data input pin, the cache unit are respectively cache unit state output end, feedback signal
Output end and data cached output end；
Three input terminals of the data selector be respectively selector external data input terminal, data cached input terminal and
Selector feedback signal input terminal, an output end of the data selector are data output end；
Higher level's control signal output of the Bypass control unit and higher level's control signal input of cache unit connect
It connects, junior's control signal output of Bypass control unit and junior's control signal input of cache unit connect；It is described slow
The choosing with the bypass feedback signal input terminal and data selector of Bypass control unit respectively of the feedback signal output of memory cell
Select the connection of device feedback signal input terminal；The data cached input of the data cached output end and data selector of the cache unit
End connection.
Further, higher level's signal input part of the Bypass control unit comes from supervisory signal for receiving, described
Junior's signal input part of Bypass control unit is for receiving the signal from junior, the Bypass control unit state output end
For showing whether data enter circuit；The buffering external data input pin of the cache unit is for receiving external data, institute
The cache unit state output end of cache unit is stated for indicating whether cache unit is non-full；The selection of the data selector
Device external data input terminal is for receiving external data, and the data output end of the data selector is for exporting data to electricity
Outside road；The buffering external data input pin of the cache unit and the selector external data input terminal of data selector receive
External data come from the same data-in port.
Further, the Bypass control unit includes: three inputs and door, the first NOT gate, two inputs and door, the second NOT gate
With two inputs or door, three input and three input terminals of door respectively with higher level's signal input part, junior's signal input part and
The input terminal of second NOT gate connects, and three input is connect with the output end of door with the input terminal of the first NOT gate, and described first is non-
The output end of door is connect with two inputs with an input terminal of door, another input terminal and higher level's signal of two inputs and door
Input terminal connection, two input are connect with higher level's control signal input of the output end of door and cache unit, and described second
The feedback signal output of the input terminal of NOT gate and cache unit connects, two input terminals of two input or door respectively with it is upper
Grade signal input part is connected with the feedback signal output of cache unit.
Further, when the cache unit is empty, higher level's signal input part sets 0, then enters without data preceding to bypass
Buffer circuit；1, junior's signal input part is set when higher level's signal input part and sets 0, and data are written into cache unit；When higher level's signal
Input terminal sets 1, junior's signal input part and sets 1, then cache unit is bypassed, and data selector directly receives external data and defeated
Out.
Further, when the cache unit non-empty, 0, junior's signal input part is set when higher level's signal input part and sets 0, then
There is no data to enter preceding to bypass buffer circuit；It sets 0, junior's signal input part when higher level's signal input part and sets 1, then deposit receipt of postponing
Member reads data, and cache unit is sky when its depth is not more than 1；1, junior's signal input part is set when higher level's signal input part to set
0, then cache unit receives external data, cache unit non-empty；1, junior's signal input part, which is set, when higher level's signal input part sets 1,
Then cache unit is read while write, cache unit non-empty.
Further, when the cache unit is full, data do not enter cache unit, and data selector selection caching is single
The data output of member.
The present invention has the advantage that
(1) method of the present invention by changing timing with area increases bypass caching, additional due to increasing this
Buffer list entry can break apart by chopping consequent handshake timing path, and, effective solution unaffected for forward path
Back-pressure sequence problem.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described.
Fig. 1 is that forward direction disclosed by the embodiments of the present invention bypasses buffer circuit functional unit connection schematic diagram；
Fig. 2 is that forward direction disclosed by the embodiments of the present invention bypasses buffer circuit structural schematic diagram；
Fig. 3 is Bypass control unit structural schematic diagram disclosed by the embodiments of the present invention；
Fig. 4 is cache unit structural schematic diagram disclosed by the embodiments of the present invention；
Fig. 5 is data selector structural schematic diagram disclosed by the embodiments of the present invention；
Fig. 6 is that forward direction disclosed by the embodiments of the present invention bypasses buffer circuit work flow diagram；
Number and corresponding component title represented by letter in figure:
1, Bypass control unit；2, cache unit；3, data selector；101, higher level's signal input part；102, junior believes
Number input terminal；103, Bypass control unit state output end；104, three inputs and door；105, the first NOT gate；106, two input with
Door；107, the second NOT gate；108, two inputs or door；201, higher level's control signal input；202, junior's control signal input；
203, external data input terminal；204, buffering external data input pin；205, cache unit state output end；206, feedback signal
Output end；207, data cached output end；301, selector external data input terminal；302, data cached input terminal；303, number
According to output end.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description.
The present invention provides before one kind to bypass buffer circuit, its working principle is that the method by changing timing with area,
Increase bypass caching, due to increasing this additional buffer list entry, consequent handshake timing path can be broken apart by chopping,
To reach effective solution back-pressure sequence problem, and purpose impregnable for forward path.
Below with reference to embodiment and specific embodiment, the present invention is described in further detail.
As shown in figs 1 to 6, a kind of preceding to bypass buffer circuit, the circuit includes: Bypass control unit 1, caching list
Member (FIFO) 2 and data selector (MUX) 3, there are three input terminal and three output ends, institutes for the setting of Bypass control unit 1
Stating the setting of cache unit 2, there are three input terminal and three output ends, and there are three input terminal and one for the setting of data selector 3
Output end, the Bypass control unit 1 are connect with cache unit 2, and the cache unit 2 is connect with data selector 3, the side
Road control unit 1 is used to that data and reading data, institute whether to be written according to from the signal of higher level and junior control cache unit 2
It states Bypass control unit 1 and is also used to inform next stage circuit, whether forward direction bypass buffer circuit has data that can export (o_vld
=1, then there is data output；O_vld=0 is then exported without data), the cache unit 2 is used for buffering external data, described
Data selector 3 is used to select the source of output data (o_dat) in outer input data (i_dat) or cache unit 2
Data (fifo_o_dat).
Wherein, three input terminals of the Bypass control unit 1 are respectively higher level's signal input part 101 (i_vld), junior
Signal input part (o_rdy) 102 and bypass feedback signal input terminal, three output ends of the Bypass control unit 1 are respectively
Higher level's control signal output, junior's control signal output and Bypass control unit state (o_vld) output end 103；
Three input terminals of the cache unit 2 are respectively higher level's control signal input (fifo_i_vld) 201, junior
Control signal input (fifo_o_rdy) 202 and caching external data input terminal 204, three outputs of the cache unit 2
End is respectively cache unit state (fifo_i_rdy) output end 205, feedback signal (fifo_o_vld) output end 206 and caching
Data (fifo_o_dat) output end 207；
Three input terminals of the data selector 3 are respectively selector external data input terminal 301, data cached input
End 302 and selector feedback signal input terminal, an output end of the data selector 3 are data output end 303；
Higher level's control signal output of the Bypass control unit 1 and higher level's control signal input of cache unit 2
201 connections, junior's control signal output of Bypass control unit 1 and junior's control signal input 202 of cache unit 2 connect
It connects；The feedback signal output 206 of the cache unit 2 respectively with the bypass feedback signal input terminal of Bypass control unit 1 and
The selector feedback signal input terminal of data selector 3 connects；The data cached output end 207 and data of the cache unit 2
The data cached input terminal 302 of selector 3 connects.
Wherein, higher level's signal input part 101 of the Bypass control unit 1 comes from supervisory signal for receiving, described
Junior's signal input part 102 of Bypass control unit 1 is for receiving the signal from junior, 1 state of Bypass control unit
Output end is for showing whether data enter circuit；The buffering external data input pin 204 of the cache unit 2 is outer for receiving
Portion's data, 2 state output end of cache unit of the cache unit 2 is for indicating whether cache unit 2 is non-full；The data
The selector external data input terminal 301 of selector 3 is for receiving external data, the data output end of the data selector 3
303 for exporting data to circuit external；The buffering external data input pin 204 and data selector 3 of the cache unit 2
The received external data of selector external data input terminal 301 come from the same data-in port.
Wherein, external data input terminal 203 is connect by a circuit with cache unit 2, passes through bypass path and data
Selector 3 connect, after data enter circuit, data selector 3 according to the state of cache unit 2 select output data source come
Data from outer input data or cache unit 2, when FIFO is empty, output data i_dat, otherwise output data be
fifo_o_dat。
Wherein, Bypass control unit 1 is provided with a by-passing signal (byp), when FIFO is sky, and i_vld and o_rdy
When being simultaneously 1, by-passing signal sets 1.
Wherein, the circuit FIFO, for storing data, only when FIFO is not bypassed, i.e. when by-passing signal byp=0,
FIFO (fifo_i_vld=1) could be written in data, at this point, if FIFO non-full (fifo_i_rdy=1), data are written into
FIFO.When FIFO is not empty (fifo_o_vld=1), and forward direction bypass buffer output end receives handshake (o_rdy=1)
When, data are read from FIFO.
Wherein, the Bypass control unit 1 includes: three inputs and door 104, the input of the first NOT gate 105, two and door 106, the
Two NOT gates 107 and two inputs or door 108, three input terminals of three input and door 104 respectively with higher level's signal input part
101, junior's signal input part 102 is connected with the input terminal of the second NOT gate 107, three input and the output end of door 104 and the
The input terminal of one NOT gate 105 connects, and the output end of first NOT gate 105 is connect with two inputs with an input terminal of door 106,
Two input is connect with another input terminal of door 106 with higher level's signal input part 101, and two input is defeated with door 106
Outlet is connect with higher level's control signal input 201 of cache unit 2, the input terminal and cache unit 2 of second NOT gate 107
Feedback signal output 206 connect, it is described two input or door 108 two input terminals respectively with higher level's signal input part 101
It is connected with the feedback signal output 206 of cache unit 2.
Wherein, when the cache unit 2 is empty, higher level's signal input part 101 sets 0, then enters without data preceding to bypass
Buffer circuit；1, junior's signal input part 102 is set when higher level's signal input part 101 and sets 0, then cache unit 2 is written in data；When upper
Grade signal input part 101 sets 1, junior's signal input part 102 and sets 1, then cache unit 2 is bypassed, and data selector 3 directly receives
External data simultaneously exports.
Wherein, when 2 non-empty of cache unit, 0, junior's signal input part 102 is set when higher level's signal input part 101 and sets 0,
Then enter without data preceding to bypass buffer circuit；0, junior's signal input part 102 is set when higher level's signal input part 101 and sets 1, then
Data are read from cache unit 2, and (when the depth of FIFO is greater than 1, and data are not when its depth is not more than 1 to be empty for cache unit 2
It all reads, cache unit is not empty at this time)；1, junior's signal input part 102 is set when higher level's signal input part 101 and sets 0, then is delayed
Memory cell 2 receives external data, 2 non-empty of cache unit；1, junior's signal input part 1102 is set when higher level's signal input part 101 to set
1, then cache unit 2 is read while write, 2 non-empty of cache unit.
Wherein, when the cache unit 2 is full, data do not enter cache unit 2, and the selection caching of data selector 3 is single
The data output of member.
Wherein, when 1 state of Bypass control unit (o_vld) output end sets 0, indicate that cache unit 2 is sky, and there is no data
Into circuit, other 1 state of situation Bypass control unit (o_vld) output ends set 1,2 state of cache unit (fifo_i_rdy)
Expression cache unit 2 is full when output end sets 0, when cache unit 2 is non-full, 2 state of cache unit (fifo_i_rdy) output end
Set 1
Above-described is only a kind of preceding preferred embodiment to bypass buffer circuit disclosed in this invention, should be referred to
Out, for those of ordinary skill in the art, without departing from the concept of the premise of the invention, can also make several
Modification and improvement, these are all within the scope of protection of the present invention.
Claims (7)
1. to bypass buffer circuit before a kind of, which is characterized in that the circuit includes: Bypass control unit, cache unit sum number
According to selector, there are three input terminal and three output ends for the Bypass control unit setting, and there are three the cache unit settings
Input terminal and three output ends, there are three input terminal and an output end, the Bypass Control lists for the data selector setting
Member is connect with cache unit, and the cache unit is connect with data selector, and the Bypass control unit is used for basis and comes from
Whether the signal of grade and junior control cache unit is written data and reads data, and the cache unit according to signal for being written
Data and reading data, the data selector are used to select the source of output data from outer input data or cache unit
Interior data.
2. forward direction according to claim 1 bypasses buffer circuit, which is characterized in that three of the Bypass control unit are defeated
Entering end is respectively higher level's signal input part, junior's signal input part and bypass feedback signal input terminal, the Bypass control unit
Three output ends be respectively higher level's control signal output, junior's control signal output and Bypass control unit state output
End；
Three input terminals of the cache unit are respectively higher level's control signal input, junior's control signal input and caching
External data input terminal, three output ends of the cache unit are respectively cache unit state output end, feedback signal output
End and data cached output end；
Three input terminals of the data selector are respectively selector external data input terminal, data cached input terminal and selection
Device feedback signal input terminal, an output end of the data selector are data output end；
Higher level's control signal output of the Bypass control unit and higher level's control signal input of cache unit connect, other
Junior's control signal output of road control unit and junior's control signal input of cache unit connect；The cache unit
Feedback signal output respectively with Bypass control unit bypass feedback signal input terminal and data selector selector it is anti-
The connection of feedback signal input terminal；The data cached output end of the cache unit and the data cached input terminal of data selector connect
It connects.
3. forward direction according to claim 2 bypasses buffer circuit, which is characterized in that the higher level of the Bypass control unit believes
Number input terminal comes from supervisory signal for receiving, and junior's signal input part of the Bypass control unit comes from down for receiving
The signal of grade, the Bypass control unit state output end is for showing whether data enter circuit；The cache unit delays
External data input terminal is deposited for receiving external data, the cache unit state output end of the cache unit is for indicating caching
Whether unit is non-full；The selector external data input terminal of the data selector is for receiving external data, the data
The data output end of selector is for exporting data to circuit external；The buffering external data input pin of the cache unit with
The received external data of selector external data input terminal of data selector comes from the same data-in port.
4. forward direction according to claim 3 bypasses buffer circuit, which is characterized in that the Bypass control unit includes: three
Input and door, the first NOT gate, two inputs and door, the second NOT gate and two inputs or door, three input terminals of three input and door
It is connect respectively with the input terminal of higher level's signal input part, junior's signal input part and the second NOT gate, three input is defeated with door
Outlet is connect with the input terminal of the first NOT gate, and the output end of first NOT gate is connect with two inputs with an input terminal of door,
Two input is connect with another input terminal of door with higher level's signal input part, the output end and caching of two input and door
Higher level's control signal input of unit connects, and the input terminal of second NOT gate and the feedback signal output of cache unit connect
It connects, two input terminals of two input or door connect with the feedback signal output of higher level's signal input part and cache unit respectively
It connects.
5. forward direction according to claim 4 bypasses buffer circuit, which is characterized in that when the cache unit is empty, higher level
Signal input part sets 0, then enters without data preceding to bypass buffer circuit；When higher level's signal input part sets the input of 1, junior's signal
End sets 0, and data are written into cache unit；1, junior's signal input part is set when higher level's signal input part and sets 1, then cache unit is other
Road, data selector directly receive external data and export.
6. forward direction according to claim 4 bypasses buffer circuit, which is characterized in that when the cache unit non-empty, when upper
Grade signal input part sets 0, junior's signal input part and sets 0, then enters without data preceding to bypass buffer circuit；When higher level's signal is defeated
Enter end and set 0, junior's signal input part to set 1, then read data from cache unit, cache unit is sky when its depth is not more than 1；
1, junior's signal input part is set when higher level's signal input part and sets 0, then cache unit receives external data, cache unit non-empty；When
Higher level's signal input part sets 1, junior's signal input part and sets 1, then cache unit is read while write, cache unit non-empty.
7. forward direction according to claim 4 bypasses buffer circuit, which is characterized in that when the cache unit is full, data
Do not enter cache unit, data selector selects the data output of cache unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811187561.1A CN109376098B (en) | 2018-10-12 | 2018-10-12 | Forward bypass buffer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811187561.1A CN109376098B (en) | 2018-10-12 | 2018-10-12 | Forward bypass buffer circuit |
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| CN109376098A true CN109376098A (en) | 2019-02-22 |
| CN109376098B CN109376098B (en) | 2022-12-27 |
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