CN109360826A - Three-dimensional storage - Google Patents
Three-dimensional storage Download PDFInfo
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- CN109360826A CN109360826A CN201811202855.7A CN201811202855A CN109360826A CN 109360826 A CN109360826 A CN 109360826A CN 201811202855 A CN201811202855 A CN 201811202855A CN 109360826 A CN109360826 A CN 109360826A
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- connecting line
- dimensional storage
- array common
- common source
- pseudo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The present invention provides a kind of three-dimensional storages, comprising: the one or more array common sources extended in a first direction on substrate；And the first conductive pattern on one or more of array common sources, comprising: the one or more connecting lines extended in a second direction are electrically connected at least one described array common source；Extend and be located at the pseudo- connecting line of one or more of connecting line two sides along the second direction；And extend and be located at multiple bit lines of the pseudo- connecting line two sides along the second direction.The two sides of connecting line in three-dimensional storage of the invention are arranged with pseudo- connecting line, reduce the short-circuit risks of connecting line and bit line.In addition, when using techniques such as self-alignment duplex patterns to form the first conductive pattern, providing process window protection since the two sides of connecting line are arranged with pseudo- connecting line.In addition, connecting line can have biggish width, its resistance is reduced.
Description
Technical field
The invention mainly relates to semiconductor field more particularly to a kind of three-dimensional storages.
Background technique
With the continuous improvement that market requires storage density, two dimensional memory critical dimension reduction has arrived scale amount
The technical limit is produced, in order to further increase memory capacity, reduce cost, proposes the memory of three-dimensional structure.
In three-dimensional storage include the bit line being electrically connected with the channel layer in channel structure and with array common source electricity
The connecting line of connection.Connecting line is for electric current to be introduced into array common source.In general, bit line and connecting line are positioned at same
Layer, and at the same time being formed.Further to promote storage density, can be arranged on the unit area of three-dimensional storage core space more
A channel structure.Correspondingly, the density of the bit line in core space and connecting line can further increase, and the interval between line and line becomes
It is small.This adds increased the short-circuit risks between bit line and connecting line.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of three-dimensional storages, and which reduce between bit line and connecting line
Short-circuit risks improve the process window to form bit line and connecting line.
In order to solve the above technical problems, the present invention provides a kind of three-dimensional storages, comprising: be located on substrate along first party
To one or more array common sources of extension；And the first conductive pattern on one or more of array common sources
Case, comprising: the one or more connecting lines extended in a second direction are electrically connected at least one described array common source；Described in
Second direction extends and is located at the pseudo- connecting line of one or more of connecting line two sides；And extend along the second direction
And it is located at multiple bit lines of the pseudo- connecting line two sides.
In one embodiment of this invention, the pseudo- connecting line is adjacent with the bit line.
In one embodiment of this invention, at least side of one or more of connecting lines is equipped with multiple pseudo- connections
Line.
In one embodiment of this invention, one or more of connecting lines are electrically connected the multiple array common source simultaneously
In at least two.
In one embodiment of this invention, at least two interconnections in the multiple connecting line.
In one embodiment of this invention, the three-dimensional storage further includes being located at one or more of array common sources
The second conductive pattern between first conductive pattern, at least one described connecting line pass through the second conductive pattern electricity
It is connected at least one described array common source.
In one embodiment of this invention, second conductive pattern includes one or more extended along the second direction
A first conducting wire, one or more of first conducting wires are electrically connected the connecting line.
In one embodiment of this invention, it is interconnected between at least two in the multiple first conducting wire.
In one embodiment of this invention, at least one described first conducting wire is electrically connected multiple connecting lines.
In one embodiment of this invention, at least one described first conducting wire is electrically connected two adjacent connecting lines.
In one embodiment of this invention, second conductive pattern includes one or more extended along the second direction
A second conducting wire, is electrically connected the bit line.
In one embodiment of this invention, at least one described second conducting wire is also electrically connected adjacent along the second direction
Channel layer in two channel holes.
In one embodiment of this invention, second conductive pattern includes one or more extended along the second direction
A privates is electrically connected the pseudo- connecting line.
In one embodiment of this invention, at least one described pseudo- connecting line connects multiple privates.
In one embodiment of this invention, the three-dimensional storage further includes multiple conductive plungers, conductive with described first
Pattern and second conductive pattern are separately connected.
In one embodiment of this invention, the three-dimensional storage further includes multiple conductive contact blocks, is led with described first
Line and the array common source are separately connected.
In one embodiment of this invention, first conductive pattern includes a connecting line, the connecting line
Width is greater than the width of the pseudo- connecting line and/or the bit line.
In one embodiment of this invention, the first direction and the second direction are mutually perpendicular to.
Compared with prior art, the invention has the following advantages that
The two sides of connecting line in three-dimensional storage of the invention are arranged with pseudo- connecting line, reduce connecting line and bit line
Short-circuit risks.In addition, using self-alignment duplex pattern (Self- since the two sides of connecting line are arranged with pseudo- connecting line
Aligned Double Patterning, SADP) etc. techniques come when forming the first conductive pattern, provide process window protection.
In addition, connecting line can have biggish width, its resistance is reduced.
Detailed description of the invention
Fig. 1 is a kind of partial top view of three-dimensional storage.
Fig. 2 is partial sectional view of the three-dimensional storage shown in FIG. 1 along line A-A.
Fig. 3 is partial sectional view of the three-dimensional storage shown in FIG. 1 along line B-B.
Fig. 4 is partial sectional view of the three-dimensional storage shown in FIG. 1 along line C-C.
Fig. 5 is partial sectional view of the three-dimensional storage shown in FIG. 1 along line D-D.
Fig. 6 is the partial top view of the three-dimensional storage of some embodiments of the invention.
Fig. 7 is partial sectional view of the three-dimensional storage shown in fig. 6 along line A-A.
Fig. 8 is partial sectional view of the three-dimensional storage shown in fig. 6 along line B-B.
Fig. 9 is partial sectional view of the three-dimensional storage shown in fig. 6 along line C-C.
Figure 10 is partial sectional view of the three-dimensional storage shown in fig. 6 along line D-D.
Figure 11 is the partial top view of the three-dimensional storage of some embodiments of the invention.
Figure 12 is partial sectional view of the three-dimensional storage shown in Figure 11 along line A-A.
Figure 13 is partial sectional view of the three-dimensional storage shown in Figure 11 along line B-B.
Figure 14 is partial sectional view of the three-dimensional storage shown in Figure 11 along line C-C.
Figure 15 is partial sectional view of the three-dimensional storage shown in Figure 11 along line D-D.
Figure 16 is the partial top view of the three-dimensional storage of some embodiments of the invention.
Figure 17 is partial sectional view of the three-dimensional storage shown in Figure 16 along line A-A.
Figure 18 is partial sectional view of the three-dimensional storage shown in Figure 16 along line B-B.
Figure 19 is partial sectional view of the three-dimensional storage shown in Figure 16 along line C-C.
Figure 20 is partial sectional view of the three-dimensional storage shown in Figure 16 along line D-D.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
Fig. 1 is a kind of partial top view of three-dimensional storage 100.Fig. 2 is three-dimensional storage shown in FIG. 1 100 along line A-A
Partial sectional view.Fig. 3 is partial sectional view of the three-dimensional storage 100 shown in FIG. 1 along line B-B.Fig. 4 is shown in FIG. 1 three
Memory 100 is tieed up along the partial sectional view of line C-C.Fig. 5 is broken section of the three-dimensional storage 100 shown in FIG. 1 along line D-D
Figure.In conjunction with shown in reference Fig. 1-5, three-dimensional storage 100 may include substrate 100a and stack layer 100b in core space.It stacks
Layer 100b may include along the direction alternately stacked grid layer and wall vertical with substrate 100a.Stack layer 100b, which has, to hang down
Directly in substrate 100a and along the first array common source 111 and second array common source 112 of first direction D1 extension.Stack layer
100b also has the channel hole 170 perpendicular to substrate 100a, and interior be disposed with along the direction of channel hole 170 from outside to inside is deposited
Reservoir layer and channel layer.Here, memory layer may include electric charge barrier layer, electric charge capture layer and tunnel layer.Stack layer 100b
Top also have along first direction D1 extend top selection gate 160.Top selection gate 160 is located at the first array common source
Between pole 111 and second array common source 112.
Three-dimensional storage 100 can also include that the first conductive pattern 120 and second above stack layer 100b is conductive
Pattern 130.Second conductive pattern 130 is between the first conductive pattern 120 and stack layer 100b.
First conductive pattern 120 can be divided into array common source section bonding pad 120a and bitline regions according to the difference of its function
120b.Array common source bonding pad 120a is located between two bitline regions 120b.Array common source bonding pad 120a includes and
Multiple connecting lines 121 that an array common source 111 and/or second array common source 112 are electrically connected, and it is untotal with the first array
The pseudo- connecting line 122 that source electrode 111 and second array common source 112 are electrically connected.Bitline regions 120b includes multiple bit lines 123.Connection
Line 121, pseudo- connecting line 122 and the in a second direction D2 of bit line 123 extend.
Second conductive pattern 130 includes the first conducting wire 131 being electrically connected with connecting line 121, be electrically connected with bit line 123
Two conducting wires 132 and the privates 133 being electrically connected with pseudo- connecting line.
Connecting line 121, pseudo- connecting line 122 and bit line 123 are led with the first conducting wire 131, third respectively by conductive plunger 140
Line 133 and the second conducting wire 132 are separately connected.First conducting wire 131 by conductive contact block 150 and the first array common source 111 and
Second array common source 112 is separately connected.
By Fig. 1-4 it is found that only there is pseudo- connecting line on one side in the array common source bonding pad 120a of three-dimensional storage 100
122, the connecting line 121 of another side is directly adjacent with bit line 123.As the density of bit line 123 and connecting line 121 further increases
Greatly, the interval between bit line 123 and connecting line 121 becomes smaller, and bit line 123 and the short-circuit risks of connecting line 123 increase therewith.Separately
Outside, with bit line 123, the increase of 121 density of connecting line, self-alignment duplex pattern (Self-aligned Double is being used
Patterning, SADP) etc. techniques come when forming the first conductive pattern 120, process margin accordingly becomes smaller.
The embodiment of the present invention description can reduce the three-dimensional storage of the short-circuit risks between bit line and connecting line, be promoted
Process window.
Fig. 6 is the partial top view of the three-dimensional storage 200 of some embodiments of the invention.Fig. 7 is that three-dimensional shown in fig. 6 is deposited
Partial sectional view of the reservoir 200 along line A-A.Fig. 8 is partial sectional view of the three-dimensional storage 200 shown in fig. 6 along line B-B.Fig. 9
It is partial sectional view of the three-dimensional storage 200 shown in fig. 6 along line C-C.Figure 10 is three-dimensional storage shown in fig. 6 200 along D-D
The partial sectional view of line.In conjunction with shown in reference Fig. 6-10, three-dimensional storage 200 may include substrate 200a and heap in core space
Lamination 200b.Stack layer 200b may include along the direction alternately stacked grid layer and wall vertical with substrate 200a.Heap
Lamination 200b has perpendicular to substrate 200a and total along first direction D1 the first array common source 211 extended and second array
Source electrode 212.First array common source 211 and second array common source 212 are located on substrate 200a, and run through stack layer 200b.
It the upper surface of first array common source 211 and second array common source 212 can be substantially coplanar with the upper surface of stack layer 200b.
Stack layer 200b also has the channel hole 270 perpendicular to substrate 200a, interior successively to set along the direction of channel hole 270 from outside to inside
It is equipped with memory layer and channel layer.Here, memory layer may include electric charge barrier layer, electric charge capture layer and tunnel layer.It stacks
The top of layer 200b also has the top selection gate 260 extended along first direction D1.Top selection gate 260 is located at first gust
Between column common source 211 and second array common source 212.
Three-dimensional storage 200 can also include the on the first array common source 211 and second array common source 212
One conductive pattern 220.That is, the first conductive pattern 220 is located at the top of stack layer 200b.
First conductive pattern 220 can be divided into array common source section bonding pad 220a and bitline regions according to the difference of its function
220b.Array common source bonding pad 220a is located between two bitline regions 220b.Array common source bonding pad 220a includes and
Multiple connecting lines 221 that an array common source 211 and/or second array common source 212 are electrically connected, and it is untotal with the first array
Multiple pseudo- connecting lines 222 that source electrode 211 and second array common source 212 are electrically connected.Bitline regions 220b includes multiple bit lines 223.
Connecting line 221, pseudo- connecting line 222 and the in a second direction D2 of bit line 223 extend.In some embodiments, first direction D1 and
Second direction D2 is orthogonal.
In conjunction with shown in reference Fig. 6-9, multiple puppet connecting lines 222 are located at the two sides of multiple connecting lines 221, multiple bit lines 223
Positioned at the two sides of multiple pseudo- connecting lines 222.That is, pseudo- connecting line 222, between connecting line 221 and bit line 223, puppet is even
Wiring 222 is adjacently positioned with bit line 223.
Although the two sides of multiple connecting lines 221 are respectively disposed with a puppet in the three-dimensional storage 200 shown by Fig. 6-9
Connecting line 222, it is to be understood that, at least side in multiple 221 two sides of connecting line can be equipped with multiple pseudo- connecting lines 222.Example
Such as, it sets in the side of multiple connecting lines 221 there are two pseudo- connecting line 222, the other side is equipped with a pseudo- connecting line 222.Multiple companies
The number for the pseudo- connecting line 222 that 221 two sides of wiring are respectively provided with can be the same or different.
In some embodiments, the part connecting line 221 in multiple connecting lines 221 is electrically connected the first array common source simultaneously
211 and second array common source 212, to provide electric current simultaneously for the first array common source 211 and second array common source 212.
In some embodiments, connecting line 221 can be electrically connected to the first array common source by conductive contact block 250
211 and/or second array common source 212.In some embodiments, connecting line 221 can be electrically connected to by conductive plunger 240
First array common source 211 and/or second array common source 212.It is appreciated that connecting line 221 can also be otherwise
It is electrically connected to the first array common source 211 and/or second array common source 212, the present invention does not limit this.
In some embodiments, at least two connecting lines 221 in multiple connecting lines 221 are electrically connected to each other.Such as Fig. 6
It is shown, it counts from left to right, is mutually to be connected between second connecting line 221, the 4th connecting line 221 and the 6th connecting line 221
It connects.In figures 7-9, by the way that outside connecting line 221 plus by way of frame, these connecting lines 221 interconnected are showed.
It should be noted that, although illustrating only the first array common source 211 and second array common source in figures 6 to 10
212 two array common sources, it is to be understood that, three-dimensional storage 200 may include one or more array common sources.For
Three-dimensional storage 200 only includes the embodiment of an array common source, and connecting line 221 is electrically connected to the array common source.For
The embodiment of three-dimensional storage 200 including multiple array common sources, a connecting line 221 in multiple connecting lines 221 can be with
An electrical connection in multiple array common sources, can also be electrically connected at least two in multiple array common sources simultaneously.
The two sides of multiple connecting lines 221 in the three-dimensional storage 200 of the present embodiment are arranged with pseudo- connecting line 222, drop
The low short-circuit risks of connecting line 221 and bit line 223.In addition, since the two sides of multiple connecting lines 221 are arranged with pseudo- connecting line
222, the is being formed using the techniques such as self-alignment duplex pattern (Self-aligned Double Patterning, SADP)
When one conductive pattern 220, process window protection is provided.
Figure 11 is the partial top view of the three-dimensional storage 300 of some embodiments of the invention.Figure 12 is three shown in Figure 11
Memory 300 is tieed up along the partial sectional view of line A-A.Figure 13 is three-dimensional storage 300 shown in Figure 11 along the broken section of line B-B
Figure.Figure 14 is three-dimensional storage 300 shown in Figure 11 along the partial sectional view of line C-C.Figure 15 is the storage of three-dimensional shown in Figure 11
Partial sectional view of the device 300 along line D-D.In conjunction with shown in reference Figure 11-15, three-dimensional storage 300 may include in core space
Substrate 300a and stack layer 300b.Stack layer 300b may include along the direction alternately stacked grid layer vertical with substrate 300a
And wall.Stack layer 300b has perpendicular to substrate 300a and along the first array common source 311 of first direction D1 extension
With second array common source 312.First array common source 311 and second array common source 312 are located on substrate 300a, and run through
Stack layer 300b.It the upper surface of first array common source 311 and second array common source 312 can be with the upper table of stack layer 300b
Face is substantially coplanar.Stack layer 300b also has the channel hole 370 perpendicular to substrate 300a, in along channel hole 370 from outside to inside
Direction be disposed with memory layer and channel layer.Here, memory layer may include electric charge barrier layer, electric charge capture layer and
Tunnel layer.The top of stack layer 300b also has the top selection gate 360 extended along first direction D1.Top selection gate
360 between the first array common source 311 and second array common source 312.
Three-dimensional storage 300 can also include the first conductive pattern 320 and the second conductive pattern on stack layer 300b
Case 330.Second conductive pattern 330 is between the first conductive pattern 320 and stack layer 300b.That is, the second conductive pattern
Case 330 is located on the first array common source 311 and second array common source 312, and the first conductive pattern 320 is located at the second conductive pattern
In case 330.
First conductive pattern 320 can be divided into array common source section bonding pad 320a and bitline regions according to the difference of its function
320b.Array common source bonding pad 320a is located between two bitline regions 320b.Array common source bonding pad 320a includes and
Multiple connecting lines 321 that an array common source 311 and/or second array common source 312 are electrically connected, and it is untotal with the first array
Multiple pseudo- connecting lines 322 that source electrode 311 and second array common source 312 are electrically connected.Bitline regions 320b includes multiple bit lines 323.
Connecting line 321, pseudo- connecting line 322 and the in a second direction D2 of bit line 323 extend.In some embodiments, first direction D1 and
Second direction D2 is orthogonal.
In conjunction with shown in reference Figure 11-14, multiple puppet connecting lines 322 are located at the two sides of multiple connecting lines 321, multiple bit lines
323 are located at the two sides of multiple pseudo- connecting lines 322.That is, pseudo- connecting line 322 is between connecting line 321 and bit line 323,
Pseudo- connecting line 322 is adjacently positioned with bit line 323.
In some embodiments, at least two connecting lines 321 in multiple connecting lines 321 are electrically connected to each other.Such as figure
It shown in 11, counts from left to right, is mutual between second connecting line 321, the 4th connecting line 321 and the 6th connecting line 321
Connection.In Figure 12-14, by the way that outside connecting line 321 plus by way of frame, these connecting lines 321 interconnected are indicated
Out.
Connecting line 321 can be electrically connected to the first array common source 311 and/or second gust by the second conductive pattern 330
Column common source 312.Specifically, the second conductive pattern 330 includes the first conducting wire of one or more being electrically connected with connecting line 321
331.First conducting wire 331 can be extended with D2 in a second direction.
In some embodiments, it is interconnected between the first conducting wire of part 331 in multiple first conducting wires 331.Such as Figure 11
It is shown, it counts from left to right, is to interconnect between second the first conducting wire 331 and second the first conducting wire 331.In Figure 12-
In 14, by the way that outside the first conducting wire 331 plus by way of frame, these first conducting wires 331 interconnected are showed.
In some embodiments, first conducting wire 331 is electrically connected to multiple connecting lines 321.That is, multiple connections
Line 321 may be coupled to same first conducting wire 331.For example, first conducting wire 331 is electrically connected two adjacent connecting lines
321.As shown in figure 11, it counts from left to right, second connecting line 321 and third connecting line 321 are electrically connected to same first
Conducting wire 331, the 4th connecting line 321 and the 5th connecting line 321 are electrically connected to same first conducting wire 331.
In some embodiments, multiple connecting lines 321 are respectively connected to multiple first conducting wires by multiple conductive plungers 340
331.That is, each conductive plunger 340 is separately connected a connecting line 321 and first conducting wire 331.It can manage
Solution, a conductive plunger 340 can also connect multiple connecting lines 321, and the present invention does not limit this.Similarly, one
Conductive plunger 340 can connect multiple first conducting wires 331.
In some embodiments, the first conducting wire 331 can be connected to the first array common source by conductive contact block 350
311 and/or second array common source 312.That is, one or more conductive contact blocks 350 and the first conducting wire 331 and first
Array common source 311 is separately connected, and/or one or more conductive contact blocks 350 and the first conducting wire 331 and second array common source
Pole 312 is separately connected.
In some embodiments, the second conductive pattern 330 may include that the one or more second connecting with bit line 323 is led
Line 332.Second conducting wire 332 can be extended with D2 in a second direction.In some embodiments, the second conducting wire 332 can also be electrically connected
Channel layer in channel hole 370.For example, second conducting wire 332 can be electrically connected two adjacent channels of D2 in a second direction
Channel layer in hole.
In some embodiments, multiple bit lines 323 are respectively connected to multiple second conducting wires by multiple conductive plungers 340
332.That is, each conductive plunger 340 is separately connected a bit line 323 and second conducting wire 332.It is appreciated that
One conductive plunger 340 can also connect multiple bit lines 323, and the present invention does not limit this.Similarly, a conduction is inserted
Plug 340 can connect multiple second conducting wires 332.
In some embodiments, the second conductive pattern 330 may include the one or more being electrically connected with pseudo- connecting line 322
Privates 333.In some embodiments, a pseudo- connecting line 322 can be electrically connected multiple privates 333.In some realities
It applies in example, a privates 333 can be electrically connected multiple pseudo- connecting lines 322.In some embodiments, pseudo- connecting line 322 can
To be connected to privates 333 by conductive plunger 340.That is, conductive plunger 340 is separately connected pseudo- 322 He of connecting line
Privates 333.
Although the two sides of multiple connecting lines 321 are respectively disposed with one in the three-dimensional storage 300 shown by Figure 11-14
Pseudo- connecting line 322, it is to be understood that, at least side in multiple 321 two sides of connecting line can be equipped with multiple pseudo- connecting lines 322.
For example, setting in the side of multiple connecting lines 321 there are two pseudo- connecting line 322, the other side is equipped with a pseudo- connecting line 322.It is multiple
The number for the pseudo- connecting line 322 that 321 two sides of connecting line are respectively provided with can be the same or different.
In some embodiments, the part connecting line 321 in multiple connecting lines 321 is electrically connected the first array common source simultaneously
311 and second array common source 312, to provide electric current simultaneously for the first array common source 311 and second array common source 312.
It should be noted that, although illustrating only the first array common source 311 and second array common source in Figure 11-15
312 two array common sources, it is to be understood that, three-dimensional storage 300 may include one or more array common sources.For
Three-dimensional storage 300 only includes the embodiment of an array common source, and connecting line 321 is electrically connected to the array common source.For
The embodiment of three-dimensional storage 300 including multiple array common sources, a connecting line 321 in multiple connecting lines 321 can be with
An electrical connection in multiple array common sources, can also be electrically connected at least two in multiple array common sources simultaneously.
The two sides of multiple connecting lines 321 in the three-dimensional storage 300 of the present embodiment are arranged with pseudo- connecting line 322, drop
The low short-circuit risks of connecting line 321 and bit line 323.In addition, since the two sides of multiple connecting lines 321 are arranged with pseudo- connecting line
322, the is being formed using the techniques such as self-alignment duplex pattern (Self-aligned Double Patterning, SADP)
When one conductive pattern 320, process window protection is provided.
Figure 16 is the partial top view of the three-dimensional storage 400 of some embodiments of the invention.Figure 17 is three shown in Figure 16
Memory 400 is tieed up along the partial sectional view of line A-A.Figure 18 is three-dimensional storage 400 shown in Figure 16 along the broken section of line B-B
Figure.Figure 19 is three-dimensional storage 400 shown in Figure 16 along the partial sectional view of line C-C.Figure 20 is the storage of three-dimensional shown in Figure 16
Partial sectional view of the device 400 along line D-D.In conjunction with shown in reference Figure 16-20, three-dimensional storage 400 may include in core space
Substrate 400a and stack layer 400b.Stack layer 400b may include along the direction alternately stacked grid layer vertical with substrate 400a
And wall.Stack layer 400b has perpendicular to substrate 400a and along the first array common source 411 of first direction D1 extension
With second array common source 412.First array common source 411 and second array common source 412 are located on substrate 400a, and run through
Stack layer 400b.It the upper surface of first array common source 411 and second array common source 412 can be with the upper table of stack layer 400b
Face is substantially coplanar.Stack layer 400b also has the channel hole 470 perpendicular to substrate 400a, in along channel hole 470 from outside to inside
Direction be disposed with memory layer and channel layer.Here, memory layer may include electric charge barrier layer, electric charge capture layer and
Tunnel layer.The top of stack layer 400b also has the top selection gate 460 extended along first direction D1.Top selection gate
460 between the first array common source 411 and second array common source 412.
Three-dimensional storage 400 can also include the first conductive pattern 420 and the second conductive pattern on stack layer 400b
Case 430.Second conductive pattern 430 is between the first conductive pattern 420 and stack layer 400b.That is, the second conductive pattern
Case 430 is located on the first array common source 411 and second array common source 412, and the first conductive pattern 420 is located at the second conductive pattern
In case 430.
First conductive pattern 420 can be divided into array common source section bonding pad 420a and bitline regions according to the difference of its function
420b.Array common source bonding pad 420a is located between two bitline regions 420b.Array common source bonding pad 420a includes and
The connecting line 421 that an array common source 411 and/or second array common source 412 are electrically connected, and it is untotal with the first array
Multiple pseudo- connecting lines 422 that source electrode 411 and second array common source 412 are electrically connected.Bitline regions 420b includes multiple bit lines 423.
In some embodiments, the width of connecting line 421 is greater than the width of pseudo- connecting line 422 and/or bit line 423.Connecting line 421, puppet
Connecting line 422 and the in a second direction D2 of bit line 423 extend.In some embodiments, first direction D1 and second direction D2 are mutual
It is perpendicular.
In conjunction with shown in reference Figure 16-20, multiple puppet connecting lines 422 are located at the two sides of connecting line 421, multiple bit lines 423
In the two sides of multiple pseudo- connecting lines 422.That is, pseudo- connecting line 422 is between connecting line 421 and bit line 423, puppet is connected
Line 422 is adjacently positioned with bit line 423.
Connecting line 421 can be electrically connected to the first array common source 411 and/or second gust by the second conductive pattern 430
Column common source 412.Specifically, the second conductive pattern 430 includes the first conducting wire of one or more being electrically connected with connecting line 421
431.First conducting wire 431 can be extended with D2 in a second direction.
In some embodiments, it is interconnected between the first conducting wire of part 431 in multiple first conducting wires 431.Such as Figure 16
It is shown, it counts from left to right, is to interconnect between second the first conducting wire 431 and second the first conducting wire 431.In Figure 17-
In 19, by the way that outside the first conducting wire 431 plus by way of frame, these first conducting wires 431 interconnected are showed.
Connecting line 421 can be connect with multiple first conducting wires 431, can also be connect with first conducting wire 431.Some
In embodiment, connecting line 421 is respectively connected to multiple first conducting wires 431 by multiple conductive plungers 440.That is, each
A conductive plunger 440 is separately connected connecting line 421 and first conducting wire 431.It is appreciated that conductive plunger 440 can be with
Connect multiple first conducting wires 431.
In some embodiments, the first conducting wire 431 can be connected to the first array common source by conductive contact block 450
411 and/or second array common source 412.That is, one or more conductive contact blocks 450 and the first conducting wire 431 and first
Array common source 411 is separately connected, and/or one or more conductive contact blocks 450 and the first conducting wire 431 and second array common source
Pole 412 is separately connected.
In some embodiments, the second conductive pattern 430 may include that the one or more second connecting with bit line 423 is led
Line 432.Second conducting wire 432 can be extended with D2 in a second direction.In some embodiments, the second conducting wire 432 can also be electrically connected
Channel layer in channel hole 470.For example, second conducting wire 432 can be electrically connected two adjacent channels of D2 in a second direction
Channel layer in hole.
In some embodiments, multiple bit lines 423 are respectively connected to multiple second conducting wires by multiple conductive plungers 440
432.That is, each conductive plunger 440 is separately connected a bit line 323 and second conducting wire 432.It is appreciated that
One conductive plunger 440 can also connect multiple bit lines 423, and the present invention does not limit this.Similarly, a conduction is inserted
Plug 440 can connect multiple second conducting wires 432.
In some embodiments, the second conductive pattern 430 may include the one or more being electrically connected with pseudo- connecting line 422
Privates 433.In some embodiments, a pseudo- connecting line 422 can be electrically connected multiple privates 433.In some realities
It applies in example, a privates 433 can be electrically connected multiple pseudo- connecting lines 422.In some embodiments, pseudo- connecting line 422 can
To be connected to privates 433 by conductive plunger 440.That is, conductive plunger 440 is separately connected pseudo- 422 He of connecting line
Privates 433.
Although the two sides of connecting line 421 are respectively disposed with a puppet even in the three-dimensional storage 400 shown by Figure 16-19
Wiring 422, it is to be understood that, at least side in 421 two sides of connecting line can be equipped with multiple pseudo- connecting lines 422.For example, even
The side of wiring 421 is set there are two pseudo- connecting line 422, and the other side is equipped with a pseudo- connecting line 422.421 two sides of connecting line difference
The number for the pseudo- connecting line 422 having can be the same or different.
In some embodiments, connecting line 421 can be electrically connected the first array common source 411 and second array common source simultaneously
Pole 412, to provide electric current simultaneously for the first array common source 411 and second array common source 412.
It should be noted that, although illustrating only the first array common source 411 and second array common source in Figure 16-20
412 two array common sources, it is to be understood that, three-dimensional storage 400 may include one or more array common sources.For
Three-dimensional storage 400 only includes the embodiment of an array common source, and connecting line 421 is electrically connected to the array common source.For
Three-dimensional storage 400 includes the embodiment of multiple array common sources, and connecting line 421 can be with one in multiple array common sources
Electrical connection can also be electrically connected at least two in multiple array common sources simultaneously.
The two sides of connecting line 421 in the three-dimensional storage 400 of the present embodiment are arranged with pseudo- connecting line 422, reduce
The short-circuit risks of connecting line 421 and bit line 423.In addition, making since the two sides of connecting line 421 are arranged with pseudo- connecting line 422
The first conductive pattern is formed with techniques such as self-alignment duplex patterns (Self-aligned Double Patterning, SADP)
When case 420, process window protection is provided.
Compared with the three-dimensional storage 300 shown by Figure 11-15, in the first conductive pattern 420 of three-dimensional storage 400
The width of connecting line 421 is greater than the width summation of multiple connecting lines 321, and connecting line 421 has lower resistance.
Other details of three-dimensional storage part, such as wordline bonding pad, periphery interconnection etc., and the emphasis of non-present invention,
This not reinflated description.
In the context of the present invention, three-dimensional storage part can be 3D flash memory, such as 3D nand flash memory.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (18)
1. a kind of three-dimensional storage, comprising:
The one or more array common sources extended in a first direction on substrate；And
The first conductive pattern on one or more of array common sources, comprising:
The one or more connecting lines extended in a second direction are electrically connected at least one described array common source；
Extend and be located at the pseudo- connecting line of one or more of connecting line two sides along the second direction；And
Extend and be located at multiple bit lines of the pseudo- connecting line two sides along the second direction.
2. three-dimensional storage according to claim 1, which is characterized in that the puppet connecting line is adjacent with the bit line.
3. three-dimensional storage according to claim 1, which is characterized in that at least side of one or more of connecting lines
Equipped with multiple pseudo- connecting lines.
4. three-dimensional storage according to claim 1, which is characterized in that one or more of connecting lines are electrically connected simultaneously
At least two in the multiple array common source.
5. three-dimensional storage according to claim 1, which is characterized in that at least two in the multiple connecting line are mutually
Connection.
6. three-dimensional storage according to claim 1, which is characterized in that the three-dimensional storage further includes being located at described one
The second conductive pattern between a or multiple array common sources and first conductive pattern, at least one described connecting line pass through
Second conductive pattern is electrically connected at least one described array common source.
7. three-dimensional storage according to claim 6, which is characterized in that second conductive pattern includes along described second
The first conducting wire of one or more that direction extends, one or more of first conducting wires are electrically connected the connecting line.
8. three-dimensional storage according to claim 7, which is characterized in that in the multiple first conducting wire at least two it
Between interconnect.
9. three-dimensional storage according to claim 7, which is characterized in that at least one described first conducting wire electrical connection is multiple
The connecting line.
10. three-dimensional storage according to claim 9, which is characterized in that at least one described first conducting wire is electrically connected phase
Two adjacent connecting lines.
11. three-dimensional storage according to claim 6, which is characterized in that second conductive pattern includes along described
The second conducting wire of one or more that two directions extend, is electrically connected the bit line.
12. three-dimensional storage according to claim 11, which is characterized in that at least one described second conducting wire is also electrically connected
Channel layer in two channel holes adjacent along the second direction.
13. three-dimensional storage according to claim 6, which is characterized in that second conductive pattern includes along described
One or more privates that two directions extend are electrically connected the pseudo- connecting line.
14. three-dimensional storage according to claim 13, which is characterized in that at least one described pseudo- connecting line connection is multiple
The privates.
15. three-dimensional storage according to claim 6, which is characterized in that the three-dimensional storage further includes multiple conductions
Plug is separately connected with first conductive pattern and second conductive pattern.
16. three-dimensional storage according to claim 7, which is characterized in that the three-dimensional storage further includes multiple conductions
Contact block is separately connected with first conducting wire and the array common source.
17. three-dimensional storage according to claim 1, which is characterized in that first conductive pattern includes described in one
Connecting line, the width of the connecting line are greater than the width of the pseudo- connecting line and/or the bit line.
18. three-dimensional storage according to claim 1, which is characterized in that the first direction and the second direction phase
It is mutually vertical.
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| CN112185967A (en) * | 2020-09-29 | 2021-01-05 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180174661A1 (en) * | 2016-12-21 | 2018-06-21 | Kwang-Soo Kim | Three-dimensional semiconductor memory devices including stair structures and dummy electrodes |
| CN108573979A (en) * | 2017-03-07 | 2018-09-25 | 三星电子株式会社 | Semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180174661A1 (en) * | 2016-12-21 | 2018-06-21 | Kwang-Soo Kim | Three-dimensional semiconductor memory devices including stair structures and dummy electrodes |
| CN108573979A (en) * | 2017-03-07 | 2018-09-25 | 三星电子株式会社 | Semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112185967A (en) * | 2020-09-29 | 2021-01-05 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112185967B (en) * | 2020-09-29 | 2021-11-09 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
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