CN109344541B - Method for judging wiring direction according to regional wiring congestion degree - Google Patents

Method for judging wiring direction according to regional wiring congestion degree Download PDF

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Publication number
CN109344541B
CN109344541B CN201811291030.7A CN201811291030A CN109344541B CN 109344541 B CN109344541 B CN 109344541B CN 201811291030 A CN201811291030 A CN 201811291030A CN 109344541 B CN109344541 B CN 109344541B
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wiring
ratio
plb
signals
available
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CN109344541A (en
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刘桂林
王海力
连荣椿
马明
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Jingwei Qili Beijing Technology Co ltd
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Jingwei Qili Beijing Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Abstract

The invention discloses a method for judging a wiring direction according to the wiring congestion degree of an area, which comprises the following steps: respectively calculating the ratio I of the number of inputtable signals to the number of available ports of input signals of a plurality of basic logic units PLB in the FPGA circuit and the ratio O of the number of available ports of receiving signals to the number of available ports of output signals of a next-stage unit of the PLB; selecting the larger one of I and O of each PLB as the value of the congestion degree DC of the corresponding PLB; the plurality of DCs of the plurality of PLBs are arranged in descending order and are wired sequentially. The reverse wiring or the forward wiring can be freely selected according to the value of the congestion degree DC and the judgment of the input/output, so that the wiring time can be effectively reduced, and the result that the wiring of a high-congestion-degree net cannot be finished due to a single wiring mode can be effectively reduced.

Description

Method for judging wiring direction according to regional wiring congestion degree
Technical Field
The invention relates to the field of FPGA (field programmable gate array) wiring algorithms, in particular to a method for judging a wiring direction according to regional wiring congestion degree.
Background
At present, when the FPGA design with high utilization rate is wired, the problem of wiring failure is often encountered. The reason for analyzing from the aspect of wiring architecture is mainly two points: firstly, the wiring resource of the FPGA is manufactured in advance, and is tense relative to the design with high utilization rate; secondly, the input and output wiring resources of the basic logic unit PLB of the FPGA are separated from each other and cannot be used in a mixed manner.
Disclosure of Invention
The invention aims to solve the problem that a high-crowdedness wire net cannot be wired due to the fact that a single wiring mode occupies the wire net.
In order to achieve the above object, the present invention provides a method for determining a routing direction according to a degree of congestion of area routing, comprising the steps of:
respectively calculating the ratio I of the number of inputtable signals to the number of available ports of input signals and the ratio O of the number of outputtable signals to the number of available ports of output signals of a plurality of basic logic units PLB in the FPGA circuit;
the ratios I and O corresponding to the PLBs are arranged in a congestion degree DC sequence in the descending order, and the wiring is sequentially performed.
Preferably, the step of arranging the ratios I and O corresponding to the PLBs into a congestion degree DC sequence in descending order, and sequentially performing wiring, wherein when the PLBs corresponding to the ratio I are wired, the input signal available port of the PLB is wired in a reverse wiring manner; when the PLB wiring corresponding to the ratio O is carried out, the output signal available port of the PLB adopts the forward wiring mode for wiring.
Preferably, the method further comprises the steps of: and marking the end point of the wiring of the PLB every time the wiring of any PLB input or output port is completed.
Preferably, the method further comprises the steps of: and checking the marked ports in real time, and recalculating the ratio I and the ratio O according to the number of inputtable signals, the number of available ports of input signals, the number of outputtable signals and the number of available ports of output signals of each PLB after checking so as to adjust the DC sequence optimization wiring.
Preferably, the step of arranging the ratios I and O corresponding to the PLBs into the congestion degree DC sequence in descending order and sequentially performing routing may be replaced by the step of:
selecting the larger one of the ratio I and the ratio O of each PLB as the crowding degree DC of the corresponding PLB;
the plurality of DCs of the plurality of PLBs are arranged in a congestion degree DC sequence in descending order, and the wiring is performed sequentially.
Further preferably, the plurality of DCs of the plurality of PLBs are arranged in a congestion DC sequence from large to small, and the step of wiring is performed sequentially, wherein when the value of the DC is a ratio I, that is, the ratio I is greater than a ratio O, an available port of an input signal of the PLB is wired in a reverse wiring manner; when the DC value is the ratio O, namely the ratio I is smaller than the ratio O, the available port of the output signal of the PLB adopts a forward wiring mode for wiring.
The invention has the advantages that: the reverse wiring or the forward wiring can be freely selected according to the value of the congestion degree DC and the judgment of input/output, so that the wiring time can be effectively reduced, and the result that the wiring of a high-congestion-degree net cannot be finished due to a single wiring mode can be effectively reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for determining routing direction based on area routing congestion;
fig. 2 is a flowchart of a method for determining a wiring direction according to the PLB-MAX congestion degree in the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a flowchart of a method for determining a routing direction according to a degree of area routing congestion. As shown in fig. 1, a method for determining a wiring direction according to a degree of wiring congestion in an area includes the steps of:
step S110, respectively calculating a ratio I of the number of inputtable signals to the number of input signal available ports and a ratio O of the number of outputtable signals to the number of output signal available ports of a plurality of basic logic units PLB in the FPGA circuit.
Specifically, the ratio I is I x (x =1,2,3 \8230; n) and the ratio O is O x (x =1,2,3 \8230; n). For example, when the FPGA contains two PLBs, there is a ratio I of the number of inputtable signals to the number of ports available for input signals for the first PLB 1 And the ratio O of the number of available ports for receiving signals to the number of available ports for outputting signals of the next stage unit of the first PLB 1 Number of signals inputted to the second PLBRatio I to the number of available ports of the input signal 2 And the ratio O of the number of ports available for receiving signals to the number of ports available for outputting signals of the next stage unit of the second PLB 2 。
In step S120, the ratios I and O corresponding to the PLBs are arranged in the congestion degree DC sequence in descending order, and the wiring is performed sequentially.
When the PLB wiring corresponding to the ratio I is performed, step S121 is executed, and the available port of the input signal of the PLB is wired in a reverse wiring manner; when the PLB wiring corresponding to the ratio O is performed, step S122 is performed, and the output signal available port of the PLB is wired in a forward wiring manner.
In step S130, each time the wiring of any PLB input or output port is completed, the port of the wiring end of the PLB is marked.
Step S140, the marked ports are checked in real time, and the ratio I and the ratio O are recalculated according to the checked number of inputtable signals, the checked number of available ports of input signals, the checked number of available ports of outputtable signals and the checked number of available ports of output signals of each PLB.
Then step S120 is executed again to adjust the DC sequence, and then the subsequent steps are executed in sequence to optimize the wiring.
In a specific embodiment, the original step S120 is refined, and a judgment formula of the ratio I and the ratio O inside a single PLB is introduced. As shown in fig. 2, a flow chart of a method for determining a wiring direction of PLB-MAX congestion degree includes the steps of:
step S110, respectively calculating a ratio I of the number of signals that can be input to the number of available ports for input signals and a ratio O of the number of signals that can be output to the number of available ports for output signals of a plurality of basic logic units PLB in the FPGA circuit.
Specifically, the ratio I is I x (x =1,2,3 \8230; n) and the ratio O is O x (x =1,2,3 \8230; n). For example, when the FPGA contains two PLBs, there is a ratio I of the number of inputtable signals to the number of ports available for input signals for the first PLB 1 And the ratio O of the number of available ports for receiving signals to the number of available ports for outputting signals of the next stage unit of the first PLB 1 The first stepRatio I of number of inputtable signals to number of ports available for input signals of two PLBs 2 And the ratio O of the number of ports available for receiving signals to the number of ports available for outputting signals of the next stage unit of the second PLB 2 。
Step S210, selects the larger one of the ratio I and the ratio O of each PLB as the congestion degree DC of the corresponding PLB.
Specifically, DC is DC x ＝MAX{I x ，O x And (x =1,2,3 \8230; n). For example, when an FPGA contains two PLBs, there is a DC value DC of the first PLB 1 ＝MAX{I 1 ，O 1 DC value of the first PLB DC 2 ＝MAX{I 2 ，O 2 }。
In step S220, the plurality of DCs of the plurality of PLBs are arranged in a congestion degree DC sequence in descending order, and the wirings are sequentially performed.
When the DC value is the ratio I, that is, the ratio I is greater than the ratio O, step S221 is executed, and the available port of the input signal of the PLB is wired in a reverse wiring manner; when the DC value is the ratio O, that is, the ratio I is smaller than the ratio O, step S222 is executed, and the available port of the output signal of the PLB is wired in a forward wiring manner.
In step S130, each time the wiring of any PLB input or output port is completed, the port of the wiring end of the PLB is marked.
Step S140, the marked ports are checked in real time, and the ratio I and the ratio O are recalculated according to the checked number of inputtable signals, the checked number of available ports for outputtable signals, and the checked number of available ports for outputtable signals of each PLB.
Then, step S210 is executed again to adjust the DC sequence, and then the subsequent steps are executed in sequence to optimize the wiring.
The invention provides a method for judging the wiring direction according to the wiring congestion degree of a region, which can freely select reverse wiring or forward wiring according to the value of the congestion degree DC and the judgment of input/output, can effectively reduce the wiring time, and can effectively reduce the result that a high-congestion-degree net cannot finish wiring due to a single wiring mode.
Due to the introduction of the congestion degree DC judging mode, the selection of forward wiring or reverse wiring in the wiring process can be judged more effectively, compared with a mode of integrally evaluating the input/output of a single PLB, the input/output of the PLB is processed separately, and the flexibility in the wiring process is improved.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (5)

1. A method for judging a wiring direction according to a regional wiring congestion degree, comprising the steps of:
respectively calculating the ratio I of the number of inputtable signals to the number of available ports of input signals and the ratio O of the number of outputtable signals to the number of available ports of output signals of a plurality of basic logic units PLBs in the FPGA circuit;
arranging a plurality of ratios I and ratios O corresponding to a plurality of PLBs into a congestion degree DC sequence according to the sequence from large to small, and sequentially carrying out wiring;
when the PLB corresponding to the ratio I is wired, the available port of the input signal of the PLB is wired in a reverse wiring mode; when the PLB corresponding to the ratio O is wired, the available port of the output signal of the PLB is wired in a forward wiring mode.
2. The method of claim 1, further comprising the step of: and marking the end point of the wiring of the PLB every time the wiring of any PLB input or output port is completed.
3. The method according to any of claims 1 or 2, further comprising the step of: and checking the marked ports in real time, and recalculating the ratio I and the ratio O according to the checked number of inputtable signals, the checked number of available ports of the input signals, the checked number of available ports of the outputtable signals and the checked number of available ports of the output signals, thereby adjusting the DC sequence optimization wiring.
4. The method according to claim 1, wherein the step of arranging the ratios I and O corresponding to the PLBs into the congestion degree DC sequence in descending order may be replaced by the step of:
selecting the larger one of the ratio I and the ratio O of each PLB as the congestion degree DC of the corresponding PLB;
the plurality of DCs of the plurality of PLBs are arranged in a congestion degree DC sequence in descending order, and the wiring is performed sequentially.
5. The method of claim 4, wherein the step of sequentially routing the plurality of DCs of the PLBs in a congestion DC sequence is performed, wherein when the value of the DC is a ratio I, that is, the ratio I is greater than a ratio O, the ports available for the input signals of the PLBs are routed in a reverse routing manner; and when the DC value is a ratio O, namely the ratio I is smaller than the ratio O, the available port of the output signal of the PLB adopts a forward wiring mode for wiring.
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Citations (4)

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Publication number Priority date Publication date Assignee Title
US5594363A (en) * 1995-04-07 1997-01-14 Zycad Corporation Logic cell and routing architecture in a field programmable gate array
JP2010287807A (en) * 2009-06-15 2010-12-24 Sharp Corp Method for arrangement and wiring of lsi having narrow-width arrangement and wiring region
CN103886137A (en) * 2014-03-03 2014-06-25 西安电子科技大学 Method for implementing quick locating and wiring of field programmable gate array (FPGA)
WO2017208901A1 (en) * 2016-05-30 2017-12-07 国立研究開発法人産業技術総合研究所 Semiconductor computing device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594363A (en) * 1995-04-07 1997-01-14 Zycad Corporation Logic cell and routing architecture in a field programmable gate array
JP2010287807A (en) * 2009-06-15 2010-12-24 Sharp Corp Method for arrangement and wiring of lsi having narrow-width arrangement and wiring region
CN103886137A (en) * 2014-03-03 2014-06-25 西安电子科技大学 Method for implementing quick locating and wiring of field programmable gate array (FPGA)
WO2017208901A1 (en) * 2016-05-30 2017-12-07 国立研究開発法人産業技術総合研究所 Semiconductor computing device

Non-Patent Citations (1)

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Title
基于异步串行链接的FPGA布线算法;商信华;《控制工程》;20170120(第01期);33-39 *

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