CN109344541A - A method of wiring direction is determined according to area routing crowding - Google Patents
A method of wiring direction is determined according to area routing crowding Download PDFInfo
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- CN109344541A CN109344541A CN201811291030.7A CN201811291030A CN109344541A CN 109344541 A CN109344541 A CN 109344541A CN 201811291030 A CN201811291030 A CN 201811291030A CN 109344541 A CN109344541 A CN 109344541A
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- plb
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- crowding
- sequence
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Architecture (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of methods that wiring direction is determined according to area routing crowding, comprising steps of calculate separately multiple basic logic unit PLB in FPGA circuitry can input signal quantity and input signal available port quantity ratio I and PLB next stage unit reception signal available port quantity and output signal available port quantity ratio O；A biggish side in the I and O of each PLB is chosen, the value of the crowding DC as corresponding PLB；Multiple DC of multiple PLB are arranged according to sequence from big to small, are sequentially routed.It is reversely routed according to the value of crowding DC and the judgement unrestricted choice of input/output or forward direction is routed, can effectively reduced high crowding gauze caused by wiring time and single wire laying mode and be unable to complete wiring ground result.
Description
Technical field
The present invention relates to FPGA Routing Algorithm field more particularly to it is a kind of according to area routing crowding determine wiring side
To method.
Background technique
Currently, being frequently run onto the problem of wiring fails when the FPGA design to high usage is routed.From wiring
Analysis, reason essentially consist in two o'clock in terms of framework: firstly, the interconnection resource of FPGA is previously fabricated completion, relative to height
It is more nervous for the design of utilization rate；Secondly, the input of the basic logic unit PLB of FPGA, output interconnection resource are mutual
Separation, it cannot use with.
Summary of the invention
It is an object of the invention to solve single wire laying mode to cause the gauze of high crowding to be unable to complete gauze occupancy
Wiring.
In order to achieve the above objectives, the present invention provides it is a kind of according to area routing crowding determine wiring direction method,
Comprising steps of
Calculate separately multiple basic logic unit PLB in FPGA circuitry can input signal quantity and input signal can
With the ratio O of the ratio I of port number and exportable number of signals and output signal available port quantity；
The corresponding multiple ratio Is of multiple PLB and ratio O are arranged as crowding DC sequence according to sequence from big to small,
Sequentially it is routed.
Preferably, the corresponding multiple ratio Is of multiple PLB and ratio O are arranged as crowding according to sequence from big to small
DC sequence, the step of sequentially wiring, wherein when the corresponding PLB wiring of progress ratio I, the input signal of PLB is available
Port is routed using reversed wire laying mode；When the corresponding PLB wiring of progress ratio O, the output signal available port of PLB is adopted
It is routed with positive wire laying mode.
Preferably, any PLB input of every completion or the wiring of output port are further comprised the steps of:, i.e., it is whole to the wiring of PLB
The port of point is marked.
Preferably, further comprise the steps of: and marked port checked in real time, according to each PLB after investigation can be defeated
Enter number of signals, input signal available port quantity, exportable number of signals and output signal available port quantity to recalculate
Ratio I and ratio O, and then adjust the wiring of DC sequence optimisation.
Preferably, the corresponding multiple ratio Is of multiple PLB and ratio O are arranged as crowding according to sequence from big to small
DC sequence can be replaced step the step of sequentially wiring:
A biggish side in the ratio I and ratio O of each PLB is chosen, as the crowding DC of corresponding PLB；
Multiple DC of multiple PLB are arranged as crowding DC sequence according to sequence from big to small, are sequentially routed.
It is further preferred that multiple DC of multiple PLB are arranged as crowding DC sequence according to sequence from big to small,
The step of being sequentially routed, wherein when DC value is ratio I, i.e., when ratio I is greater than ratio O, the input signal of PLB can
It is routed with port using reversed wire laying mode；When DC value is ratio O, i.e., when ratio I is less than ratio O, the output letter of PLB
Number available port is using positive wire laying mode wiring.
The present invention has the advantages that according to the reversed cloth of judgement unrestricted choice of the value of crowding DC and input/output
Line or positive wiring, can effectively reduce caused by wiring time and single wire laying mode that high crowding gauze can not be complete
At wiring ground result.
Detailed description of the invention
In order to become apparent from the technical solution for illustrating the embodiment of the present invention, below embodiment will be described in required use
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings others
Attached drawing.
Fig. 1 is a kind of method flow diagram that wiring direction is determined according to area routing crowding；
Fig. 2 is that a kind of PLB-MAX crowding of the embodiment of the present invention determines the method flow diagram of wiring direction.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
Member's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Fig. 1 is a kind of method flow diagram that wiring direction is determined according to area routing crowding.As shown in Figure 1, a kind of
Determine that the method for wiring direction, step include: according to area routing crowding
Step S110, calculate separately multiple basic logic unit PLB in FPGA circuitry can input signal quantity with it is defeated
Enter the ratio I of signal available port quantity and the ratio O of exportable number of signals and output signal available port quantity.
Specifically, ratio I Ix(x=1,2,3 ... n), and ratio O is Ox(x=1,2,3 ... n).For example, working as FPGA
When comprising two PLB, there are the first PLB can input signal quantity and input signal available port quantity ratio I1With
The ratio O of reception the signal available port quantity and output signal available port quantity of one PLB next stage unit1, the 2nd PLB
Can input signal quantity and input signal available port quantity ratio I2With the reception signal of the 2nd PLB next stage unit
The ratio O of available port quantity and output signal available port quantity2。
The corresponding multiple ratio Is of multiple PLB and ratio O are arranged as according to sequence from big to small crowded by step S120
DC sequence is spent, is sequentially routed.
Wherein, when the corresponding PLB wiring of progress ratio I, S121, the input signal available port of PLB are thened follow the steps
It is routed using reversed wire laying mode；When the corresponding PLB wiring of progress ratio O, S122, the output signal of PLB are thened follow the steps
Available port is using positive wire laying mode wiring.
Step S130, it is every to complete any PLB input or the wiring of output port, i.e., to the port of the wiring terminal of PLB into
Line flag.
Step S140 in real time checks marked port, according to each PLB after investigation can input signal number
Amount, input signal available port quantity, exportable number of signals and output signal available port quantity recalculate ratio I and
Ratio O.
It is then re-execute the steps S120, adjusts DC sequence, then sequentially execute subsequent step, optimization wiring.
In a specific embodiment, former step S120 has been refined, ratio I and ratio O inside single PLB are introduced
Judgment formula.As shown in Fig. 2, a kind of PLB-MAX crowding determines the method flow diagram of wiring direction, step includes:
Step S110, calculate separately multiple basic logic unit PLB in FPGA circuitry can input signal quantity with it is defeated
Enter the ratio I of signal available port quantity and the ratio O of exportable number of signals and output signal available port quantity.
Specifically, ratio I Ix(x=1,2,3 ... n), and ratio O is Ox(x=1,2,3 ... n).For example, working as FPGA
When comprising two PLB, there are the first PLB can input signal quantity and input signal available port quantity ratio I1With
The ratio O of reception the signal available port quantity and output signal available port quantity of one PLB next stage unit1, the 2nd PLB
Can input signal quantity and input signal available port quantity ratio I2With the reception signal of the 2nd PLB next stage unit
The ratio O of available port quantity and output signal available port quantity2。
Step S210 chooses a biggish side in the ratio I and ratio O of each PLB, as gathering around for corresponding PLB
Squeeze degree DC.
Specifically, DC DCx=MAX { Ix, Ox(x=1,2,3 ... n).For example, being deposited when FPGA includes two PLB
In the DC value DC of the first PLB1=MAX { I1, O1, the DC value DC of the first PLB2=MAX { I2, O2}。
Multiple DC of multiple PLB are arranged as crowding DC sequence according to sequence from big to small, sequentially by step S220
It is routed.
Wherein, when DC value is ratio I, i.e., when ratio I is greater than ratio O, S221, the input letter of PLB are thened follow the steps
Number available port is routed using reversed wire laying mode；When DC value is ratio O, i.e., when ratio I is less than ratio O, then execute step
The output signal available port of rapid S222, PLB are using positive wire laying mode wiring.
Step S130, it is every to complete any PLB input or the wiring of output port, i.e., to the port of the wiring terminal of PLB into
Line flag.
Step S140 in real time checks marked port, according to each PLB after investigation can input signal number
Amount, input signal available port quantity, exportable number of signals and output signal available port quantity recalculate ratio I and
Ratio O.
It is then re-execute the steps S210, adjusts DC sequence, then sequentially execute subsequent step, optimization wiring.
The present invention provides a kind of methods that wiring direction is determined according to area routing crowding, according to crowding DC's
Value and the judgement unrestricted choice of input/output are reversely routed or positive wiring, can effectively reduce wiring time, with
And high crowding gauze caused by single wire laying mode is unable to complete wiring ground result.
The introducing of crowding DC decision procedure can more effectively judge positive wiring or reversed wiring in wiring process
Selection the input/output of PLB is separately handled compared to the mode that total evaluation is done in the input/output to single PLB,
Improve the flexibility ratio in wiring process.
Above specific embodiment has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
Illustrate, it should be understood that the above is only a specific embodiment of the invention, the protection that is not intended to limit the present invention
Range, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should be included in this
Within the protection scope of invention.
Claims (6)
1. a kind of method for determining wiring direction according to area routing crowding, which is characterized in that comprising steps of
Calculate separately multiple basic logic unit PLB in FPGA circuitry can input signal quantity and input signal available port
The ratio O of the ratio I of quantity and exportable number of signals and output signal available port quantity；
The corresponding multiple ratio Is of the multiple PLB and ratio O are arranged as crowding DC sequence according to sequence from big to small,
Sequentially it is routed.
2. the method according to claim 1, wherein described by the corresponding multiple ratio Is of the multiple PLB and ratio
Value O is arranged as crowding DC sequence according to sequence from big to small, the step of sequentially wiring, wherein when progress ratio I pair
When the PLB wiring answered, the input signal available port of the PLB is routed using reversed wire laying mode；When carrying out, ratio O is corresponding
When PLB is routed, the output signal available port of the PLB is using positive wire laying mode wiring.
3. the method according to claim 1, wherein further comprising the steps of: any PLB input of every completion or output end
The wiring of mouth, i.e., be marked the port of the wiring terminal of the PLB.
4. according to claim 1 or method described in 3 any claims, which is characterized in that further comprise the steps of: in real time to having marked
The port of note is checked, according to each PLB after investigation can input signal quantity, input signal available port quantity, can be defeated
Number of signals and output signal available port quantity recalculate ratio I and ratio O out, and then adjust the wiring of DC sequence optimisation.
5. the method according to claim 1, wherein described by the corresponding multiple ratio Is of the multiple PLB and ratio
Value O, which is arranged as crowding DC sequence according to sequence from big to small, can be replaced step the step of sequentially wiring:
A biggish side in the ratio I and ratio O of each PLB is chosen, as the crowding DC of corresponding PLB；
Multiple DC of the multiple PLB are arranged as crowding DC sequence according to sequence from big to small, are sequentially routed.
6. according to the method described in claim 5, it is characterized in that, multiple DC by the multiple PLB according to from greatly to
Small sequence is arranged as crowding DC sequence, the step of sequentially wiring, wherein when DC value is ratio I, i.e. ratio I
When greater than ratio O, the input signal available port of the PLB is routed using reversed wire laying mode；When DC value is ratio O,
When i.e. ratio I is less than ratio O, the output signal available port of the PLB is using positive wire laying mode wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811291030.7A CN109344541B (en) | 2018-10-31 | 2018-10-31 | Method for judging wiring direction according to regional wiring congestion degree |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811291030.7A CN109344541B (en) | 2018-10-31 | 2018-10-31 | Method for judging wiring direction according to regional wiring congestion degree |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109344541A true CN109344541A (en) | 2019-02-15 |
| CN109344541B CN109344541B (en) | 2023-01-31 |
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| CN201811291030.7A Active CN109344541B (en) | 2018-10-31 | 2018-10-31 | Method for judging wiring direction according to regional wiring congestion degree |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5594363A (en) * | 1995-04-07 | 1997-01-14 | Zycad Corporation | Logic cell and routing architecture in a field programmable gate array |
| JP2010287807A (en) * | 2009-06-15 | 2010-12-24 | Sharp Corp | Method for arrangement and wiring of lsi having narrow-width arrangement and wiring region |
| CN103886137A (en) * | 2014-03-03 | 2014-06-25 | 西安电子科技大学 | Method for implementing quick locating and wiring of field programmable gate array (FPGA) |
| WO2017208901A1 (en) * | 2016-05-30 | 2017-12-07 | 国立研究開発法人産業技術総合研究所 | Semiconductor computing device |
-
2018
- 2018-10-31 CN CN201811291030.7A patent/CN109344541B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5594363A (en) * | 1995-04-07 | 1997-01-14 | Zycad Corporation | Logic cell and routing architecture in a field programmable gate array |
| JP2010287807A (en) * | 2009-06-15 | 2010-12-24 | Sharp Corp | Method for arrangement and wiring of lsi having narrow-width arrangement and wiring region |
| CN103886137A (en) * | 2014-03-03 | 2014-06-25 | 西安电子科技大学 | Method for implementing quick locating and wiring of field programmable gate array (FPGA) |
| WO2017208901A1 (en) * | 2016-05-30 | 2017-12-07 | 国立研究開発法人産業技術総合研究所 | Semiconductor computing device |
Non-Patent Citations (1)
| Title |
|---|
| 商信华: "基于异步串行链接的FPGA布线算法", 《控制工程》 * |
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| CN109344541B (en) | 2023-01-31 |
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