CN109309003A - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN109309003A CN109309003A CN201710616689.4A CN201710616689A CN109309003A CN 109309003 A CN109309003 A CN 109309003A CN 201710616689 A CN201710616689 A CN 201710616689A CN 109309003 A CN109309003 A CN 109309003A
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 230000005669 field effect Effects 0.000 title claims abstract description 43
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- 238000000227 grinding Methods 0.000 claims abstract description 45
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- 239000000758 substrate Substances 0.000 claims abstract description 36
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- 239000000463 material Substances 0.000 claims description 28
- 238000005137 deposition process Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
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- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
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- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
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- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910015345 MOn Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
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- 229910010037 TiAlN Inorganic materials 0.000 description 1
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- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
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- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
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- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
Abstract
A kind of forming method of fin formula field effect transistor, comprising: provide substrate, the substrate surface has fin；There is interlayer dielectric layer, the height of the interlayer dielectric layer is higher than the fin top surface on the substrate；The part of the surface exposure of the fin is simultaneously formed with opening in the interlayer dielectric layer；The bottom and side wall surface of the opening has gate dielectric layer；In gate dielectric layer chemical mechanical grinding stop-layer formed above；It is higher than at the top of the interlayer dielectric layer at the top of chemical mechanical grinding stop-layer metal layer formed above, the full opening of the metal layer filling and the metal layer；Wherein, the chemical mechanical grinding stop-layer is different from the metal layer.Before forming metal layer, forming chemical mechanical grinding stop-layer can be handled the present invention by the chemical mechanical grinding stop-layer with stepped process, improve metal gate high consistency.
Description
Technical field
The present invention relates to semiconductor field more particularly to a kind of forming methods of fin formula field effect transistor.
Background technique
In semiconductor fabrication, with the development trend of super large-scale integration, integrated circuit feature size persistently subtracts
It is small.For the reduction of meeting market's demand size, the channel length of MOSFET field-effect tube is also corresponding constantly to be shortened.However, with device
The shortening of part channel length, device source electrode between drain electrode at a distance from also shorten therewith, therefore grid to the control ability of channel with
Variation, the difficulty of grid voltage pinch off (pinch off) channel is also increasing, so that sub-threshold leakage
(subthreshold leakage) phenomenon, i.e., so-called short-channel effect (SCE:short-channel effects) are more held
Easily occur.
Therefore, for the reduction of better meeting market's demand size, semiconductor technology gradually starts from planar MOSFET crystal
Pipe to more high effect three-dimensional transistor transient, such as fin field effect pipe (FinFET).In FinFET, grid are extremely
Ultra-thin body (fin) can be controlled from two sides less, there is control of the grid more much better than than planar MOSFET devices to channel
Ability can be good at inhibiting short-channel effect；And FinFET has better existing integrated circuit relative to other devices
The compatibility of manufacturing technology.
In order to further increase the performance of fin formula field effect transistor, the gate dielectric layer uses high K dielectric material, described
Gate electrode layer uses metal, i.e. fin formula field effect transistor constitutes high-K metal gate (High-kMetalGate, HKMG) transistor,
The fin formula field effect transistor of the high-K metal gate structure can be formed using rear grid (GateLast) technique.In the prior art,
The gate electrode metal layer of substitution is ground using the method for chemical mechanical grinding, until exposing oxide isolation layer, is held
The scraping of oxide isolation layer is easily caused to be recessed, so as to cause the inconsistent and defect of gate height.
Summary of the invention
When preparing fin formula field effect transistor the purpose of the present invention is to solve the rear grid technique of above-mentioned utilization, the prior art
In directly adopt the method for chemical mechanical grinding the gate electrode metal layer of substitution be ground, be easy to cause oxide isolation
Layer scraping recess, so as to cause gate height consistency and defect the problem of, the following technical solution is provided:
A kind of forming method of fin formula field effect transistor, comprising: provide substrate, the substrate surface has fin；Institute
Stating has interlayer dielectric layer on substrate, the height of the interlayer dielectric layer is higher than the fin top surface；The portion of the fin
The exposure of point surface is simultaneously formed with opening in the interlayer dielectric layer；The bottom and side wall surface of the opening has gate medium
Layer；In gate dielectric layer chemical mechanical grinding stop-layer formed above；In chemical mechanical grinding stop-layer metal layer formed above, institute
It states and is higher than at the top of the interlayer dielectric layer at the top of the full opening of metal layer filling and the metal layer.
Preferably, the metal layer is removed using chemical mechanical milling tech, until exposing the chemical mechanical grinding
Stop-layer；Then, using dry etch process etching processing until exposing gate dielectric layer.
Preferably, before the chemical mechanical grinding stop-layer is formed, workfunction layers are formed on gate dielectric layer.
Preferably, the material of the chemical mechanical grinding stop-layer is cobalt, aluminium or copper.
Preferably, the chemical mechanical grinding stop-layer with a thickness of 20-300A.
Preferably, the workfunction layers with a thickness of 15-100A.
Preferably, the technique for forming the chemical mechanical grinding stop-layer is atom layer deposition process.
Preferably, the metal layer is tungsten metal layer.
Preferably, the gate dielectric layer includes high-K gate dielectric layer and cap layer one.
Preferably, the opening is formed after removing pseudo- gate electrode by the pseudo- grid structure comprising pseudo- gate electrode layer.
Preferably, the pseudo- gate electrode layer material is polysilicon.
Preferably, the transistor is p-type fin formula field effect transistor, and the workfunction layers are p-type work function gold
Belong to layer.
Preferably, the transistor is N-type fin formula field effect transistor, and the workfunction layers are N-type work function gold
Belong to layer.
Preferably, after dry etch process etching processing, cap layer two is formed, planarizes cap layer two.
Preferably, the cap layer one or cap layer two are silicon nitride layer.
Preferably, the flatening process is chemical mechanical milling tech.
Preferably, while dry etch process etching processing, the partial metal layers and work function in the opening are removed
Metal layer forms recessed.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of fin formula field effect transistor provided by the invention forms chemical machinery before forming metal layer
Polish stop layer can be handled with stepped process, be gone using chemical mechanical grinding by the chemical mechanical grinding stop-layer
Except metal layer until exposure chemical mechanical grinding stop-layer, further dry etching processing, to will not be made to oxide isolation layer
At influence, can be very good to improve metal gate high consistency.
Detailed description of the invention
Fig. 1 to Fig. 9 is the corresponding structural schematic diagram of each step of forming method of a fin formula field effect transistor.
Figure 10 to Figure 15 is each step counter structure in one embodiment of forming method of fin formula field effect transistor of the present invention
Schematic diagram.
Specific embodiment
Fig. 1 to Fig. 9 is the corresponding structural schematic diagram of each step of forming method of a fin formula field effect transistor.With reference to Fig. 1
To 9, the forming method of the fin formula field effect transistor the following steps are included:
With reference to Fig. 1, semiconductor base is formed, the semiconductor base includes substrate 100, protrudes from the substrate 100
Fin 101.There is pseudo- grid structure (not indicating), dummy gate structure includes polygate electrodes 120, institute on the substrate 100
Stating has interlayer dielectric layer on substrate 100, the height of the interlayer dielectric layer 110 is higher than pseudo- grid structure, specifically, described partly to lead
Body substrate further includes the source-drain area 140 positioned at pseudo- grid structure two sides.
With reference to Fig. 2, to 110 mechanical lapping of interlayer dielectric layer until exposing the polygate electrodes 120.
With reference to Fig. 3, the part of the surface that the polygate electrodes 120 expose fin 101 is removed, in the inter-level dielectric
Opening 130 is formed in layer 110.
With reference to Fig. 4, gate dielectric layer is formed in the bottom and side wall of the opening 130 and the interlayer dielectric layer 110
121, workfunction layers 122 are then formed on the gate dielectric layer 121.
With reference to Fig. 5, metal layer 123 is formed in the workfunction layers 122, the filling of metal layer 123 is full described
It is higher than 122 top of workfunction layers at the top of opening and the metal layer 123.
With reference to Fig. 6, the metal layer 123 is removed using the method for chemical mechanical grinding, is situated between until exposing the interlayer
Matter layer 110.
With reference to Fig. 7, part workfunction layers 122 and the part metal layer of 130 side walls of the opening are removed
123, it is formed recessed.
With reference to Fig. 8, SiN cap layer is formed in the interlayer dielectric layer 110 and the recessed bottom and its side wall
104, described full described recessed and its height of the filling of SiN cap layer 104 is higher than the top of the interlayer dielectric layer 110.
With reference to Fig. 9, planarization process is carried out to the SiN cap layer 104 using mechanical lapping.
As shown in fig. 6, on interlayer dielectric layer metal layer and workfunction layers be removed processing when, using chemistry
The method of grinding, milled processed is up to exposing interlayer dielectric layer, in this way, the scraping of interlayer dielectric layer is be easy to cause to be recessed, from
And lead to the inconsistent and defect of gate height.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, comprising: provide lining
Bottom, the substrate surface have fin；There is interlayer dielectric layer, the height of the interlayer dielectric layer is higher than described on the substrate
Fin top surface；The part of the surface exposure of the fin is simultaneously formed with opening in the interlayer dielectric layer；The opening
Bottom and side wall surface has gate dielectric layer；In gate dielectric layer chemical mechanical grinding stop-layer formed above；It is ground in chemical machinery
Stop-layer metal layer formed above is ground, is higher than the interlayer at the top of the full opening of the metal layer filling and the metal layer and is situated between
At the top of matter layer.
The forming method of fin formula field effect transistor of the invention, by forming chemical mechanical grinding before metal layer
Stop-layer is handled so as to which the removal technique of metal layer is divided into two parts technique, avoids in the prior art only useization
The scraping recess for learning the caused interlayer dielectric layer of mechanical lapping processing leads to the inconsistent and defect of gate height.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Figure 10 to Figure 15 is each step counter structure in one embodiment of forming method of fin formula field effect transistor of the present invention
Schematic diagram.
With reference to Figure 10 and Figure 11, substrate 200 is provided, 200 surface of substrate has fin 201；Have on the substrate 200
There is interlayer dielectric layer 210, the height of the interlayer dielectric layer 210 is higher than 201 top surface of fin；The fin 201
Part of the surface exposure is simultaneously formed with opening 230 in the interlayer dielectric layer 210；The bottom and side wall of the opening 230, and
More than the interlayer dielectric layer there is gate dielectric layer 221；In gate dielectric layer chemical mechanical grinding stop-layer 223 formed above；?
The metal layer 224 formed above of chemical mechanical grinding stop-layer 223, the full opening 230 of the metal layer filling and the metal
224 top of layer is higher than 210 top of interlayer dielectric layer；Wherein, the chemical mechanical grinding stop-layer 223 is different from the gold
Belong to layer 224.
In the present embodiment, the quantity of the fin 201 is greater than or equal to 1.
In the present embodiment, the interlayer dielectric layer 210 is two layers, in other embodiments the interlayer dielectric layer 210
It can be one layer, or three layers or three layers or more.
210 material of interlayer dielectric layer includes but is not limited to silica, silicon oxynitride or silicon hydroxide, in the present embodiment
For silica.
The method for forming the interlayer dielectric layer 210 is depositing operation, as atom layer deposition process, low pressure chemical phase are heavy
Product technique or plasma enhanced chemical vapor deposition technique.In the present embodiment, the interlayer dielectric layer 210, wherein close
One layer of substrate is formed using atom layer deposition process, and another layer of using plasma enhancing chemical vapor deposition process is formed.
The substrate 200 can be silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, insulation
Germanium (GOI) substrate, glass substrate or III-V compound substrate (such as silicon nitride or GaAs etc.) etc. on body.This implementation
In example, the substrate 200 is silicon substrate.
The material of the fin 201 includes silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium.In the present embodiment, institute
The material for stating fin 201 is silicon.
In the present embodiment, the forming step of the substrate 200 and fin 201 includes: offer semiconductor base；Etching institute
Semiconductor base is stated, forms several grooves in the semiconductor base, the semiconductor base between adjacent trenches forms fin
201, substrate 200 is formed positioned at the semiconductor base of fin 201 and channel bottom.
In the present embodiment, the gate dielectric layer 221 includes high-k gate dielectric layer (not indicating) and is situated between positioned at the high k grid
The cap layer one (not indicating) of matter layer surface.It is applied in example in others, according to actual needs, the gate dielectric layer can also include
Other dielectric layers, such as before forming the high-k gate dielectric layer, grid oxide layer is formed in the bottom surface of the opening 230,
The high-k gate dielectric layer is formed in the grid oxygen layer surface；The material of the grid oxide layer is silica, the formation of the grid oxide layer
Technique can be thermal oxidation technology or wet process oxidation technology；The grid oxide layer for improve the high-k gate dielectric and substrate 200 it
Between bond strength.
The material of the high-k gate dielectric layer is the gate medium material that relative dielectric constant is greater than silica relative dielectric constant
Material.In the present embodiment, the material of the high-k gate dielectric layer is HfO2.In other embodiments, the material of the high-k gate dielectric layer
Material can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2Or Al2O3.Chemical vapor deposition, physics can be used
Vapor deposition or atom layer deposition process form the high-k gate dielectric layer.In the present embodiment, formed using atom layer deposition process
The high-k gate dielectric layer.
The cap layer one can play the role of the protection high-k gate dielectric layer, prevent subsequent etching technics to institute
Stating high-k gate dielectric layer causes unnecessary etching to lose, and the cap layer, which also helps, to be stopped in subsequent formed gate electrode layer
Easy diffused metal ions spread into the high-k gate dielectric layer.
In the present embodiment, the material of the cap layer one is TiN, forms the cap layer using atom layer deposition process,
Make the cap layer one that there is good step coverage.
The material of the metal layer 224 is Al, Cu, Ag, Au, Pt, Ni, Ti or W etc..In the present embodiment, the metal layer
Material be W.
In the present embodiment, before the chemical mechanical grinding stop-layer 223 is formed, work function gold is formed on gate dielectric layer
Belong to layer 222.
The workfunction layers 222 are p-type workfunction layers or N-type workfunction layers, described in the present embodiment
When transistor is p-type fin formula field effect transistor, the workfunction layers are p-type workfunction layers, and the transistor is N
When type fin formula field effect transistor, the workfunction layers are N-type workfunction layers.
The p-type workfunction layers workfunction range is 5.1ev to 5.5ev, for example, 5.2ev, 5.3ev or 5.4ev.
The p-type workfunction layers be single layer structure or laminated construction, the material of the p-type workfunction layers include Ta, TiN,
One or more of TaN, TaSiN and TiSiN.In the present embodiment, the material of the p-type workfunction layers is TiN.
The N-type workfunction layers workfunction range is 3.9ev to 4.5ev, for example, 4ev, 4.1ev or 4.3ev.Institute
State N-type workfunction layers be single layer structure or laminated construction, the material of the N-type workfunction layers include TiAl,
One or more of TaAlN, TiAlN, MoN, TaCN and AlN.In the present embodiment, the material of the N-type workfunction layers
For TiAl.
The workfunction layers can be formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process
222.In the present embodiment, the workfunction layers 222 are formed using atom layer deposition process.
The chemical mechanical grinding stop-layer 223 is different from the material of the metal layer 224, so as to metal layer
224 progress chemical mechanical grindings play barrier and fail.In the present embodiment, the material of the chemical mechanical grinding stop-layer 223
For cobalt, aluminium or copper.In other embodiments, the chemical mechanical grinding stop-layer is also possible to the workfunction layers
222, but in view of the thickness of the workfunction layers 222 is usually in 15-100A, thickness there may come a time when to chemistry than relatively thin
Mechanical lapping cannot play effective barrier action, so, the chemical mechanical grinding stop-layer 223 is preferably different from described
Workfunction layers 222.
The thickness of the chemical mechanical grinding stop-layer 223 is preferably 20-300A, and thickness is too thin cannot to play effective resistance
Every failing, thickness is too thick to be unfavorable for subsequent removal.
The chemical mechanical grinding can be formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process
Stop-layer 223.In the present embodiment, the chemical mechanical grinding stop-layer 223 is formed using atom layer deposition process.
In the present embodiment, the opening 230 is formed after removing pseudo- gate electrode layer by the pseudo- grid structure comprising pseudo- gate electrode.Institute
Stating pseudo- gate electrode layer material is polysilicon.
The forming step of the dummy gate structure includes: to form pseudo- gate oxidation films and position in the semiconductor substrate surface
Pseudo- gate electrode film in the pseudo- gate oxidation films surface, the puppet gate oxidation films cover the fin 201；To the pseudo- gate electrode
Film carries out planarization process；Patterned hard mask layer is formed on the pseudo- gate electrode film surface, the position of the hard mask layer,
Shape and size are identical as the position for the pseudo- gate electrode layer being subsequently formed, shape and size；Using the hard mask layer as exposure mask, carve
The pseudo- gate electrode film and pseudo- gate oxidation films are lost, pseudo- grid structure is formed.
In the present embodiment, the technique for removing pseudo- gate electrode layer is dry etch process；The dry etch process be it is each to
Anisotropic etching technics or isotropic etching technics.In other embodiments, the technique for removing pseudo- gate electrode layer can also
For wet-etching technology.
In the present embodiment, the gate structure further includes the side wall positioned at sidewall surfaces, the spacer material be silica,
One of silicon nitride, silicon oxynitride or multiple combinations.The side wall can be single layer structure or laminated construction.
In the present embodiment, source-drain area, the formation of the source-drain area are formed in the substrate of the dummy gate structure two sides
Step includes: to form groove in the substrate of the dummy gate structure two sides；It is formed and is answered in the groove using epitaxy technique
Power layer；Doped ions are in the stressor layers to form source-drain area.It is p-type fin formula field effect transistor when being formed by transistor
When, the material of the stressor layers is SiGe, the doped p-type ion in source-drain area.It is imitated when being formed by transistor for N-type fin field
When answering transistor, the material of the stressor layers is silicon carbide, the doped N-type ion in source-drain area, the technique of the Doped ions
For ion implantation technology or doping process in situ.
It is carried out by the way that the removal technique of metal layer is divided into two techniques using the chemical mechanical grinding stop-layer 223
Processing, it is preferred, the metal layer 224 is removed using chemical mechanical milling tech, is stopped until exposing the chemical mechanical grinding
Only layer 223；Then, using dry etch process etching processing until exposing gate dielectric layer 221.It is first such as Figure 12 in the present embodiment
First, the metal layer 224 is removed using chemical mechanical milling tech, until the chemical mechanical grinding stop-layer 223 is exposed,
Then, as Figure 13 using dry etch process etching removal chemical mechanical grinding stop-layer 223 and workfunction layers 222 until
Expose gate dielectric layer 221.
In the present embodiment, removal chemical mechanical grinding stop-layer 223 and workfunction metal are etched using dry etch process
Layer 222 is until while exposing gate dielectric layer 221, such as Figure 14 removes the partial metal layers and work function gold in the opening 230
Category layer forms recessed.Then, such as Figure 15, cap layer 2 225 is formed, the filling of cap layer 2 225 is full described recessed and described
2 225 top of cap layer is higher than 221 top of interlayer dielectric layer, then using chemical mechanical milling tech to the cap layer
2 225 are planarized.In other embodiments, the opening 230 can also not formed recessed, that is, do not open described
Partial metal layers and workfunction layers in mouth 230 are removed, directly formation cap layer 2 225, then using chemical machine
Tool grinding technics planarizes the cap layer 2 225.
In the present embodiment, the material of the cap layer 2 225 is TiN, forms the nut cap using atom layer deposition process
Layer makes the cap layer 2 225 have good step coverage.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of fin formula field effect transistor characterized by comprising
Substrate is provided, the substrate surface has fin；
There is interlayer dielectric layer, the height of the interlayer dielectric layer is higher than the fin top surface on the substrate；
The part of the surface exposure of the fin is simultaneously formed with opening in the interlayer dielectric layer；
The bottom and side wall surface of the opening has gate dielectric layer；
In gate dielectric layer chemical mechanical grinding stop-layer formed above；
In the chemical mechanical grinding stop-layer metal layer formed above, the full opening of the metal layer filling and the metal
Layer top is higher than at the top of the interlayer dielectric layer.
2. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that ground using chemical machinery
Grinding process removes the metal layer, until exposing the chemical mechanical grinding stop-layer；Then, it is carved using dry etch process
Erosion processing is until expose gate dielectric layer.
3. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the chemical machinery is ground
Before grinding stop-layer formation, workfunction layers are formed on gate dielectric layer.
4. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the chemical machinery is ground
The material for grinding stop-layer is cobalt, aluminium or copper.
5. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the chemical machinery is ground
Grind stop-layer with a thickness of 20-300A.
6. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that the workfunction metal
Layer with a thickness of 15-100A.
7. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that form the chemical machine
The technique of tool polish stop layer is atom layer deposition process.
8. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the metal layer is tungsten
Metal layer.
9. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the gate dielectric layer packet
Include high-K gate dielectric layer and cap layer one.
10. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the opening is by wrapping
Pseudo- grid structure containing pseudo- gate electrode layer is formed after removing pseudo- gate electrode layer.
11. the forming method of fin formula field effect transistor according to claim 10, which is characterized in that the puppet gate electrode
Layer material is polysilicon.
12. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that the transistor is P
Type fin formula field effect transistor, the workfunction layers are p-type workfunction layers.
13. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that the transistor is N
Type fin formula field effect transistor, the workfunction layers are N-type workfunction layers.
14. the forming method of fin formula field effect transistor according to claim 2, which is characterized in that dry etch process
After etching processing, cap layer two is formed, planarizes cap layer two.
15. the forming method of the fin formula field effect transistor according to claim 9 or 14, the cap layer one or cap layer
Two be silicon nitride layer.
16. the forming method of fin formula field effect transistor according to claim 14, which is characterized in that the flat chemical industry
Skill is chemical mechanical milling tech.
17. the forming method of fin formula field effect transistor according to claim 14, which is characterized in that dry etch process
While etching processing, remove partial metal layers and workfunction layers in the opening formed it is recessed.
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| CN102468238A (en) * | 2010-11-04 | 2012-05-23 | 联华电子股份有限公司 | Semiconductor element with metal gate, and manufacturing method for semiconductor element |
| CN102842491A (en) * | 2011-06-24 | 2012-12-26 | 联华电子股份有限公司 | Production method of metal grid electrode |
| US9349833B1 (en) * | 2014-12-26 | 2016-05-24 | United Microelectronics Corp. | Semiconductor device and method of forming the same |
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| CN1596460A (en) * | 2001-11-30 | 2005-03-16 | 自由度半导体公司 | Transistor metal gate structure and method of fabrication to minimize non-planarity effects |
| CN102468238A (en) * | 2010-11-04 | 2012-05-23 | 联华电子股份有限公司 | Semiconductor element with metal gate, and manufacturing method for semiconductor element |
| CN102842491A (en) * | 2011-06-24 | 2012-12-26 | 联华电子股份有限公司 | Production method of metal grid electrode |
| US9349833B1 (en) * | 2014-12-26 | 2016-05-24 | United Microelectronics Corp. | Semiconductor device and method of forming the same |
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