CN109300905A - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN109300905A CN109300905A CN201811168328.9A CN201811168328A CN109300905A CN 109300905 A CN109300905 A CN 109300905A CN 201811168328 A CN201811168328 A CN 201811168328A CN 109300905 A CN109300905 A CN 109300905A
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- pad
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- semiconductor devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
A kind of forming method of semiconductor devices, comprising: provide initial device, the initial device includes pad, and the pad is located at the surface of the initial device, and the pad includes pad ontology and the pad protective layer positioned at pad bodies top；Passivating structure layer is formed in initial device on the pad and around pad；At least partly passivating structure layer on etching removal pad, to form groove in the passivating structure layer；After forming groove, intermediate heat-treatment is carried out；After carrying out intermediate heat-treatment, photosensitive protective layer is formed on the passivating structure layer, the photosensitive protective layer exposes the bottom surface of groove；It is performed etching using the photosensitive protective layer as exposure mask, the pad protective layer removal of the bottom portion of groove is exposed to the surface of pad ontology.The method improves the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of semiconductor devices.
Background technique
Flash memory (Flash Memory) is also known as flash memory, and flash memory is mainly characterized by energy in the case where not powered
The long-term information for keeping storage, and have many advantages, such as that integrated level is high, access speed is fast, be easy to wipe and rewrite, therefore become non-
The mainstream memory of volatile storage.According to the difference of structure, flash memory be divided into NOT gate flash memory (NOR Flash Memory) and
NAND gate flash memory (NAND Flash Memory).Can be provided compared to NOR Flash Memory, NAND Flash Memory and
High cell density, can achieve high storage density, and be written and the speed of erasing also faster.
With the development of plane flash memory, the production technology of semiconductor achieves huge progress.But current plane
The development of flash memory encounters various challenges: physics limit, such as the exposure technique limit, the developing technique limit and storage electron density pole
Limit etc..In this context, to solve the difficulty that encounters of plane flash memory and pursue being produced into for lower unit storage unit
This, three-dimensional (3D) flash memory is applied and is given birth to, such as 3D-NAND flash memory.
Existing 3D-NAND flash memory surface needs to form a protective layer.
However, the technique based on existing protective layer, the performance for the semiconductor devices that 3D-NAND flash memory is constituted needs to be mentioned
It is high.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor devices, to improve the property of semiconductor devices
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: initial device is provided,
The initial device includes pad, and the pad is located at the surface of the initial device, and the pad includes pad ontology and position
In the pad protective layer of pad bodies top；Passivating structure is formed in initial device on the pad and around pad
Layer；At least partly passivating structure layer on etching removal pad, to form groove in the passivating structure layer；Form groove
Afterwards, intermediate heat-treatment is carried out；After carrying out intermediate heat-treatment, photosensitive protective layer is formed on the passivating structure layer, it is described photosensitive
Protective layer exposes the bottom surface of groove；It is performed etching using the photosensitive protective layer as exposure mask, by the bottom portion of groove
The removal of pad protective layer is to expose the surface of pad ontology.
Optionally, the method for at least partly passivating structure layer on etching removal pad includes: in the passivating structure layer
It is upper to form patterned photoresist layer, there is opening, the opening is located above the pad in the photoresist layer；With described
Photoresist layer is the passivating structure layer of at least partly thickness of mask etching open bottom, forms the groove；With the photoetching
After passivating structure layer of the glue-line for at least partly thickness of mask etching open bottom, the photoresist layer is removed.
Optionally, etching removes the surface layer of passivating structure layer on pad, to form groove in the passivating structure layer；Institute
State the forming method of semiconductor devices further include: using the photosensitive protective layer as the pad protective layer of mask etching bottom portion of groove
Before, using the photosensitive protective layer as the passivating structure layer of mask etching bottom portion of groove until exposing pad protective layer.
Optionally, before using the photosensitive protective layer as the pad protective layer of mask etching bottom portion of groove, the bottom of groove
The passivating structure layer in portion with a thickness of 200 angstroms~500 angstroms.
Optionally, the passivating structure layer on etching removal pad, forms groove, the bottom of groove in the passivating structure layer
Portion exposes pad protective layer.
Optionally, the intermediate heat-treatment includes annealing.
Optionally, after forming the groove, and before carrying out the intermediate heat-treatment, further includes: to the groove
Carry out cleaning process.
Optionally, the material of the photosensitive protective layer includes polyimide material.
Optionally, the method for forming the photosensitive protective layer include: on the passivating structure layer of the groove vicinity and
Initial photosensitive protective layer is formed in groove；The initial photosensitive protective layer is successively exposed, developed and solidified, makes initially to feel
Light protection layer forms the photosensitive protective layer.
Optionally, the photosensitive protective layer is also located at the side wall of groove, so that the opening bore of the photosensitive protective layer is small
In the bore of the groove.
Optionally, the method for forming the passivating structure layer includes: the tickler on the pad and around pad
The first passivation layer is formed on part；The second passivation layer is formed on the first passivation layer；At least partly passivation on etching removal pad
The method of structure sheaf includes: the first passivation of at least partly thickness on the second passivation layer and pad on etching removal pad
Layer.
Optionally, the material of first passivation layer includes silica；The material of second passivation layer includes silicon nitride.
Optionally, further includes: performed etching using the photosensitive protective layer as exposure mask, the pad of the bottom portion of groove is protected
After sheath removal, curing process is carried out to the photosensitive protective layer.
Optionally, the material of the pad ontology includes aluminium；The material of the pad protective layer includes titanium nitride.
Optionally, further includes: after forming the passivating structure layer, and it is at least partly blunt on etching removal pad
Before changing structure sheaf, initially it is heat-treated.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor devices that technical solution of the present invention provides, the passivating structure layer on pad ontology is removed
With pad protective layer, the surface of pad ontology is exposed, the surface of pad ontology is suitable for connecting with bond wire line.The centre
Heat treatment is required processing step during forming other structures on to initial device or in initial device.It is gone in etching
During except at least partly passivating structure layer on pad, not using photosensitive protective layer as exposure mask.The photosensitive protective layer
The exposure mask of pad protective layer as mask etching bottom portion of groove.After the photosensitive protective layer is used as exposure mask, it will not be gone
It removes, the photosensitive protective layer, which can be used as protective layer, can reduce influence of the environment to semiconductor devices, and the photosensitive protective layer is also
Buffer function can be played, stress is reduced.After photosensitive protective layer heat treatment formed between, photosensitive protection
The high temperature that layer not will receive intermediate heat-treatment influences, and photosensitive protective layer is improved the protective effect of semiconductor devices.To sum up,
Improve the performance of semiconductor devices.
Secondly, the pad protective layer can protect pad ontology during forming photosensitive protective layer.
Further, after forming the groove, and before carrying out the intermediate heat-treatment, further includes: to the groove
Carry out cleaning process.During carrying out cleaning process, the pad protective layer can protect pad ontology not to be washed
The damage of solution.
Further, etching removes the surface layer of passivating structure layer on pad, to form groove in the passivating structure layer.?
Before using the photosensitive protective layer as the pad protective layer of mask etching bottom portion of groove, the effect of the passivating structure layer of bottom portion of groove
Include: the passivating structure layer of bottom portion of groove and pad protective layer protects pad ontology together, enhances the protection to pad ontology and make
With the probability of the technique etching injury pad ontology of the passivating structure layer on reduction etching pad.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor devices forming process；
Fig. 4 to Figure 14 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention；
Figure 15 to Figure 21 is the structural schematic diagram of semiconductor devices forming process in another embodiment of the present invention.
Specific embodiment
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor devices forming process.
With reference to Fig. 1, initial device is provided, the initial device includes pad 100, and the pad 100 is located at described initial
The surface of device, the pad 100 include pad ontology 101 and the pad protective layer 102 positioned at 101 top of pad ontology；?
Passivating structure layer 110 is formed in initial device on the pad 100 and around pad 100.
With reference to Fig. 2, patterned photosensitive protective layer 120, the photosensitive protective layer 120 are formed on passivating structure layer 110
In have opening 121, it is described opening 121 be located at pad 100 on.
The material of the photosensitive protective layer 120 is polyimide material.
It is exposure mask, the passivating structure layer 110 of 121 bottom of etching opening and weldering with the photosensitive protective layer 120 with reference to Fig. 3
Disc protective layer 102 is until expose the surface of pad ontology 101.
Specifically, being exposure mask, the passivating structure layer 110 of 121 bottom of etching opening, blunt with the photosensitive protective layer 120
Change in structure sheaf 110 and forms groove；It later, is the pad protective layer of 121 bottoms of mask etching opening with photosensitive protective layer 120
102 until expose the surface of pad ontology 101.
The photosensitive protective layer 120 is not removed, and can be retained.The photosensitive protective layer 120 is used to be used as and partly lead
The protective layer of body device, it is possible to reduce influence of the environment to semiconductor devices, the photosensitive protective layer 120 are also used to play buffering
Effect reduces stress.
In general, being protected with the pad of 121 bottom of etching opening the passivating structure layer 110 of 121 bottom of etching opening the step of
Between the step of sheath 102, it is also necessary to carry out the processing step for being used to form other structures component, include annealing in these steps
Processing.
However, if carrying out the annealing, the high temperature of the unbearable annealing of photosensitive protective layer 120,
The annealing can make photosensitive protective layer 120 by serious damage, lead to the reduced performance of photosensitive protective layer 120.
On this basis, the present invention provides a kind of forming method of semiconductor devices, comprising: initial device is provided, it is described
Initial device includes pad, and the pad is located at the surface of the initial device, and the pad includes pad ontology and is located at weldering
The pad protective layer of disk bodies top；Passivating structure layer is formed in initial device on the pad and around pad；It carves
Etching off is except at least partly passivating structure layer on pad, to form groove in the passivating structure layer；Later, intermediate heat is carried out
Processing；Later, photosensitive protective layer is formed on passivating structure layer, the photosensitive protective layer exposes the bottom surface of groove；With
Photosensitive protective layer performs etching for exposure mask, and the pad protective layer removal of bottom portion of groove is exposed to the table of pad ontology
Face.The method improves the performance of semiconductor devices.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 14 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 4, initial device is provided, the initial device includes pad 200, and the pad 200 is located at described initial
The surface of device, the pad 200 include pad ontology 201 and the pad protective layer 202 positioned at 201 top of pad ontology.
In one embodiment, the initial device includes: semiconductor substrate；Stacking knot in semiconductor substrate
Structure, the stacked structure include the insulating layer and conductive layer of intersecting, and the top layer and bottom of the stacked structure are insulation
Layer；Through the channel structure of the stacked structure；Dielectric layer on the channel structure and stacked structure；The pad
200 are located at the surface of dielectric layer.The pad 200 can be electrically connected with channel structure.
The material of the pad ontology 201 includes aluminium, and the material of the pad protective layer 202 includes titanium nitride.
The pad protective layer 202 with a thickness of 100 angstroms~900 angstroms.
The pad protective layer 202 is suitable for protection pad ontology 201.
With reference to Fig. 5, passivating structure layer 210 is formed in the initial device on the pad 200 and around pad 200.
The method for forming the passivating structure layer 210 includes: initial on the pad 200 and around pad 200
The first passivation layer 211 is formed on device；The second passivation layer 212 is formed on the first passivation layer 211.
The material of first passivation layer 211 includes silica；The material of second passivation layer 212 includes silicon nitride.
The formation process of first passivation layer 211 is depositing operation, and the formation process of the second passivation layer 212 is depositing operation.
The effect of first passivation layer 211 includes: the first passivation layer 211 as stress-buffer layer, avoids the second passivation layer 212
It is directly contacted with initial device and biggish stress is caused to initial device.
The effect of second passivation layer 212 includes: the steam in isolation environment.
It is initially heat-treated after forming passivating structure layer 210 with reference to Fig. 6.
The initial heat treatment includes annealing process.
The initial heat treatment is required during forming other structures on to initial device or in initial device
Processing step.
Then, at least partly passivating structure layer on etching removal pad 200, forms recessed in the passivating structure layer
Slot.
The method of at least partly passivating structure layer on etching removal pad 200 includes: the on etching removal pad 200
First passivation layer 211 of at least partly thickness on two passivation layers 212 and pad 200.
In the present embodiment, to etch the passivating structure layer on removal pad 200, formed in the passivating structure layer recessed
Slot, the bottom-exposed of groove go out pad protective layer 202 and are illustrated for example.
With reference to Fig. 7, patterned photoresist layer 230, the photoresist layer 230 are formed on the passivating structure layer 210
In have opening 231, it is described opening 231 be located at the pad 200 on.
The method for forming the photoresist layer 230 includes: to coat photoresist film on the passivating structure 210；To described
Photoresist film is exposed, develops and solidifies, and photoresist film is made to form the photoresist layer 230.
It take the photoresist layer 230 as the passivating structure layer 210 of 231 bottoms of mask etching opening, in institute with reference to Fig. 8
It states formation groove 220, the bottom-exposed of groove 220 in passivating structure layer 210 and goes out pad protective layer 202.
Technique with the passivating structure layer 210 that the photoresist layer 230 is 231 bottoms of mask etching opening includes wet etching work
Skill or dry carving technology.
Specifically, be exposure mask with the photoresist layer 230, the first passivation layer 211 and second on etching removal pad 200
Passivation layer 212, to form groove 220 in the passivating structure layer 210.
With reference to Fig. 9, after the passivating structure layer 210 with the photoresist layer 230 for 231 bottoms of mask etching opening, removal
The photoresist layer 230.
The technique for removing the photoresist layer 230 includes cineration technics.
With reference to Figure 10, cleaning process is carried out to the groove 220.
The solution that cleaning process use is carried out to the groove 220 includes hydrofluoric acid solution.
During carrying out cleaning process to the groove 220, the pad protective layer 202 of 220 bottom of groove can be protected
Pad ontology 201 is protected not by etching injury.
In the present embodiment, after carrying out cleaning process to the groove 220, avoid in groove 220 that there are more residuals
Object.
In other embodiments, cleaning process can not be carried out to groove.
With reference to Figure 11, after forming groove 220, intermediate heat-treatment is carried out.
In the present embodiment, after carrying out cleaning process, intermediate heat-treatment is carried out, avoids residue in the height of intermediate heat-treatment
Other structures are had an impact under temperature；And if the residue in groove 220 pass through intermediate heat-treatment, by the residual of intermediate heat-treatment
It stays object that chemical reaction occurs and is firmly attached to 220 inner wall of groove and is difficult to remove again, therefore selects carrying out cleaning process
Afterwards, intermediate heat-treatment is carried out.
The intermediate heat-treatment is required during forming other structures on to initial device or in initial device
Processing step.The intermediate heat-treatment includes annealing.
After carrying out intermediate heat-treatment, photosensitive protective layer is formed on passivating structure layer 210, the photosensitive protective layer exposes
The bottom surface of groove 220.
It is formed with reference to Figure 12, on the passivating structure layer 210 around the groove 220 and in groove 220 initial photosensitive
Protective layer 240.
The initial photosensitive protective layer 240 is used to form photosensitive protective layer.
The material of the initial photosensitive protective layer 240 is polyimide material.
Firstly, polyimide material can be used as photoresist, secondly, polyimide material is electrical insulation material, can make
Influence of the environment to semiconductor devices can be reduced for protective layer；Again, polyimide material can play buffer function, and reduction is answered
Power.
The technique for forming initial photosensitive protective layer 240 is spin coating proceeding.
With reference to Figure 13, the initial photosensitive protective layer 240 is successively exposed, developed and solidified, makes initial photosensitive guarantor
Sheath 240 forms the photosensitive protective layer 241.
After the initial photosensitive protective layer 240 is exposed and is developed, solidified, cured temperature is 155 Celsius
~165 degrees Celsius of degree, cured effect include: solvent in the initial photosensitive protective layer 240 of volatilization.
During forming photosensitive protective layer 241, the pad protective layer 202 protects pad ontology 201, specific manifestation
: during developing initial photosensitive protective layer 240, pad protective layer 202 protects pad ontology 201 will not developer solution etching
Damage.
The photosensitive protective layer 241 is located on the passivating structure layer 210 around groove 220.
In the present embodiment, the photosensitive protective layer 241 is also located at the side wall of groove 220.
The photosensitive protective layer 241 exposes the bottom of groove 220.
With reference to Figure 14, with pad protective layer 202 that the photosensitive protective layer 241 is 220 bottom of mask etching groove until
Expose the surface of pad ontology 201.
In the present embodiment, further includes: protected with the pad that the photosensitive protective layer 241 is 220 bottom of mask etching groove
Layer 202 carries out curing process after exposing the surface of pad ontology 201, to the photosensitive protective layer 241.
The temperature for carrying out curing process to the photosensitive protective layer 241 is 200 degrees Celsius~360 degrees Celsius.
The effect that curing process is carried out to the photosensitive protective layer 241 includes: by solvent remaining in photosensitive protective layer 241
It evaporates, and stablizes the material properties of photosensitive protective layer 241.
It is subsequent also bonding connecting line to be formed on 201 surface of pad ontology using routing technique.
The photosensitive protective layer 241 is subsequent to be removed, and the photosensitive protective layer 241 retains in the semiconductor device.
The material of the photosensitive protective layer 241 includes polyimide material.
The photosensitive protective layer 241, which can be used as protective layer, can reduce influence of the environment to semiconductor devices；It is described photosensitive
Protective layer 241 may also function as buffer function, reduce stress.
Another embodiment of the present invention also provides a kind of forming method of semiconductor devices, the present embodiment and previous embodiment
Difference is: the surface layer of passivating structure layer on etching removal pad, to form groove in the passivating structure layer；With described
Before photosensitive protective layer is the pad protective layer of mask etching bottom portion of groove, using the photosensitive protective layer as mask etching groove-bottom
The passivating structure layer in portion is until expose pad protective layer.
Figure 15 to Figure 21 is the structural schematic diagram of semiconductor devices forming process in another embodiment of the present invention.
With reference to Figure 15, Figure 15 is schematic diagram on the basis of Fig. 6, is formed on the passivating structure layer 210 patterned
Photoresist layer 330, has opening 331 in the photoresist layer 330, and the opening 331 is located on the pad 200.
The method that the reference of photoresist layer 330 forms photoresist layer 230 is formed, is no longer described in detail.
It is the surface layer of the passivating structure layer 210 of 331 bottoms of mask etching opening with the photoresist layer 330 with reference to Figure 16,
To form groove 320 in the passivating structure layer 210.
Specifically, being exposure mask, the second passivation layer 212 and opening of 331 bottom of etching opening with the photoresist layer 330
First passivation layer 211 of the segment thickness of 331 bottoms.
The bottom-exposed of groove 320 goes out the material of passivating structure layer 210, the work of the passivating structure layer 210 of 320 bottom of groove
Pad ontology 201 is protected together with the passivating structure layer 210 and pad protective layer 202 that include: 320 bottom of groove, enhances butt welding
The protective effect of disk ontology 201 reduces the technique etching injury pad ontology 201 of the passivating structure layer 210 on etching pad
Probability.
It is subsequent with the photosensitive protective layer 330 be 320 bottom of mask etching groove pad protective layer 202 before, it is recessed
The passivating structure layer 210 of 320 bottom of slot with a thickness of 200 angstroms~500 angstroms.If selecting the benefit of this thickness range includes: groove
The thickness of the passivating structure layer 210 of 320 bottoms is excessive, then subsequent to need to rely on photosensitive protective layer 330 also for mask etching removal
The thicker passivating structure layer 210 in 320 bottom of groove, can consume more photosensitive protective layer 330 in this way, and photosensitive protective layer 330 is right
The protective effect of semiconductor devices reduces；If if the thinner thickness of the passivating structure layer 210 of 320 bottom of groove, enhancing butt welding
The degree of the protective effect of disk ontology 201 is smaller.
With reference to Figure 17, the photoresist layer 330 is removed.
With reference to Figure 18, after removing the photoresist layer 330, cleaning process is carried out to the groove 320.
During carrying out cleaning process to the groove 320, the pad protective layer 202 of 320 bottom of groove and passivation
Structural material can protect jointly pad ontology 201 not by etching injury.
With reference to Figure 19, after forming groove 320, intermediate heat-treatment is carried out.
Specifically, carrying out intermediate heat-treatment after carrying out cleaning process.
The intermediate heat-treatment is required during forming other structures on to initial device or in initial device
Processing step.The intermediate heat-treatment includes annealing.
With reference to Figure 20, after carrying out intermediate heat-treatment, photosensitive protective layer 341 is formed on passivating structure layer 210, it is described photosensitive
Protective layer 341 exposes the bottom surface of groove 320.
Specifically, forming initial photosensitive guarantor on the passivating structure layer 210 around the groove 220 and in groove 220
Sheath；The initial photosensitive protective layer is successively exposed, developed and solidified, forms initial photosensitive protective layer described photosensitive
Protective layer 341.
The photosensitive protective layer 341 is located on the passivating structure layer 210 around groove 320, and the photosensitive protective layer 341 is also
Positioned at the side wall of groove 320, so that the opening bore of the photosensitive protective layer 341 is less than the bore of the groove 320.
With reference to Figure 21, with passivating structure layer 210 that the photosensitive protective layer 341 is 320 bottom of mask etching groove until
Expose pad protective layer 202；Later, it is protected with the pad that the photosensitive protective layer 341 is 320 bottom of mask etching groove
Layer 202 is until expose the surface of pad ontology 201.
In the present embodiment, further includes: protected with the pad that the photosensitive protective layer 341 is 320 bottom of mask etching groove
Layer 202 carries out curing process after exposing the surface of pad ontology 201, to the photosensitive protective layer 341.
The effect that curing process is carried out to the photosensitive protective layer 341 includes: by solvent remaining in photosensitive protective layer 341
It evaporates, and stablizes the material properties of photosensitive protective layer 341.
It is subsequent also bonding connecting line to be formed on 201 surface of pad ontology using routing technique.
The photosensitive protective layer 341 is subsequent to be removed, and the photosensitive protective layer 341 retains in the semiconductor device.
The material of the photosensitive protective layer 341 includes polyimide material.
The photosensitive protective layer 341, which can be used as protective layer, can reduce influence of the environment to semiconductor devices；It is described photosensitive
Protective layer 341 may also function as buffer function, reduce stress.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of forming method of semiconductor devices characterized by comprising
Initial device is provided, the initial device includes pad, and the pad is located at the surface of the initial device, the pad
Including pad ontology and positioned at the pad protective layer of pad bodies top；
Passivating structure layer is formed in initial device on the pad and around pad；
At least partly passivating structure layer on etching removal pad, to form groove in the passivating structure layer；
After forming groove, intermediate heat-treatment is carried out；
After carrying out intermediate heat-treatment, photosensitive protective layer is formed on the passivating structure layer, the photosensitive protective layer exposes recessed
The bottom surface of slot；
It is performed etching using the photosensitive protective layer as exposure mask, by the pad protective layer removal of the bottom portion of groove to expose
The surface of pad ontology.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that on etching removal pad at least
The method of partial deactivation structure sheaf includes:
Patterned photoresist layer is formed on the passivating structure layer, and there is opening, the opening position in the photoresist layer
Above the pad；
Using the photoresist layer as the passivating structure layer of at least partly thickness of mask etching open bottom, the groove is formed；
After using the photoresist layer as the passivating structure layer of at least partly thickness of mask etching open bottom, the photoetching is removed
Glue-line.
3. the forming method of semiconductor devices according to claim 1, which is characterized in that be passivated knot on etching removal pad
The surface layer of structure layer, to form groove in the passivating structure layer；
The forming method of the semiconductor devices further include: using the photosensitive protective layer as the pad of mask etching bottom portion of groove
Before protective layer, using the photosensitive protective layer as the passivating structure layer of mask etching bottom portion of groove until exposing pad protection
Layer.
4. the forming method of semiconductor devices according to claim 3, which is characterized in that be with the photosensitive protective layer
Before the pad protective layer of mask etching bottom portion of groove, the passivating structure layer of the bottom of groove with a thickness of 200 angstroms~500 angstroms.
5. the forming method of semiconductor devices according to claim 1, which is characterized in that the passivation on etching removal pad
Structure sheaf, forms groove in the passivating structure layer, and the bottom-exposed of groove goes out pad protective layer.
6. the forming method of semiconductor devices according to claim 1, which is characterized in that the intermediate heat-treatment includes moving back
Fire processing.
7. the forming method of semiconductor devices according to claim 1, which is characterized in that after forming the groove, and
Before carrying out the intermediate heat-treatment, further includes: carry out cleaning process to the groove.
8. the forming method of semiconductor devices according to claim 1, which is characterized in that the material of the photosensitive protective layer
Including polyimide material.
9. the forming method of semiconductor devices according to claim 1, which is characterized in that form the photosensitive protective layer
Method includes: to form initial photosensitive protective layer on the passivating structure layer of the groove vicinity and in groove；To described initial
Photosensitive protective layer is successively exposed, develops and solidifies, and initial photosensitive protective layer is made to form the photosensitive protective layer.
10. the forming method of semiconductor devices according to claim 1, which is characterized in that the photosensitive protective layer also position
In the side wall of groove, so that the opening bore of the photosensitive protective layer is less than the bore of the groove.
11. the forming method of semiconductor devices according to claim 1, which is characterized in that form the passivating structure layer
Method include: to form the first passivation layer in initial device on the pad and around pad；On the first passivation layer
Form the second passivation layer；
Etching removal pad at least partly passivating structure layer method include: etching removal pad on the second passivation layer with
And the first passivation layer of at least partly thickness on pad.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that the material of first passivation layer
Material includes silica；The material of second passivation layer includes silicon nitride.
13. the forming method of semiconductor devices according to claim 1, which is characterized in that further include: with the photosensitive guarantor
Sheath performs etching for exposure mask, after the pad protective layer of the bottom portion of groove is removed, consolidates to the photosensitive protective layer
Change processing.
14. the forming method of semiconductor devices according to claim 1, which is characterized in that the material of the pad ontology
Including aluminium；The material of the pad protective layer includes titanium nitride.
15. the forming method of semiconductor devices according to claim 1, which is characterized in that further include: it is described blunt being formed
After changing structure sheaf, and before at least partly passivating structure layer on etching removal pad, initially it is heat-treated.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112447679A (en) * | 2019-08-30 | 2021-03-05 | 珠海格力电器股份有限公司 | Power semiconductor device and manufacturing method thereof |
| CN112820657A (en) * | 2021-01-05 | 2021-05-18 | 苏州工业园区纳米产业技术研究院有限公司 | Method for solving abnormal routing of aluminum pad |
| CN116706684A (en) * | 2023-07-11 | 2023-09-05 | 苏州镓锐芯光科技有限公司 | Preparation method of semiconductor laser |
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| CN112820657A (en) * | 2021-01-05 | 2021-05-18 | 苏州工业园区纳米产业技术研究院有限公司 | Method for solving abnormal routing of aluminum pad |
| CN116706684A (en) * | 2023-07-11 | 2023-09-05 | 苏州镓锐芯光科技有限公司 | Preparation method of semiconductor laser |
| CN116706684B (en) * | 2023-07-11 | 2024-03-01 | 苏州镓锐芯光科技有限公司 | Preparation method of semiconductor laser |
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