CN109427736A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109427736A CN109427736A CN201710772683.6A CN201710772683A CN109427736A CN 109427736 A CN109427736 A CN 109427736A CN 201710772683 A CN201710772683 A CN 201710772683A CN 109427736 A CN109427736 A CN 109427736A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
A kind of semiconductor structure and forming method thereof, wherein the forming method includes: offer substrate, and the substrate includes fuse region；Dielectric structure is formed over the substrate, and there is fuse connection structure in the fuse region dielectric structure；Fuse metal layer is formed on the fuse connection structure surface；Stop-layer is formed on the fuse metal layer；Initial protective layers are formed on the stop-layer；The part initial protective layers are performed etching, protective layer is formed, the protective layer exposes the stop-layer on the fuse metal layer, and in the etching process, the etch rate of the initial protective layers is greater than the etch rate of the stop-layer.The stop-layer is not easy the removal that is etched, so as to prevent the fuse metal layer to be exposed.Therefore, the forming method can reduce the damage of the fuse metal layer, and then can improve the performance of formed semiconductor structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With the development of fuse (fuse) technology, the application of fuse is also more and more extensive, has been not limited only to for depositing
Storage unit is repaired, and programmable array can also be used as.
Mainly provide sufficiently large electric current by several transistors arranged side by side makes fuse failure to the cellular construction of fuse, or
Information is stored whether making fuse failure by laser irradiation, and be blown by fuse.Fuse resistance very little before fusing,
Resistance exponentially increases again after the lower fusing of lasting high current effect, and the state of fuse failure will be kept forever.Therefore, one
Root electric fuse can correspond to " 0 " and " 1 " in binary system.
In semiconductor processing, fuse generally requires to be formed simultaneously same label on piece with other logical devices, this will
The formation process of fuse is asked to need compatible with the formation process of other logical devices.
However, the reliability that the prior art forms fuse is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can be improved formed fuse
Reliability.
To solve the above problems, technical solution of the present invention provides a kind of forming method of semiconductor structure, comprising: provide lining
Bottom, the substrate include fuse region；Dielectric structure is formed over the substrate, in the fuse region dielectric structure there is fuse to connect
Binding structure；Fuse metal layer is formed on the fuse connection structure surface；Stop-layer is formed on the fuse metal layer；Institute
It states and forms initial protective layers on stop-layer；The part initial protective layers are performed etching, protective layer is formed, the protective layer is sudden and violent
Expose the stop-layer on the fuse metal layer.
Optionally, the substrate includes center and the external zones for surrounding the center, the center of the center with
The center of the substrate is overlapped；The center includes one or more fuse regions, and the external zones includes one or more
A fuse region.
Optionally, the substrate further includes logic area；The forming method further include: in the logic area dielectric structure
Form logical connection structure；Top layer metallic layer is formed on the logical connection structure surface；The initial protective layers are also located at institute
It states on top layer metallic layer；The protective layer also exposes the top layer metallic layer.
Optionally, the substrate includes center and the external zones for surrounding the center, the center of the center with
The center of the substrate is overlapped；The center includes one or more logic areas, and the external zones includes one or more
A logic area.
Optionally, fuse region dielectric structure surface is lower than logic area dielectric structure surface；The initial protection
Layer includes: the coating on the fuse region stop-layer；Positioned at the coating, logic area dielectric structure and top-level metallic
Passivation layer on layer.
Optionally, the material of the coating is silica, and the material of the passivation layer is silica.
Optionally, the dielectric structure includes: the underlying dielectric structure on the logic area and fuse region substrate；Position
Top layer dielectric structure in the logic area underlying dielectric structure；The logical connection structure includes: positioned at the logic area
Lower level logical connection structure in underlying dielectric structure；Interlayer connecting line positioned at Lower level logical connection structure surface；Position
Top layer plug in the top layer dielectric structure, the top layer plug connect the interlayer connecting line and the top-level metallic
Layer；The step of forming the dielectric structure, logical connection structure, fuse connection structure, interlayer connecting line and stop-layer include:
Underlying dielectric structure is formed on the logic area and fuse region substrate, and there is Lower level logical in the logic area underlying dielectric structure
Connection structure has fuse connection structure in the fuse region underlying dielectric structure；On Lower level logical connection structure surface
Form interlayer connecting line；Fuse metal layer is formed on the fuse connection structure surface；It is connected in the fuse metal layer, interlayer
Stop-layer is formed in line and the underlying dielectric structure；It is formed after stop-layer, forms top layer on the logic area stop-layer
Dielectric structure.
Optionally, the initial protective layers include: the coating on the fuse region stop-layer；Positioned at the covering
Passivation layer on layer, logic area dielectric structure and top layer metallic layer；Form the initial protective layers, top layer plug, top-level metallic
The step of layer and the top layer dielectric structure includes: the formation top layer dielectric structure on the logic area stop-layer, and described
Coating is formed on the stop-layer of fuse region；Top layer plug is formed in the top layer dielectric structure；In the top layer plug surface
Form top layer metallic layer；Passivation layer is formed on the top layer metallic layer, top layer dielectric structure and the coating.
Optionally, the material of the fuse metal layer is identical as the material of the interlayer connecting line.
Optionally, during being performed etching to the initial protective layers, the etch rate of the protective layer with it is described
The ratio of the etch rate of stop-layer is greater than 5.
Optionally, the material of the initial protective layers includes silica, and the material of the stop-layer is silicon nitride or nitrogen oxygen
SiClx；The technique for forming the stop-layer includes chemical vapor deposition process, physical gas-phase deposition or atomic layer deposition work
Skill.
Optionally, the step of forming protective layer includes: that patterned photoresist is formed on the initial protective layers, described
Photoresist exposes the initial protective layers on the fuse metal layer；Using the photoresist as exposure mask to the initial protective layers into
Row is etched to the stop-layer exposed on the fuse metal layer；The initial protective layers are carried out using the photoresist as exposure mask
After etching, the photoresist is removed.
Optionally, the technique for removing the photoresist includes cineration technics, and the reactant of the cineration technics includes CF4。
Optionally, after removing the photoresist, further includes: remove the stop-layer of the fuse region.
Optionally, the technique performed etching to the initial protective layers includes dry etch process.
Optionally, when the technique performed etching to the initial protective layers is dry etch process, to the initial guarantor
The technological parameter that sheath performs etching includes: that etching gas includes CF4And O2；Gas flow is 1sccm~100sccm；Power is
500W~3000W.
Corresponding technical solution of the present invention also provides a kind of semiconductor structure, comprising: substrate, the substrate include fuse
Area；Dielectric structure on the substrate has fuse connection structure in the fuse region dielectric structure；Positioned at the fuse
The fuse metal layer on connection structure surface；Stop-layer on the fuse metal layer；Protection on the stop-layer
Layer, the protective layer expose the stop-layer on the fuse metal layer, the material of the protective layer and the stop-layer not phase
Together.
Optionally, the material of the protective layer includes silica, and the material of the stop-layer is silicon nitride.
Optionally, the stop-layer with a thickness of 700 angstroms~900 angstroms.
Optionally, the substrate further includes logic area, has logical connection structure in the logic area dielectric structure；It is described
Dielectric structure includes: the underlying dielectric structure on the logic area and fuse region substrate；It is situated between positioned at the logic area bottom
Top layer dielectric structure in matter structure；The logical connection structure includes: the bottom in the logic area underlying dielectric structure
Layer logical connection structure；Interlayer connecting line positioned at Lower level logical connection structure surface；Positioned at the top layer dielectric structure
In top layer plug, the top layer plug connects the interlayer connecting line and the top layer metallic layer；The stop-layer is also located at
On the interlayer connecting line and the logic area underlying dielectric structure；The protective layer includes: positioned at the fuse region stop-layer
On coating, the coating exposes the stop-layer on the fuse metal layer；Positioned at the coating, logic area medium
Passivation layer in structure and top layer metallic layer.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor structure that technical solution of the present invention provides, performed etching to the initial protective layers
During, the etch rate of the stop-layer is less than the etch rate of the initial protective layers, then the stop-layer is not easy
Be etched removal, so as to prevent the fuse metal layer to be exposed.Therefore, the forming method can reduce etching
Damage of the process to the fuse metal layer, and then the performance of formed semiconductor structure can be improved.
Further, during etching the initial protective layers, the etch rate of the initial protective layers of the center
Greater than the etch rate of the initial protective layers of the external zones.Due to having stop-layer, institute on the center fuse metal layer
The etch rate for stating stop-layer is less than the initial protective layers, and the stop-layer can reduce the process of etching external zones protective layer
In loss to center fuse metal layer, so as to improve the performance of formed semiconductor structure.
Further, after removing the photoresist, the stop-layer is removed.During removing the photoresist, institute
The fuse metal layer can be protected by stating stop-layer, reduce the loss of fuse metal layer.The stop-layer is removed, it can be in institute's shape
At in the course of work of semiconductor structure, stop-layer is avoided to have an impact semiconductor structure performance.
In semiconductor structure of the invention, there is stop-layer on the fuse metal layer.The stop-layer can prevent institute
It states fuse metal layer to be exposed, the damage of fuse metal layer can be reduced, and then formed semiconductor structure can be improved
Performance.
Further, the stop-layer with a thickness of 700 angstroms~900 angstroms, the thickness of the stop-layer is smaller.The fuse gold
Belong to layer during the work time, the stop-layer is not easy to influence effect of the light to the fuse metal layer.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of fuse equipment；
Fig. 4 to Figure 10 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
There are problems for the forming method of the semiconductor structure of the prior art, such as: it is formed by the reliability of fuse
It is poor.
Now in conjunction with the semiconductor structure of the prior art, the poor reason of the fuse reliability of prior art formation is analyzed:
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of fuse equipment.
Referring to FIG. 1, providing substrate 100, the substrate 100 includes logic area A and fuse region B；In the logic area A and
Interlayer dielectric structure 120 is formed on fuse region B substrate 100, and there is interlayer connection in the logic area A inter-level dielectric structure 120
Structure 121 has fuse connection structure 122 in the fuse region B inter-level dielectric structure 120；It is connected in the logic area A interlayer
Interlayer metal layer 112 is formed in structure 121 and inter-level dielectric structure 120；In the fuse region B inter-level dielectric structure 120 and melt
Fuse metal layer 110 is formed in silk connection structure 122；In the fuse metal layer 110, inter-level dielectric structure 120 and interlayer gold
Belong to and forms top layer dielectric layer 111 on layer 112；Top layer plug, the top layer plug connection are formed in the top layer dielectric layer 111
The interlayer metal layer；Top layer metallic layer 130 is formed on the top layer plug；In the top layer dielectric layer 111 and top layer gold
Belong to and forms passivation layer 140 on layer 130.
Referring to FIG. 2, forming patterned photoresist 150 on the passivation layer 140；With the patterned photoresist
150 perform etching the passivation layer 140 and top layer dielectric layer 111 for exposure mask, expose the top layer metallic layer 130 and fuse
Metal layer 110.
Referring to FIG. 3, removing the photoresist after performing etching to the passivation layer 140 and top layer dielectric layer 111
150 (as shown in Figure 2).
Wherein, the fuse equipment during the work time, is irradiated the fuse metal layer 110 by laser, from
And the fuse metal layer 110 is made to fuse, resistance increases, and then realizes programming.Therefore, it is carved to the passivation layer 140
During erosion, the needs of fuse metal layer 110 are exposed, to reduce top layer dielectric layer 111 to fuse metal layer
The influence of 110 programming processes.During removing photoresist 150, since the fuse metal layer 110 is exposed
Come, the technique for removing photoresist is cineration technics, and the reactant of the cineration technics includes CF4。CF4Easily corrode the fuse
Metal layer 110 is easier to be blown so as to cause the fuse metal layer 110, and then influences the programming process to fuse equipment,
Therefore the performance for being formed by fuse equipment is poor.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: described molten
Silk connection structure surface forms fuse metal layer；Stop-layer is formed on the fuse metal layer；It is formed on the stop-layer
Initial protective layers；The part initial protective layers are performed etching, protective layer is formed, the protective layer exposes the fuse gold
Belong to the stop-layer on layer in the etching process, the etch rate of the initial protective layers is greater than the etching speed of the stop-layer
Rate.The stop-layer is not easy the removal that is etched, so as to prevent the fuse metal layer to be exposed.Therefore, described
Forming method can reduce the damage of the fuse metal layer, and then can improve the performance of formed semiconductor structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 10 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Referring to FIG. 4, providing substrate 200, the substrate 200 includes fuse region II.
In the present embodiment, the substrate 200 further includes logic area I.The substrate 200 includes center and surrounds in described
The external zones of heart district, the center of the center are overlapped with the center of the substrate 200.In other embodiments, the substrate
It can not include the logic area.
200 center of substrate and external zones include one or more fuse region II；200 center of substrate
Area and external zones include one or more logic area I.
In the present embodiment, the fuse region II is for being subsequently formed fuse；The logic area I is used to form logical device.
It is subsequent that dielectric structure is formed on the substrate 200, there is fuse connection knot in the fuse region II dielectric structure
Structure has logical connection structure in the logic area I dielectric structure.
In the present embodiment, the fuse region II dielectric structure surface is lower than the logic area I dielectric structure surface, is given an account of
Matter structure includes: the underlying dielectric structure on the logic area I and fuse region II substrate 200；Positioned at the bottom the logic area I
Top layer dielectric structure on layer dielectric structure.The logical connection structure includes: in the logic area I underlying dielectric structure
Lower level logical connection structure；Interlayer connecting line positioned at Lower level logical connection structure surface；Positioned at the top layer medium
Top layer plug in structure, the top layer plug connect the interlayer connecting line and the top layer metallic layer
Specifically, the step of forming the underlying dielectric structure, Lower level logical connection structure and fuse connection structure such as Fig. 4
It is shown.
Referring to FIG. 4, forming underlying dielectric structure, the logic area on the logic area I and fuse region II substrate 200
There is Lower level logical connection structure in I underlying dielectric structure, there is fuse connection knot in the fuse region II underlying dielectric structure
Structure.
The underlying dielectric structure includes: one or more layers layer on the logic area I and fuse region II substrate 200
First underlying dielectric layer 213 of folded setting；In first underlying dielectric layer 213 that one or more layers is stacked
Two underlying dielectric layers.
The Lower level logical connection structure includes: the first bottom in first underlying dielectric layer of logic area I 213
Logical connection structure；The second logical connection structure in second underlying dielectric layer of logic area I, second bottom are patrolled
Connection structure is collected to be electrically connected with the first Lower level logical connection structure.
The first Lower level logical connection structure includes: first in first underlying dielectric layer of logic area I 213
Bottom plug 212, the first bottom plug 212 run through first underlying dielectric layer 213；Positioned at the first bottom plug
The first bottom connecting line 211 on 212 surfaces.
The second bottom connection structure includes: the second bottom plug in second underlying dielectric layer, and second
Bottom plug runs through second underlying dielectric layer, and the second bottom plug connects the first bottom connecting line 211.
The first bottom connecting line 211, the first bottom plug 212 and the second bottom plug are for realizing the lining
Electrical connection between bottom 200 and the interlayer connecting line being subsequently formed.First underlying dielectric layer 213 and the second underlying dielectric layer
For realizing the first bottom connecting line 211 of logic area I, the first bottom plug 212 and the second bottom plug and fuse region
The electric isolution of II.
In the present embodiment, the first bottom connecting line 211, the first bottom plug 212 and the second bottom plug
Material is aluminium.In other embodiments, the material of the first bottom connecting line, the first bottom plug and the second bottom plug
Material can also be copper or tungsten.
The fuse connection structure includes: that the first fuse in first underlying dielectric layer of fuse region II 213 connects
Binding structure；The second fuse connection structure in second underlying dielectric layer of fuse region II.
First fuse connection structure includes: first molten in first underlying dielectric layer of fuse region II 213
Silk plug 222, the first fuse plug 222 run through first underlying dielectric layer 213；Positioned at the first fuse plug
The first fuse metal layer 221 on 222 surfaces.
Second fuse connection structure includes: the second fuse plug in second underlying dielectric layer, described
Second fuse plug runs through second underlying dielectric layer.
The first fuse plug 222, the first fuse connecting line 221 and the second fuse plug are for realizing the fuse region
Being electrically connected between II substrate 200 and the fuse metal layer being subsequently formed；First underlying dielectric layer of fuse region II 213 and
Two underlying dielectric layers are for realizing the first fuse plug 222, the first fuse connecting line 221 and the second fuse plug and logic area I
Electric isolution.
In the present embodiment, the material of the first fuse plug 222, the first fuse connecting line 221 and the second fuse plug
For aluminium.In other embodiments, the material of the first fuse plug, the first fuse connecting line and the second fuse plug can be with
For copper or tungsten.
Referring to FIG. 5, forming interlayer connecting line 231 on Lower level logical connection structure surface；It is connected in the fuse
Body structure surface forms fuse metal layer 230.
The interlayer connecting line 231 is for realizing the electricity between the second bottom plug and the top layer plug being subsequently formed
Connection；The fuse metal layer 230 is used as fuse, and the fuse metal layer 230 can be under the control of high current or luminous energy
Fusing, to realize programming.
In the present embodiment, the interlayer connecting line 231 is identical as the material of the fuse metal layer 230.The interlayer connects
Wiring 231 can be formed with the fuse metal layer 230 by same technique.In other embodiments, the interlayer connecting line
Material with the fuse metal layer can not be identical.
Specifically, the material of the interlayer connecting line 231 and the fuse metal layer 230 is aluminium in the present embodiment.At it
In his embodiment, the material of the fuse metal layer can be copper.
In the present embodiment, forming the interlayer connecting line 231 with the step of fuse metal layer 230 includes: described
Metal layer is formed in Lower level logical connection structure, the fuse connection structure and underlying dielectric structure；The metal layer is carried out
Graphically, interlayer connecting line 231 is formed on Lower level logical connection structure surface, and in fuse connection structure surface shape
At fuse metal layer 230.
Referring to FIG. 6, forming stop-layer 270 on the fuse metal layer 230.
The stop-layer 270 is for playing etching stopping during subsequent etching initial protective layers, thus anti-
Only the fuse metal layer 230 is exposed, to reduce subsequent removal photoresist process to the damage of fuse metal layer 230
Consumption.
In the present embodiment, the material of the stop-layer 270 is not identical as the material for the initial protective layers being subsequently formed.To
During capable of making the initial protective layers described in subsequent etching, the etch rate of the stop-layer 270 is less than the initial guarantor
The etch rate of sheath.
Specifically, the material of the stop-layer 270 is silicon nitride or silicon oxynitride.
If the thickness of the stop-layer 270 is excessive, it is easy to influence the performance of formed semiconductor structure；If described stop
Only the thickness of layer 270 is too small, and during subsequent etching initial protective layers, the stop-layer 270 is easily removed, and leads to institute
Fuse metal layer 230 is stated to be exposed.Specifically, the material of the stop-layer 270 is 700 angstroms~900 in the present embodiment
Angstrom.
Spacing between the thickness of the stop-layer 270 and the interlayer connecting line 231 and fuse metal layer 230 is related.
If the spacing between the interlayer connecting line 231 and fuse metal layer 230 is larger, the fillibility of 270 material of stop-layer
Can preferably, stop-layer 270 is stronger to the protective effect of 230 side wall of fuse metal layer, and the thickness of the stop-layer 270 is smaller；Instead
It, if the spacing between the interlayer connecting line 231 and fuse metal layer 230 is smaller, the thickness of the stop-layer 270 compared with
Greatly.
In the present embodiment, the technique for forming the stop-layer 270 includes chemical vapor deposition process, physical vapour deposition (PVD) work
Skill or atom layer deposition process.
In the present embodiment, the interlayer connecting line 231 is located in the logic area I underlying dielectric structure of part, described to stop
Only layer 270 is also located on the interlayer connecting line 231 and the logic area I underlying dielectric structure.
It is subsequent that top layer dielectric structure, the top layer dielectric structure and stop-layer are formed on the logic area I stop-layer 270
There is top layer plug in 270；Top layer metallic layer is formed in the top layer plug surface；In 270 He of fuse region II stop-layer
Initial protective layers are formed on the top layer metallic layer.
In the present embodiment, the initial protective layers include: the coating on the fuse region II stop-layer 270；Position
Passivation layer on the coating, logic area I dielectric structure and top layer metallic layer 260.Specifically, forming the initial protection
The step of layer, top layer dielectric structure, top layer plug and top layer metallic layer, is as shown in Figure 7 and Figure 8.
Referring to FIG. 7, forming coating 251 on the fuse region II stop-layer 270；In the logic area I stop-layer
Top layer dielectric structure 241 is formed on 270, and there is top layer plug 242, the top layer plug 242 in the top layer dielectric structure 241
Connect the interlayer connecting line 231.
The coating 251 is for during passivation layer 252, protecting the fuse metal layer described in subsequent etching
230 and stop-layer 270.
The step of forming top layer plug 242 includes: the shape in the top layer dielectric layer 241 and the stop-layer 270
At contact hole, the contact hole bottom-exposed goes out the interlayer connecting line 231；Top layer plug 242 is formed in the contact hole.
In the present embodiment, the step of forming the top layer dielectric layer 241 and the coating 251 includes: in the logic
Initial medium floor is formed on area I and fuse region II stop-layer 270；Planarization process is carried out to the initial medium layer, described
Logic area I forms top layer dielectric layer 241, and forms coating 251 in the fuse region II.
In the present embodiment, the material of the top layer dielectric layer 241 and the coating 251 is silica.Silica has
Good isolation performance.
If the thickness of the top layer dielectric layer 241 and the coating 251 is excessive, it is easy to increase formed semiconductor junction
The volume of structure；If the thickness of the top layer dielectric layer 241 and the coating 251 is too small, it is right to be unfavorable for the coating 251
The protective effect of the stop-layer 270 is easy to be removed the stop-layer 270 during subsequent etching passivation layer.Tool
Body, the top layer dielectric layer 241 and the coating 251 with a thickness of 0.91um~1.19um.
It should be noted that the fuse region II dielectric structure surface is lower than the logic area I dielectric structure surface, thus
It can make during forming the top layer metallic layer 260, coating can be formed on the fuse region II stop-layer 270
251, so that protection of the initial protective layers to stop-layer 270 can be increased during the initial protective layers described in subsequent etching
Effect, and then the loss to fuse metal layer 230 can be reduced, improve the performance of formed semiconductor structure.
With continued reference to Fig. 7, top layer metallic layer 260 is formed on the logical connection structure surface.
The top layer metallic layer 260 is connect with the top layer plug 242.The top layer metallic layer 260 is for realizing described
Top layer plug 242 is electrically connected with external circuit.
In the present embodiment, the material of the top layer metallic layer 260 is aluminium.In other embodiments, the top layer metallic layer
Material can also be copper.
The blunt of the top layer dielectric layer 241, top layer metallic layer 260 and the coating 251 is covered referring to FIG. 8, being formed
Change layer 252.
The passivation layer 252 is isolated for realizing top layer metallic layer 260, top layer plug 242 with external environment.
The material of the passivation layer 252 is silica.Silica has good heat-insulated, moisture-proof and insulation performance.
The technique for forming the passivation layer 252 includes chemical vapor deposition process, physical gas-phase deposition or atomic layer
Depositing operation.
The thickness of the passivation layer 252 is related with the thickness of the top layer metallic layer 260.The top layer metallic layer 260
Thickness is bigger, and the thickness of the passivation layer 252 is bigger, and the time of subsequent etching passivation layer 252 is longer；The top layer metallic layer
260 thickness is smaller, and the thickness of the passivation layer 252 is smaller, and the time of subsequent etching passivation layer 252 is shorter.
It is subsequent that the initial protective layers are performed etching, protective layer is formed, the protective layer exposes the fuse metal
Stop-layer 270 on layer 230.
In the etching process, the etch rate of the initial protective layers is greater than the etch rate of the stop-layer 270.
In the present embodiment, the step of performing etching to the initial protective layers, is as shown in Figure 9 and Figure 10.
Referring to FIG. 9, forming patterned photoresist 280 on the initial protective layers.
The photoresist 280 is used as the exposure mask for etching the initial protective layers.The photoresist 280 exposes top-level metallic
Portion of the passivating layer 252 on layer 260 and the passivation layer 252 on the fuse metal layer 230.
In the present embodiment, the technique for forming the photoresist 280 includes spin coating proceeding.
With continued reference to Fig. 9, it is exposure mask with the patterned photoresist 280, the initial protective layers is performed etching, shape
At protective layer, the protective layer exposes the stop-layer 270 on the fuse metal layer 230, and the protective layer exposes institute
State top layer metallic layer 260.
It should be noted that due to during being performed etching to the passivation layer 252, the external zones passivation layer
252 etch rate is less than the etch rate of the center passivation layer 252.When the coating 251 of the center is just sudden and violent
When exposing the stop-layer 270, the passivation layer 252 of the external zones not yet exposes top layer metallic layer 260.In order to make external zones
Passivation layer 252 expose it is described go out top layer metallic layer 260, need that the passivation layer 252 of external zones is continued to etch.Right
During the passivation layer 252 of external zones continues etching, the stop-layer 270 can protect the fuse metal layer 230, reduce
The loss of fuse metal layer 230.
During being performed etching to the initial protective layers, since the etch rate of the stop-layer 270 is less than institute
The etch rate of initial protective layers is stated, the stop-layer 270 is not easily removed, so as in subsequent removal photoresist 280
Technique in protect the fuse metal layer 230.
During being performed etching to the initial protective layers, if the initial protective layers and the stop-layer 270
Etching selection ratio it is too small, be easy to make stop-layer 270 to be etched removal, to be unfavorable for the protection to fuse metal layer 230.
Therefore, the etching selection ratio of the initial protective layers and the stop-layer 270 is greater than 5.Specifically, in the present embodiment, it is described
The etching selection ratio of initial protective layers and the stop-layer 270 is 6.
In the present embodiment, the technique performed etching to the initial protective layers includes dry etch process.In other implementations
In example, the technique performed etching to the initial protective layers includes wet-etching technology.
Specifically, it includes CF that the technological parameter performed etching to the initial protective layers, which includes: etching gas,4And O2；Gas
Flow is 1sccm~100sccm；Power is 500W~3000W.
It selects the meaning of the etching gas flow to be, if the flow of the etching gas is too small, is unfavorable for institute
It states initial protective layers to perform etching, is easy to extend etch period；If the flow of the etching gas is excessive, it is not easy to etching
Process is controlled.
In the present embodiment, since the thickness of the stop-layer 270 is smaller, it is not easy to influence light to the fuse metal layer
230 fusing, so as to not remove the stop-layer 270, and then simplification of flowsheet.
Referring to FIG. 10, being formed after the protective layer, the photoresist 280 (as shown in Figure 9) is removed.
In the present embodiment, the step of removing photoresist 280 includes: to carry out ash to the photoresist by cineration technics
Change processing；After the ashing processing, started the cleaning processing by cleaning agent.
The technological parameter of the cineration technics includes: that reaction gas includes plasma gas and CF4。
Plasma gas with the photoresist 280 for reacting, to remove the photoresist.In plasma gas
With polymer can be generated in 280 reaction process of photoresist, the polymer is liable to stick to 280 surface of photoresist, to prevent
The removal of photoresist 280.Therefore, it needs to pass through CF in podzolic process4Remove the polymer generated.
If CF4Flow it is too small, be easy to make accumulation of polymer and the removal that influences photoresist 280.Therefore, CF4Flow
It is larger.Specifically, in the present embodiment, it is described to remove CF in glue4Flow be 50sccm~500sccm.
The cleaning treatment is for further removing the polymer.The cleaning agent is EKC solution, and EKC solution is hydroxyl
The mixed solution of amine (HDA), aminoethoxyethanol (DGA) and catechol (Catechol).
It should be noted that the stop-layer 270 covers the fuse metal during removing the photoresist 280
Layer 230 so that the stop-layer 270 can prevent glue from contacting with fuse metal layer 230, and then can prevent described remove photoresist
Fuse metal layer 230 described in corrosion.
It should be noted that not removing the stop-layer 270 in the present embodiment, the removal stop-layer 270 can be avoided
Damage of the process to the fuse metal layer 230.
In other embodiments, after removing the photoresist, further includes: remove the stopping on the fuse metal layer
Layer.Remove the stop-layer can, influence of the stop-layer to formed semiconductor structure performance is prevented in programming process.
0 is continued to refer to figure 1, the embodiment of the present invention also provides a kind of semiconductor structure, comprising: substrate 200, the substrate
200 include fuse region II；Dielectric structure on the substrate 200 there is fuse to connect in the fuse region II dielectric structure
Binding structure；Fuse metal layer 230 positioned at the fuse connection structure surface；Stopping on the fuse metal layer 230
Layer 270；Protective layer on the stop-layer 270, the protective layer expose the stop-layer on the fuse metal layer 230
270, the protective layer is not identical as the material of the stop-layer 270.
The stop-layer 270 with a thickness of 700 angstroms~900 angstroms.
The substrate 200 further includes logic area I, has logical connection structure in the logic area I dielectric structure.
The dielectric structure includes: the underlying dielectric structure on the logic area I and fuse region II substrate 200；Position
Top layer dielectric structure in the logic area I underlying dielectric structure.
The logical connection structure includes: the Lower level logical connection structure in the logic area I underlying dielectric structure；
Interlayer connecting line 231 positioned at Lower level logical connection structure surface；Top layer plug in the top layer dielectric structure
242, the top layer plug 242 connects the interlayer connecting line 213 and the top layer metallic layer 260.
Further include: the top layer metallic layer 260 in the logical connection structure.
The stop-layer 270 is also located on the interlayer connecting line 231 and the logic area I underlying dielectric structure.
The protective layer includes: the coating 251 on the fuse region II stop-layer 270, and the coating 251 is sudden and violent
Expose the stop-layer 270 on the fuse metal layer 230；Positioned at the coating 251, logic area II dielectric structure and top layer gold
Belong to the passivation layer 252 on layer 230.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes fuse region；
Dielectric structure is formed over the substrate, and there is fuse connection structure in the fuse region dielectric structure；
Fuse metal layer is formed on the fuse connection structure surface；
Stop-layer is formed on the fuse metal layer；
Initial protective layers are formed on the stop-layer；
The part initial protective layers are performed etching, protective layer is formed, the protective layer exposes on the fuse metal layer
Stop-layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate includes center and packet
The external zones of the center is enclosed, the center of the center is overlapped with the center of the substrate；The center includes one
Or multiple fuse regions, the external zones include one or more fuse regions.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate further includes logic area；
The forming method further include: form logical connection structure in the logic area dielectric structure；In the logical connection structure
Surface forms top layer metallic layer；
The initial protective layers are also located on the top layer metallic layer；The protective layer also exposes the top layer metallic layer.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the substrate includes center and packet
The external zones of the center is enclosed, the center of the center is overlapped with the center of the substrate；The center includes one
Or multiple logic areas, the external zones include one or more logic areas.
5. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that fuse region dielectric structure surface
Lower than logic area dielectric structure surface；The initial protective layers include: the coating on the fuse region stop-layer；
Passivation layer on the coating, logic area dielectric structure and top layer metallic layer.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the material of the coating is oxidation
Silicon, the material of the passivation layer are silica.
7. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the dielectric structure includes: to be located at
Underlying dielectric structure on the logic area and fuse region substrate；Top layer medium in the logic area underlying dielectric structure
Structure；
The logical connection structure includes: the Lower level logical connection structure in the logic area underlying dielectric structure；It is located at
The interlayer connecting line on Lower level logical connection structure surface；Top layer plug in the top layer dielectric structure, the top
Layer plug connects the interlayer connecting line and the top layer metallic layer；
The step of forming the dielectric structure, logical connection structure, fuse connection structure, interlayer connecting line and stop-layer include:
Underlying dielectric structure is formed on the logic area and fuse region substrate, is patrolled in the logic area underlying dielectric structure with bottom
Connection structure is collected, there is fuse connection structure in the fuse region underlying dielectric structure；In the Lower level logical connection structure table
Face forms interlayer connecting line；Fuse metal layer is formed on the fuse connection structure surface；Connect in the fuse metal layer, interlayer
Stop-layer is formed in wiring and the underlying dielectric structure；It is formed after stop-layer, forms top on the logic area stop-layer
Layer dielectric structure.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the initial protective layers include: position
Coating on the fuse region stop-layer；It is blunt on the coating, logic area dielectric structure and top layer metallic layer
Change layer；
The step of forming the initial protective layers, top layer plug, top layer metallic layer and the top layer dielectric structure includes: described
Top layer dielectric structure is formed on logic area stop-layer, and forms coating on the fuse region stop-layer；It is situated between in the top layer
Top layer plug is formed in matter structure；Top layer metallic layer is formed in the top layer plug surface；It is situated between in the top layer metallic layer, top layer
Passivation layer is formed on matter structure and the coating.
9. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the material of the fuse metal layer with
The material of the interlayer connecting line is identical.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that the initial protective layers into
During row etching, the ratio of the etch rate of the etch rate of the protective layer and the stop-layer is greater than 5.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the initial protective layers
Including silica, the material of the stop-layer is silicon nitride or silicon oxynitride；
The technique for forming the stop-layer includes chemical vapor deposition process, physical gas-phase deposition or atomic layer deposition work
Skill.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that formed protective layer the step of include:
Patterned photoresist is formed on the initial protective layers, the photoresist exposes the initial guarantor on the fuse metal layer
Sheath；The initial protective layers are performed etching to the stopping exposed on the fuse metal layer using the photoresist as exposure mask
Layer；After performing etching as exposure mask to the initial protective layers using the photoresist, the photoresist is removed.
13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the technique for removing the photoresist
Including cineration technics, the reactant of the cineration technics includes CF4。
14. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that after removing the photoresist,
Further include: remove the stop-layer of the fuse region.
15. the forming method of semiconductor structure as described in claim 1, which is characterized in that carried out to the initial protective layers
The technique of etching includes dry etch process.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that when to the initial protective layers into
When the technique of row etching is dry etch process, the technological parameter performed etching to the initial protective layers includes: etching gas
Including CF4And O2；Gas flow is 1sccm~100sccm；Power is 500W~3000W.
17. a kind of semiconductor structure characterized by comprising
Substrate, the substrate include fuse region；
Dielectric structure on the substrate has fuse connection structure in the fuse region dielectric structure；
Fuse metal layer positioned at the fuse connection structure surface；
Stop-layer on the fuse metal layer；
Protective layer on the stop-layer, the protective layer expose the stop-layer on the fuse metal layer, the guarantor
Sheath is not identical as the material of the stop-layer.
18. semiconductor structure as claimed in claim 17, which is characterized in that the material of the protective layer includes silica, institute
The material for stating stop-layer is silicon nitride.
19. semiconductor structure as claimed in claim 17, which is characterized in that the stop-layer with a thickness of 700 angstroms~900
Angstrom.
20. semiconductor structure as claimed in claim 17, which is characterized in that the substrate further includes logic area, the logic
There is logical connection structure in area's dielectric structure；
The dielectric structure includes: the underlying dielectric structure on the logic area and fuse region substrate；Positioned at the logic
Top layer dielectric structure in area's underlying dielectric structure；
The logical connection structure includes: the Lower level logical connection structure in the logic area underlying dielectric structure；It is located at
The interlayer connecting line on Lower level logical connection structure surface；Top layer plug in the top layer dielectric structure, the top
Layer plug connects the interlayer connecting line and the top layer metallic layer；
The stop-layer is also located on the interlayer connecting line and the logic area underlying dielectric structure；
The protective layer includes: the coating on the fuse region stop-layer, and the coating exposes the fuse gold
Belong to the stop-layer on layer；Passivation layer on the coating, logic area dielectric structure and top layer metallic layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220115321A1 (en) * | 2020-10-12 | 2022-04-14 | Chantgxin Memory Technologies, Inc. | Fuse structure and formation method |
| WO2022095418A1 (en) * | 2020-11-05 | 2022-05-12 | 长鑫存储技术有限公司 | Integrated circuit device and forming method thereof |
| US11769725B2 (en) | 2020-11-05 | 2023-09-26 | Changxin Memory Technologies, Inc. | Integrated circuit device and formation method thereof |
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| CN1469466A (en) * | 2002-07-19 | 2004-01-21 | 联华电子股份有限公司 | Semiconductor structure with copper fuse wire and its forming process |
| CN102054765A (en) * | 2009-10-29 | 2011-05-11 | 无锡华润上华半导体有限公司 | Method for forming fuse structure |
| JP2017069436A (en) * | 2015-09-30 | 2017-04-06 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device manufacturing method |
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| CN1469466A (en) * | 2002-07-19 | 2004-01-21 | 联华电子股份有限公司 | Semiconductor structure with copper fuse wire and its forming process |
| CN102054765A (en) * | 2009-10-29 | 2011-05-11 | 无锡华润上华半导体有限公司 | Method for forming fuse structure |
| JP2017069436A (en) * | 2015-09-30 | 2017-04-06 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device manufacturing method |
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| US20220115321A1 (en) * | 2020-10-12 | 2022-04-14 | Chantgxin Memory Technologies, Inc. | Fuse structure and formation method |
| WO2022095418A1 (en) * | 2020-11-05 | 2022-05-12 | 长鑫存储技术有限公司 | Integrated circuit device and forming method thereof |
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Application publication date: 20190305 |