CN109298980A - A kind of IIC storage chip common circuit, electronic device and its stand-by circuit switching method - Google Patents
A kind of IIC storage chip common circuit, electronic device and its stand-by circuit switching method Download PDFInfo
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- CN109298980A CN109298980A CN201810984172.5A CN201810984172A CN109298980A CN 109298980 A CN109298980 A CN 109298980A CN 201810984172 A CN201810984172 A CN 201810984172A CN 109298980 A CN109298980 A CN 109298980A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
- G06F11/2089—Redundant storage control functionality
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
Abstract
The present invention relates to a kind of IIC storage chip common circuit, electronic device and its stand-by circuit switching methods, belong to electronic circuit technology field.Specifically include that first singlechip is connect by three road optocouplers with storage chip; the two-wire system of second singlechip routine is connect with storage chip; to realize pin-saving chip insulation blocking and share; the linking for keeping standby control circuit quickly seamless when governor circuit breaks down, to ensure the normal operation of electronic device.This scheme further improves the reliability of the electronic device using fallback circuit design, while saving storage chip, simplify exploitation design work and improving the operational efficiency of electronic device.
Description
Technical field
The present invention relates to a kind of IIC storage chip common circuit, electronic device and its stand-by circuit switching methods, belong to electricity
Sub-circuit technical field.
Background technique
In order to improve the reliability of electronic equipment, redundant backup circuit is generally used, in this way, when event occurs in main control circuit
When barrier, stand-by circuit can substitute main control circuit, the normal operation of safeguards system.In this kind of electronic device, for example, it is some
Gate inhibition's product also uses the spare running scheme of some gate inhibitions in the high application scenarios of reliability requirement, and this kind of scheme is past
Toward two independent control circuits of single-chip microcontroller (microcontroller) are used, i.e., governor circuit is constituted by main control singlechip, by spare list
At standby control circuit, main control circuit is relatively independent with standby control circuit for piece mechanism.As shown in Figure 1, to be existing common
One of embedded control system redundant backup circuit scheme, between main control singlechip (microcontroller) and spare single-chip microcontroller
It is general to be communicated by serial ports (or IIC or SPI) to exchange data, and store data in respective storage chip.It is this to set
Meter scheme can improve the reliability of electronic device on certain procedures, but also defective, mainly there is the following aspects:
1) in the case where application scenes especially bad environments, the control circuit of correlation function (such as the motor in access control system
Driving circuit) it is easy to cause failure, there are direct connections for this two single-chip microcontrollers, also there is hidden danger, i.e., if worked as
Main control singlechip circuit breaks down, and especially when serious, main control singlechip occurs burning phenomenon, at this point, entire monolithic machine core
Piece is often in short-circuit condition, causes the spare single-chip microcontroller being directly connected to and its control circuit also to will receive serious influence, sternly
In the case where weight, may influence spare control circuit failure can not be worked normally；2) side of this standby control circuit
There is also the communication protocols for needing to establish between two single-chip microcontrollers for case, and programming is complicated, implements heavy workload, development cost
It is high；3) for this electronic device in actual moving process, main control singlechip will increase the signal procedure of operation with spare single-chip microcontroller,
Spare single-chip microcontroller also waits for receiving the data of main control singlechip transmission, also increases the operation expense of entire electronic device；4)
Generally in this kind of electronic device, since data volume is little, it is basic to store to generally use the EEPROM storage chip of iic bus
Operating parameter and basic log, and the EEPROM storage chip price of relatively high capacity is high, also increases cost.
Basically, it to realize when breaking down, standby control circuit can be with main control electricity in basic function
Road without seam linking, key point be standby control circuit need have the fortune being stored in EEPROM identical with governor circuit
Row parameter.If being capable of providing corresponding protective separation again while realizing pin-saving chip and sharing, stand-by circuit is just
Quickly can seamlessly it be connected when governor circuit breaks down, to ensure the normal operation of electronic device.
Summary of the invention
The technical problem to be solved by the present invention is in view of the above-mentioned problems, it is necessary to provide a kind of storage chip common circuit,
To realize governor circuit and slack storage chip, in circuit when governor circuit breaks down, stand-by circuit still is able to read and write
The data of storage chip, it is ensured that the normal operation of electronic device.
In addition, there is a need to provide a kind of electronic device and its stand-by circuit switching method, with realize governor circuit with it is standby
With storage chip, in circuit when governor circuit breaks down, stand-by circuit still is able to the data of read-write storage chip, it is ensured that
The normal operation of electronic device.
The technical scheme is that one kind deposits IIC storage chip common circuit, it is applied in electronic device, comprising: first
The storage chip of single-chip microcontroller, second singlechip and IIC interface；The first singlechip is connected by three road optocouplers and storage chip
It connecing, wherein the port SCL of the first singlechip is connected by the port SCL of the first optocoupler and storage chip, and described first
The port SDA of single-chip microcontroller is divided into two-way, is respectively used to read or write, by the optocoupler of one-way communication, by increasing by a road port
Mode is divided into two-way, all the way for reading, all the way for writing, to realize two-way communication；First end SDA of the first singlechip
Mouth is connected by the port SDA of the second optocoupler and storage chip, and the 2nd port SDA of the first singlechip passes through third optocoupler
It is connect with the port SDA of storage chip；The port SCL of the second singlechip and the port SCL of storage chip connect, and described the
The port SDA of two single-chip microcontrollers is connect with the port SDA of the storage chip.
The port SCL of the first singlechip is connect with the cathode of the input terminal of the first optocoupler, the input terminal of the first optocoupler
Anode connect with positive pole by resistance, the port the SCL connection of the collector and storage chip of the output end of the first optocoupler,
The emitter of the output end of first optocoupler is connect with power cathode；First port SDA of the first singlechip and the second optocoupler
Input terminal cathode connection, the anode of the input terminal of the second optocoupler connect by resistance with positive pole, the second optocoupler it is defeated
The collector of outlet and the port SDA of storage chip connect, and the emitter of the output end of the second optocoupler is connect with power cathode；Institute
The 2nd port SDA for stating first singlechip is connect with the collector of the output end of third optocoupler, the current collection of third optocoupler output
Pole is connect by resistance with positive pole, and the emitter of the output end of third optocoupler is connect with power cathode, third optocoupler it is defeated
The anode for entering end is connect by resistance with positive pole, and the cathode of third optocoupler and the port SDA of storage chip connect；Store core
The port SCL of piece is connect by resistance with positive pole, and the port SDA of storage chip is connect by resistance with positive pole.
The first singlechip writes data to storage chip by its port SCL and the port SDA；The first singlechip is logical
It crosses its port SCL and the 2nd port SDA and reads data from storage chip；Second singlechip is by its port SCL and the port SDA from depositing
Store up chip reading and writing data.The first singlechip when communicating with storage chip, during writing data, passes through the port SCL
High level or low level tranmitting data register signal are set, and cooperates clock signal, high level or low level are set by its first port SDA
Data " 1 " or " 0 " are write in realization；During reading data, high level or low level tranmitting data register signal are set by the port SCL,
And cooperate clock number, read the high level occurred on its 2nd port SDA or low level further to receive data " 1 " or " 0 ".
The second singlechip periodically detects whether its port SCL or the port SDA low level occur to determine whether there is number
Then show there is data communication when there is low level according to communication, otherwise, is judged as that no data communicates, to avoid communication contention aware.
A kind of electronic device, including above-described storage chip common circuit, the first singlechip are master control monolithic
Machine, the second singlechip are spare single-chip microcontroller.In the electronic device, standby electricity is constituted based on second singlechip
Road；The first singlechip includes: the first storage chip module for reading and writing, for being communicated by iic bus with storage chip, with reality
Now to the read-write of storage chip；Heartbeat packet module, for periodically sending heartbeat packet on iic bus.The second singlechip packet
Include: whether IIC detecting module has IIC data communication for detecting on the port SCL or SDA.
Second singlechip further include: spare switching module, for according to IIC detecting module to whether there is or not data communications to detect
It surveys, further timing, if at the appointed time threshold value does not have a data communication, the work of adapter tube first singlechip, from spare
Low power consumpting state is switched to the state of normal work, with the work of adapter tube first singlechip.Second storage chip module for reading and writing is used
In being communicated with storage chip for second singlechip, to realize the read-write to storage chip；Warning note module is used for the second monolithic
After the work of machine adapter tube first singlechip, warning note is carried out, to remind user to replace electronic device；
A kind of stand-by circuit switching method is applied in electronic device, including above-described storage chip common circuit,
The first singlechip is main control singlechip, and the second singlechip is spare single-chip microcontroller.In the electronic device, with second
Stand-by circuit is constituted based on single-chip microcontroller, which comprises
The first singlechip is communicated by iic bus with storage chip, to realize the read-write to storage chip.
The first singlechip periodically sends heartbeat packet on iic bus.
Whether there is data communication on the second monolithic detecting iic bus.
Second singlechip is according to whether there is or not the detecting of data communication, further timing, if at the appointed time threshold value does not have
Data communication, the then work of adapter tube first singlechip, the state of normal work is switched to from spare low power consumpting state, with adapter tube
The work of first singlechip.
Second singlechip is communicated with storage chip, the read-write to storage chip.
After the work of second singlechip adapter tube first singlechip, warning note is carried out, to remind user to replace electronic device.
The second singlechip judges that whether having IIC data communication on iic bus is judged on the port SDA or the port SCL
Whether low level is occurred；If there is low level, then show there is data communication on iic bus.
It is shared the beneficial effects of the present invention are: the present invention realizes pin-saving chip by light-coupled isolation protected mode,
Make standby control circuit being capable of the quickly work of seamless adapter tube main control circuit when governor circuit breaks down.This side
Case further improves the reliability of the electronic device using fallback circuit design, while saving storage chip, and simplifies
Exploitation design work and the operational efficiency for improving electronic device.
Detailed description of the invention
Fig. 1 is the structural block diagram of prior art Standby control circuit described in background of invention；
Fig. 2 is the schematic diagram of the storage chip common circuit of the embodiment of the present invention；
Fig. 3 is the structural block diagram of the electronic device of the embodiment of the present invention；
Fig. 4 is the flow chart of the method for the embodiment of the present invention.
Specific embodiment
With reference to the accompanying drawings and detailed description, the invention will be further described.
As shown in Fig. 2, for a kind of schematic diagram of IIC storage chip common circuit of the present invention.Include: first singlechip U1,
The storage chip U3 of second singlechip U2 and IIC interface；The first singlechip U1 passes through three road optocouplers and storage chip U3
Connection, wherein the port the SCL U1_13 of the first singlechip U1 passes through the port SCL of the first optocoupler U4 and storage chip U3
U3_6 connection, and the port SDA of the first singlechip U1 is divided into two-way, be respectively used to read perhaps to write be respectively used to read or
It writes, by the optocoupler of one-way communication, is divided into two-way by way of increasing by a road port, all the way for reading, all the way for writing, thus
Realize two-way communication；First port SDA U1_12 of the first singlechip passes through the SDA of the second optocoupler U5 and storage chip U3
Port U3_5 connection, the 2nd port SDA U1_11 of the first singlechip pass through the SDA of third optocoupler U6 and storage chip U3
Port U3_5 connection；The port the SCL U3_6 of the port the SCL U2_20 and storage chip U3 of the second singlechip U2 are connect, described
The port the SDA U3_5 of the port the SDA U2_19 and storage chip U3 of second singlechip U2 are connect.
One basic ideas of the present embodiment are exactly isolated governor circuit and stand-by circuit using optocoupler, while energy
Enough realize sharing for storage chip.It is isolated using governor circuit with storage chip and stand-by circuit and IIC storage chip are straight
It connects in succession, is to be easy to cause failure, if direct-connected, there is also governor circuits to go out because governor circuit is usually to work normally
After existing failure, stand-by circuit can not also read and write storage chip.The mode standard of iic bus is 100Kbps, and high-speed mode is
400Kbps, the conversion rate of high speed photo coupling product is fully able to meet demand up to 10Mbps at present.
Stand-by circuit in an electronic is typically in idle state, in general, spare single-chip microcontroller is also at suspend mode shape
State, it is not easy to cause failure.Certainly, light-coupled isolation can also also be carried out using stand-by circuit here, on the one hand in order to save light
Coupling chip, on the other hand, this isolation is for the stand-by circuit that only emergency transition uses, it appears extra.Based on this
On the basis of kind circuit connection scheme, governor circuit can also be had using the scheme of double storage chips, that is, main control circuit
The storage chip oneself being directly connected to, the also above-described storage chip connected by optocoupler, this double storage chips,
Under storage chip access (being especially written) frequent application scenarios, facilitate the reliable of the storage for further increasing main control circuit
Property.It is possible to further be only written crucial basic data to share storage chip in the case where reading and writing frequent situation, to reduce
To the read-write number of share storage chip.Certainly, disadvantage be exactly increase hardware cost, meanwhile, also increase storage chip reading
The expense write.But in the case where storage chip is written infrequently, it is not recommended that use this scheme.
The storage chip used in the present embodiment is the storage chip based on iic bus.Iic bus is that a kind of support is set more
Standby bus.In an IIC communication bus, multiple IIC communication equipments can be connected, support multiple main devices and multiple from device
Communication.In general, iic bus only uses two bus lines, a bidirectional serial data lines (SDA), a serial time clock line
(SCL).Data line is used to indicate data, and clock line is synchronous for data transmit-receive.The equipment for being each connected to bus has one
A independent address, main device can use the access between this address progress distinct device.Bus is connect by pull-up resistor
To power supply.When all devices are all idle in bus, bus is pulled into high level by pull-up resistor.It is a kind of normal using light-coupled isolation
Scheme, but optocoupler is unidirectional, and using IIC communication be a kind of two-way communication in this storage chip, also just need into
Row is read or is write.Often there is iic bus hardware interface in single-chip microcontroller at present, can be by Hardware I IC come read-write equipment, it can also
To pass through software simulated implementation read-write equipment.But the defect that hardware mode reads and writes iic bus is exactly to have limited to the I/O port of single-chip microcontroller,
And IIC is simulated with software, I/O port oneself can be defined according to their own needs, as long as any one single-chip microcontroller has I/O port, so that it may
With the cracking transplanting past, and specific I/O port is not needed.Therefore, read-write of the general industry to iic bus equipment, it is main at present
To use software analog form.And in the present embodiment, the mode for being all made of software simulation reads and writes IIC equipment, in this way can be flexible
The customized port SDA of the applicable cases according to actual circuit and the port SCL.It is appreciated that in the present embodiment, the SCL
Port and the port SDA can be customized, the I/O port that can also be specified using hardware.Certainly, if posted using what hardware was specified
Storage configuration may result in three line modes used by the present embodiment if completing read-write by two-wire system hardware mode
IIC communication mode is limited to or can only read or can only write.Although in this way, also can satisfy under specific application scenarios
Functional requirement.
The basic ideas for improving share storage chip reliability as the present embodiment are exactly: light-coupled isolation, and read-write separates.It reads
It writes and separates, realize unidirectional optocoupler by increasing mouth line to be converted to two-way communication.The above analysis it is found that optionally,
First singlechip U1 can only retain the read port all the way of SDA perhaps SDA write port all the way for be only written data or
Only read the specific application scene of data.In this way, it is possible to reduce the application of optocoupler all the way.
The SCL of iic bus is the clock of IIC, is often issued by main device, and controlled by main device, is unidirectional；
SDA line is two-way as data line.In the present embodiment, single-chip microcontroller is used as main device, and storage chip is used as from device.
First singlechip U1 is connect by optocoupler with storage chip U3, and second singlechip U2 is to be directly connected to optocoupler.Therefore, SCL
A line is needed, the read-write of the i.e. controllable storage chip of low level can be generated.For first singlechip, SDA be it is two-way,
But optocoupler be it is unidirectional, therefore, SDA needs two-way optocoupler, could bidirectional data transfers, in the present embodiment, SDA line is divided into two
Road is all the way reading data (R), it may be assumed that the first port SDA U1_12 and the 2nd port SDA U1_11 all the way to write data (W).It has
Body connection is described as follows:
The port the SCL U1_13 of the first singlechip U1 is connect with the cathode U4_2 of the input terminal of the first optocoupler U4, and first
The positive U4_1 of the input terminal of optocoupler U4 is connect by resistance R1 with positive pole, the collector of the output end of the first optocoupler U4
The connection of the port SCL of U4_4 and storage chip, the emitter U4_3 of the output end of the first optocoupler U4 are connect with power cathode；It is described
The first port the SDA U1_12 of first singlechip U1 is connect with the cathode U5_2 of the input terminal of the second optocoupler U5, the second optocoupler U5's
The positive U5_1 of input terminal is connect by resistance R2 with positive pole, the collector U5_4 of the output end of the second optocoupler U5 and storage
The port the SDA U3_5 connection of chip U3, the emitter U5_3 of the output end of the second optocoupler U5 are connect with power cathode；Described first
The 2nd port the SDA U1_11 of single-chip microcontroller U1 is connect with the collector U6_4 of the output end of third optocoupler U6, third optocoupler U6 output
The collector U6_4 at end is connect by resistance R3 with positive pole, and the emitter U6_3 and power supply of the output end of third optocoupler U6 are negative
The positive U6_1 of pole connection, the input terminal of third optocoupler U6 is connect by resistance R4 with positive pole, the cathode of third optocoupler U6
It is connect with the port the SDA U3_5 of storage chip U3；The port the SCL U3_6 of storage chip U3 is connected by resistance R5 and positive pole
It connects, the port the SDA U3_5 of storage chip U3 is connect by resistance R6 with positive pole.
As pull-up resistor, being in some cases can be unused by resistance R3, R5, R6 described above, usually used to be
In order to which circuit is relatively reliable；And R1, R2, R4 must be connected as current-limiting resistance.The first singlechip U1 passes through it
The port SCL U1_13 and the first port SDA U1_12 writes data to storage chip U3；Its port SCL the first singlechip U1 and
2nd port SDA U1_11 reads data from storage chip U3.The second singlechip U2 passes through its port SCL U2_20 and the end SDA
Mouth U2_19 reads and writes data from storage chip U3.
When first singlechip U1 reads and writes storage chip U3, main device of the first singlechip U1 as IIC, and storage chip
Slave device of the U3 as iic bus.SCL is controlled by first singlechip U1, is unidirectional.When read-write, first singlechip U1 control
The low and high level of its port SCL issues clock control signal, realizes that data transmit-receive is synchronous.When sending data, first singlechip
U1 controls the low and high level of its first port SDA U1_12, realizes the transmission of data bit (0 or 1)；When receiving data, first is single
Piece machine U1 reads the low and high level on the U1_11 of its 2nd port SDA, realizes the reading of data bit (0 or 1).And second singlechip
When U2 reads and writes storage chip U3, it is written and read according to the reading/writing method of conventional dual bus, just no longer has been described in detail here.
When first singlechip U1 reads and writes IIC storage chip U3 by the way of software simulation, it is different from second singlechip
Using the program of conventional software simulation read-write, only uses one SDA mouthfuls and be written and read, but also only need to determine the port for writing data
Justice is write port (the first SDA port U1_12), and is read port (the 2nd SDA port U1_11) by the port definition for reading data.
The first singlechip U1, when being communicated with storage chip U3, during writing data, by its port SCL
U1_13 sets high level or low level tranmitting data register signal, and cooperates clock signal, by setting height to its first port SDA U1_12
Data " 1 " or " 0 " are write in level or low level realization；During reading data, by its port SCL U1_13 set high level or
Low level tranmitting data register signal, and cooperate clock number, read the high level occurred on the U1_11 of its 2nd port SDA or low level from
And receive data " 1 " or " 0 ".
Since optocoupler is unidirectional, and the SDA line of iic bus is two-way.First singlechip U1 passes through the first port SDA
When U1_12 writes 0 to storage chip U3, the first port SDA U1_12 of first singlechip U1 be low level, by the principle of optocoupler it is found that
The output end of optocoupler U5 is connected, and since its output end emitter U5_3 is grounded (power cathode), then collector U5_4 output is also
Low level, entire SDA line are pulled low, and are low level 0；And when writing 1, the output end of optocoupler U5 ends, due to pull-up resistor R6
Effect, be high level 1 on SDA line.Same principle, when storage chip U3 transmits 0 to first singlechip U1, SDA line quilt
It drags down, the output end conducting of optocoupler U6, since the emitter U6_3 of output end is grounded (power cathode), then its collector U6_4 is defeated
Out it is low level, is i.e. is low level 0 on the 2nd port the SDA U1_11 of first singlechip U1.When storage chip U3 is to the first monolithic
It is high level on SDA line, the output end of optocoupler U6 ends, due to the effect of pull-up resistor R6, the first monolithic when machine U1 transmission 1
It is high level 1 on the 2nd port the SDA U1_11 of machine U1.Also it is achieved that SDA's is bi-directionally transmitted in this way.As it can be seen that this mode electricity
Road is simple, that is, increases an I/O port, is achieved that isolation and two-way communication, and the I/O port of single-chip microcontroller all compares at present
It is abundant.
The second singlechip U2 periodically detects whether its port SCL U2_20 or port SDA U2_19 low level occurs
Data communication is judged whether there is, when there is low level, then shows there is data communication, otherwise, is judged as that no data communicates, to avoid
Communication contention aware.
In the design of shared storage chip, it is high electricity when due to the iic bus free time that it is in need of consideration for, which avoiding conflict,
It is flat, can judge whether bus is idle by whether occurring low level in bus using this characteristic, without designing volume
Outer circuit judges.
It should be noted that using three single channel opto-coupler chips in the present embodiment for ease of description, can also use
The chip of integrated multipath optocoupler, principle are consistent on one chip.
As shown in figure 3, being a kind of structural block diagram of electronic device 300, shared including the above storage chip as shown in Figure 2
Circuit, the first singlechip U1 are main control singlechip, and the second singlechip U2 is spare single-chip microcontroller.In the electronic device
In 300, stand-by circuit is constituted based on second singlechip U2；The first singlechip U1 includes: the read-write of the first storage chip
Module U11, for being communicated by iic bus with storage chip, to realize the read-write to storage chip；Heartbeat packet module U12 is used
In periodically sending heartbeat packet on iic bus.The second singlechip U2 includes: IIC detecting module U21, total for detecting IIC
Whether there is data communication on line.
The so-called module of the present embodiment, that is, the computer program code segments that can be executed in single-chip microcontroller.It is described above
Storage chip common circuit applied in actual electronic device, needing to meet most basic function is exactly first singlechip
U1 needs to read and write storage chip.Then, further, in order to avoid additional circuit design expense, the first monolithic can be passed through
Machine U1 using it is idle when, periodically send heartbeat packet on iic bus, and at this point, second singlechip U2 just to pass through periodic detection total
Whether whether have heartbeat packet on line has communication on detecting iic bus to realize.In this manner it is possible to further judge first singlechip
Whether U1 is normally working.Of course, it is possible to not have to by sending heartbeat packet, and directly detect on iic bus since first is single
Piece machine U1 read-write storage chip U3's and the low level that is likely to occur detects whether have data communication, but this mode may
There are problems that timeliness and timeliness.Because of actual electronic device, especially in access control system, whether first singlechip U1
It is uncertain for being written and read to storage chip U3.It is crossed in order to avoid data volume, general heartbeat packet can be specific using a byte
Number indicates.And the setting about heartbeat packet time interval, it be depending on practical situations.It is high in requirement of real-time
Default obtains smaller, and can be set to be large in the not high system of requirement of real-time, such as 30 seconds or 60 seconds.
Second singlechip U2 further include: spare switching module U22 is used for according to IIC detecting module to whether there is or not data communications
Detecting, further timing, if at the appointed time threshold value does not have a data communication, the work of adapter tube first singlechip U1, from
Spare low power consumpting state is switched to the state of normal work, with the work of adapter tube first singlechip U1.Second storage chip is read
Writing module U23 is communicated for second singlechip U2 with storage chip U3, to realize the read-write to storage chip U3；Warning note
Module U24 after the work for second singlechip U2 adapter tube first singlechip U1, carries out warning note, to remind user to replace
Electronic device.
Second singlechip U2 judges according to the time interval of heartbeat packet, for example heartbeat packet time interval is 30 seconds, if
Spare single-chip microcontroller all confiscates heartbeat packet in 60 seconds, i.e. time threshold is set as 60 seconds, then may determine that first singlechip
U1 operation irregularity.Certainly, it for reliability the considerations of, can also judge to confiscate heartbeat packet in 90 seconds, then judge the first monolithic
Machine U1 operation irregularity.Certainly, second singlechip U2 can also work in timing dormancy state, to save power consumption, it is generally the case that
Stand-by circuit is all often to operate in low power consumpting state, to reduce the power consumption of electronic device to greatest extent.In second singlechip
After U2 adapter tube, generally requires to exit low power consumpting state, into normal working condition, while wanting normally read and write storage chip
U3 is likely to guarantee the normal work of electronic device 300.Meanwhile electronic device 300 has been in a kind of less reliable shape
State, needs to issue alarm to prompt user's more exchange device, in general, in electronic device 300, can using special buzzer come into
Row warning note.
Second singlechip U2 judges whether first singlechip U1 is working properly with cut-in stand-by circuit, can there is many sides
Method.For example, special circuit can be increased to detect the working condition of first singlechip U1 to judge, or pressed by design
Key is completed adapter tube state by the mode of user's manual switching.But these methods can all bring additional hardware cost.
A kind of stand-by circuit switching method is applied in electronic device 300, including above-described storage chip shares electricity
Road, the first singlechip U1 are main control singlechip, and the second singlechip U2 is spare single-chip microcontroller.In the electronic device
In 300, stand-by circuit is constituted based on second singlechip U2, which comprises
S1, the first singlechip U1 are communicated by iic bus with storage chip, to realize the read-write to storage chip.
S2, the first singlechip U1 periodically send heartbeat packet on iic bus；
Whether there is data communication on S3, the second singlechip U2 detecting iic bus.
S4, second singlechip are according to whether there is or not the detecting of data communication, further timing, if at the appointed time threshold value does not have
There is data communication, then the work of adapter tube first singlechip U1, the state of normal work is switched to from spare low power consumpting state, with
The work of adapter tube first singlechip U1.
S5, second singlechip U2 are communicated with storage chip U3, to realize the read-write to storage chip U3.
S6, second singlechip U2 adapter tube first singlechip U1 work after, carry out warning note, with remind user replace electricity
Sub-device 300.
In step s3, the second singlechip U2 judges that whether having IIC data communication on iic bus is to judge the end SDA
Whether there is low level on mouth U2_19 or SCL port U2_20；If there is low level, then show there are data logical on iic bus
Letter.
Judge whether there is data communication on iic bus, can be using the heartbeat bag data read on iic bus, it can also be with
Read the data deposited and read and write on iic bus to storage chip, and most simple and fast method, exactly judge on iic bus whether
There is low level.Because being always at high level in bus (SCL line and person's SDA line) in the iic bus free time.
The light-coupled isolation protected mode that the present embodiment proposes realizes pin-saving chip and shares, and enables standby control circuit
Enough linkings quickly seamless when governor circuit breaks down, to ensure the normal work of electronic device.Due to using optocoupler every
From avoiding the direct connection of governor circuit and stand-by circuit, improve the reliability of electronic device；Using share storage core
Piece saves storage chip, reduces hardware cost；Due to share storage chip, the inconsistence problems of data are avoided, are both
Identical storage chip is operated, there is identical data storage organization, can directly be multiplexed relevant program code, less use
Relevant data communication protocol is established to exchange data, exploitation design work is largely simplified, reduces development cost.
It should be understood that the invention is not limited to the specific structure for being described above and being shown in the accompanying drawings,
Connection and method.Although in embodiment all to the solution of the present invention, basic ideas and principle and basic principle and beneficial effect
Relatively be described in detail, and for those skilled in the art can also be to above based on these thinkings and principle
Documented technical solution is modified or is equivalently replaced to part of scheme.Therefore, all in spirit of the invention
With any modifications, equivalent replacements, and improvements made within principle etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of IIC storage chip common circuit, be applied in electronic device, comprising: first singlechip, second singlechip and
The storage chip of IIC interface, it is characterised in that: the first singlechip is connect by three road optocouplers with storage chip, wherein institute
The port SCL for stating first singlechip is connected by the port SCL of the first optocoupler and storage chip, and the first singlechip
The port SDA is divided into two-way, is respectively used to read or write, and the optocoupler of one-way communication is divided by way of increasing by a road port
Two-way, all the way for reading, all the way for writing, to realize two-way communication；First port SDA of the first singlechip passes through the
2nd port SDA of the connection of the port SDA of two optocouplers and storage chip, the first singlechip passes through third optocoupler and storage core
The port SDA of piece connects；The port SCL of the second singlechip and the port SCL of storage chip connect, the second singlechip
The port SDA connect with the port SDA of the storage chip.
2. IIC storage chip common circuit according to claim 1, it is characterised in that: the end SCL of the first singlechip
Mouth is connect with the cathode of the input terminal of the first optocoupler, and the anode of the input terminal of the first optocoupler is connect by resistance with positive pole,
The collector of the output end of first optocoupler and the port SCL of storage chip connect, the emitter and electricity of the output end of the first optocoupler
The connection of source cathode；First port SDA of the first singlechip is connect with the cathode of the input terminal of the second optocoupler, the second optocoupler
The anode of input terminal is connect by resistance with positive pole, the collector of the output end of the second optocoupler and the end SDA of storage chip
Mouth connection, the emitter of the output end of the second optocoupler are connect with power cathode；2nd port SDA of the first singlechip and the
The collector of the output end of three optocouplers connects, and the collector of third optocoupler output is connect by resistance with positive pole, third
The emitter of the output end of optocoupler is connect with power cathode, and the anode of the input terminal of third optocoupler is connected by resistance and positive pole
It connects, the cathode of third optocoupler and the port SDA of storage chip connect；The port SCL of storage chip passes through resistance and positive pole
The port SDA of connection, storage chip is connect by resistance with positive pole.
3. IIC storage chip common circuit according to claim 2, it is characterised in that: the first singlechip passes through it
Data are write to storage chip in the port SCL and the port SDA；The first singlechip is by its port SCL and the 2nd port SDA from depositing
It stores up chip and reads data；The second singlechip passes through its port SCL and the port SDA from storage chip reading and writing data.
4. IIC storage chip common circuit according to claim 3, it is characterised in that: the first singlechip, with storage
When chip communication, during writing data, high level or low level tranmitting data register signal are set by its port SCL, and cooperate
Clock signal sets high level by its first port SDA or data " 1 " or " 0 " is write in low level realization；In the process for reading data
In, high level or low level tranmitting data register signal are set by its port SCL, and cooperate clock signal, reads its 2nd port SDA
The high level or low level of upper appearance are to receive data " 1 " or " 0 ".
5. IIC storage chip common circuit according to claim 3, it is characterised in that: the second singlechip is periodically detectd
It surveys whether its port SCL or the port SDA low level occur to determine whether there is data communication, when there is low level, then shows have
Otherwise data communication is judged as that no data communicates, to avoid communication contention aware.
6. a kind of electronic device, it is characterised in that: described including any storage chip common circuit of claim 1 to 5
First singlechip is main control singlechip, and the second singlechip is spare single-chip microcontroller；In the electronic device, with the second monolithic
Stand-by circuit is constituted based on machine；The first singlechip includes at least: the first storage chip module for reading and writing, for passing through IIC
Bus is communicated with storage chip, to realize the read-write to storage chip；Heartbeat packet module, for periodically being sent on iic bus
Heartbeat packet；The second singlechip includes: IIC detecting module, whether has data communication on iic bus for detecting.
7. electronic device according to claim 3, it is characterised in that: the second singlechip further include: spare switching mould
Block, for according to IIC detecting module to whether there is or not the detecting of data communication, further timing, if at the appointed time threshold value does not have
Data communication, the then work of adapter tube first singlechip, the state of normal work is switched to from spare low power consumpting state, with adapter tube
The work of first singlechip；Second storage chip module for reading and writing, for being communicated with storage chip for second singlechip, with realization pair
The read-write of storage chip；Warning note module after the work for second singlechip adapter tube first singlechip, carries out alarm and mentions
Show, to remind user to replace electronic device.
8. a kind of stand-by circuit switching method is applied in electronic device, it is characterised in that: any including such as claim 1 to 5
The storage chip common circuit, the first singlechip are main control singlechip, and the second singlechip is spare single-chip microcontroller,
In the electronic device, stand-by circuit is constituted based on second singlechip, which comprises
The first singlechip is communicated by iic bus with storage chip, to realize the read-write to storage chip；
The first singlechip periodically sends heartbeat packet on iic bus；
Whether there is data communication on the second monolithic detecting iic bus.
9. stand-by circuit switching method according to claim 8, it is characterised in that: second singlechip is according to there is no data
The detecting of communication, further timing, if at the appointed time threshold value does not have a data communication, the work of adapter tube first singlechip,
It is switched to the state of normal work, from spare low power consumpting state with the work of adapter tube first singlechip；
Second singlechip is communicated with storage chip, is written and read to storage chip；
After the work of second singlechip adapter tube first singlechip, warning note is carried out, to remind user to replace electronic device.
10. stand-by circuit switching method according to claim 8, it is characterised in that: the second singlechip judges that IIC is total
Whether having IIC data communication on line is to judge whether low level occur on the port SDA or the port SCL；If there is low level, then
Show there is data communication on iic bus.
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| CN111047736A (en) * | 2019-12-30 | 2020-04-21 | 潍柴动力股份有限公司 | Data storage device, method, electronic control unit and automobile |
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