CN109285775A - 一种雪崩整流二极管的制作工艺 - Google Patents

一种雪崩整流二极管的制作工艺 Download PDF

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CN109285775A
CN109285775A CN201811066649.8A CN201811066649A CN109285775A CN 109285775 A CN109285775 A CN 109285775A CN 201811066649 A CN201811066649 A CN 201811066649A CN 109285775 A CN109285775 A CN 109285775A
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avalanche
rectifier diode
manufacture craft
chip
diode according
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曹孙根
王志忠
张俊超
芮正果
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Anhui Juxin Semiconductor Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2225—Diffusion sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66098—Breakdown diodes
    • H01L29/66113—Avalanche diodes

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Abstract

本发明提供一种雪崩整流二极管的制作工艺，采用电解法去除硅片扩散后在其表面形成的磷硅、硼硅玻璃，电解液采用ZnSO4溶液，直流源阳极连接一根钼棒，直流源阴极连接一根铜棒，芯片P面朝上放置于电解液中，P面接触钼棒底部；电解反应结束后，将芯片取出浸入HF溶液浸泡10‑15分钟后，用清水冲洗干净。电解法去除磷硅、硼硅玻璃，彻底避免吹砂工艺而造成的巨大应力，提高了雪崩二极管的雪崩能力。

Description

一种雪崩整流二极管的制作工艺
技术领域
本发明涉及一种功率半导体分立器件，尤其是一种雪崩整流二极管的制作工艺。
背景技术
现代功率器件不仅需要二极管的整流、滤波、续流、吸收功能，有时还需要它的过压保护、过流保护功能，这就要利用到整流二极管具有的雪崩能力。即使整流、吸收、续流也往往需要雪崩能力，这就是必须开发雪崩整流二极管的必要性。最初表征二极管的雪崩能力，是在高温下，通过示波器看其是否硬转折。高温下硬转折，说明雪崩特性好，但仅此还不能说其就是雪崩二极管。
1954年硅整流二极管诞生，然而直到上世纪八十年代末，欧洲才正式诞生雪崩二极管，中间经过了漫长的三十多年。上世纪七十年代，我国台湾地区率先采用DVR、△VF，甚至包括后面出现的IPPM值测试，把整流二极管的性能提高到一个很高的水平，但还不能称之为雪崩二极管，只能叫做STD二极管。以雪崩功率PRSM为标志参数的二极管才是真正的雪崩二极管，它的主要代表为EUPEC（即infineon）、ABB、ixys生产的欧洲雪崩二极管。
国内的高雪崩能力[PRSM=（1-200）kw]二极管，几乎都是从infineon、ABB、ixys进口，其中PRSM=（1-20）kw的二极管，即为方片中小功率雪崩二极管。
影响二极管雪崩能力大小的使其应力大小，其应力的主要来源有：第一，高温过程中的掺杂和形变，晶片内部会产生晶格热缺失；第二，将石英砂高速喷射到晶片表面，以去除扩散后的磷硅、硼硅玻璃，石英砂高速撞击硅片，在硅片表面形成高温下的机械损伤，往往导致基区少子寿命极大降低，使得二极管几乎完全丧失雪崩能力。
发明内容
针对上述问题，本发明提供一种雪崩整流二极管的制作工艺，采用电解法去除硅片扩散后在其表面形成的磷硅、硼硅玻璃，电解液采用ZnSO4溶液，直流源阳极连接一根钼棒，直流源阴极连接一根铜棒，芯片P面朝上放置于电解液中，P面接触钼棒底部；电解反应结束后，将芯片取出浸入HF溶液浸泡10-15分钟后，用清水冲洗干净。
优选的，单晶材料采用电阻率为0.02-100Ω·cm、截面电阻率均匀性不超过20％的N型100晶向低阻单晶硅片。
优选的，硅片双面采用磷型纸源和硼型纸源同时进行扩散；扩散过程中，纸源燃烧时会导致晶片之间产生不均匀的空隙，此时施加一个外力（此外力可以为弹簧力），及时将晶片空隙填补压平并牢牢结合成一个整体，保证晶片在整个扩散过程中高度平整不形变；扩散后，构成PIN二极管非穿通基本结构，雪崩二级管发生雪崩的条件必须是先体内雪崩，再表面雪崩，体内，应有雪崩基本结构，穿通肯定不行，基区太宽也不行，应控制基区宽度是空间电荷区宽度的1.1-1.15倍。
优选的，PN结边缘的阳极P+区至衬底N区三分之二处设有弧形沟槽，使得边缘PN结形成65°～85°的正斜角度，使得雪崩整流二极管有较大的反向电压。
依照本发明制成的雪崩整流二极管的芯片边长为1-20mm，雪崩耗散功率为1-40KW，基区少子寿命为8-100μs，可以采用专用的雪崩功率测试仪直接测试其PRSM。
本发明的有益效果：1.采用N型100晶向低阻单晶硅片，相比111晶向单晶硅片，电流扩展速度提高了10-15%，雪崩耗散功率提高了10%以上；2.纸源一次全扩散，避免多次扩散工艺造成的应力过大的弊病；3.扩散过程中，施加外力压紧，保证晶片在整个扩散过程中高度平整不形变；4.电解法去除磷硅、硼硅玻璃，彻底避免吹砂工艺而造成的巨大应力；5.PN结边缘弧形沟槽的设置和65°～85°的正斜角度，使得雪崩整流二极管有较大的反向电压。
附图说明
图1为PIN二极管非穿通基本结构示意图；
图2为PN结边缘形状示意图；
图3为电解法去除硼硅/磷硅玻璃的示意图。
具体实施方式
下面结合附图对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
一种雪崩整流二极管的制作工艺，单晶材料选取厚度为250μm、电阻率为20Ω·cm的单晶硅片。
硅片双面采用磷型纸源和硼型纸源同时进行扩散；扩散过程中，纸源燃烧时会导致晶片之间产生不均匀的空隙，此时施加一个外力（此外力可以为弹簧力），及时将晶片空隙填补压平并牢牢结合成一个整体，保证晶片在整个扩散过程中高度平整不形变；扩散后，构成PIN二极管非穿通基本结构，如图1所示，雪崩二级管发生雪崩的条件必须是先体内雪崩，再表面雪崩，体内，应有雪崩基本结构，穿通肯定不行，基区太宽也不行，应控制基区宽度是空间电荷区宽度的1.1-1.15倍；PN结边缘的阳极P+区至衬底N区三分之二处设有弧形沟槽，使得边缘PN结形成65°～85°的正斜角度，如图2所示，使得雪崩整流二极管有较大的反向电压。
采用电解法去除硅片扩散后在其表面形成的磷硅、硼硅玻璃，电解液采用ZnSO4溶液，直流源阳极连接一根钼棒，直流源阴极连接一根铜棒，芯片P面朝上放置于电解液中，P面接触钼棒底部，如图3所示；电解反应结束后，将芯片取出浸入HF溶液浸泡10-15分钟后，用清水冲洗干净。
最终制成边长为1.3mm的正方形二极管，测其电性如下表1。
表1
实施例2
单晶材料选取厚度为310μm、电阻率为30Ω·cm的单晶硅片，其他工艺与实施例1一致，制成边长为3mm的正方形二极管，测其电性如下表2。
表2
最后，还需要注意的是，以上列举仅是本发明一个具体实施例。显然，本发明不限于以上实施例，还可以有许多变形。本领域的普通技术人员能从本发明公开的内容直接导出或联想到的所有变形，均应认为是本发明的保护范围。

Claims (6)

1.一种雪崩整流二极管的制作工艺，其特征在于，采用电解法去除硅片扩散后在其表面形成的磷硅、硼硅玻璃，电解液采用ZnSO4溶液，直流源阳极连接一根钼棒，直流源阴极连接一根铜棒，芯片P面朝上放置于电解液中，P面接触钼棒底部；电解反应结束后，将芯片取出浸入HF溶液浸泡10-15分钟后，用清水冲洗干净。
2.根据权利要求1所述的雪崩整流二极管的制作工艺，其特征在于，单晶材料采用电阻率为0.02-100Ω·cm、截面电阻率均匀性不超过20％的N型100晶向低阻单晶硅片。
3.根据权利要求1或2所述的雪崩整流二极管的制作工艺，其特征在于，硅片双面采用磷型纸源和硼型纸源同时进行扩散。
4.根据权利要求3所述的雪崩整流二极管的制作工艺，其特征在于，扩散过程中，施加一个外力，保证晶片在整个扩散过程中高度平整不形变。
5.根据权利要求3所述的雪崩整流二极管的制作工艺，其特征在于，PN结边缘的阳极P+区至衬底N区三分之二处设有弧形沟槽，使得边缘PN结形成65°～85°的正斜角度。
6.根据权利要求3所述的雪崩整流二极管的制作工艺，其特征在于，扩散后，构成PIN二极管非穿通基本结构，基区宽度是空间电荷区宽度的1.1-1.15倍。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5930660A (en) * 1997-10-17 1999-07-27 General Semiconductor, Inc. Method for fabricating diode with improved reverse energy characteristics
CN101582455A (zh) * 2009-07-02 2009-11-18 锦州市双合电器有限公司 16000a/200～400v电焊机专用雪崩整流二极管及其制造方法
CN102243984A (zh) * 2010-05-11 2011-11-16 扬州杰利半导体有限公司 一种去除芯片上硼斑的方法
CN205428951U (zh) * 2016-03-14 2016-08-03 江苏捷捷微电子股份有限公司 一种vr大于2600v的方片式玻璃钝化二极管芯片

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5930660A (en) * 1997-10-17 1999-07-27 General Semiconductor, Inc. Method for fabricating diode with improved reverse energy characteristics
CN101582455A (zh) * 2009-07-02 2009-11-18 锦州市双合电器有限公司 16000a/200～400v电焊机专用雪崩整流二极管及其制造方法
CN102243984A (zh) * 2010-05-11 2011-11-16 扬州杰利半导体有限公司 一种去除芯片上硼斑的方法
CN205428951U (zh) * 2016-03-14 2016-08-03 江苏捷捷微电子股份有限公司 一种vr大于2600v的方片式玻璃钝化二极管芯片

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