CN109256421A - A kind of bipolar device and preparation method thereof of high early voltage - Google Patents
A kind of bipolar device and preparation method thereof of high early voltage Download PDFInfo
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Abstract
The invention discloses a kind of bipolar device and preparation method thereof of high early voltage, the bipolar device includes 3 metal connecting lines and substrate；Substrate is sequentially arranged above N buried layer, the first epitaxial layer, the second epitaxial layer and SiO2Layer；3 metal connecting lines are each passed through SiO2After the fairlead being arranged on layer, it is separately connected draw-out area, emitter region and the p-type base area of collecting zone；The draw-out area and p-type base area of collecting zone are located inside the second epitaxial layer, and emitter region is located inside p-type base area；Bipolar device two sides are respectively provided with p-type isolated area.The method mainly improves be to include carrying out first time epitaxy technique to substrate, forms the first epitaxial layer；Second of epitaxy technique is carried out on the first epitaxial layer, forms the second epitaxial layer；It by the design of double epitaxial layers, can effectively increase Early voltage, reduce Early effect, improve the precision of integrated circuit；Meanwhile parasitic PMOS tube threshold voltage increases, the metal line of circuit is more convenient, and operating voltage range expands.
Description
Technical Field
The invention belongs to the field of performance improvement of semiconductor devices, and relates to a bipolar device with high early voltage and a manufacturing method thereof.
Background
NPN transistors are a type of transistor structure often used in bipolar integrated circuits, which, in conventional bipolar integrated circuit production, depositing an N-type epitaxial layer with expected resistivity and thickness on a P-type substrate, forming a P-type impurity doped base region by adopting an ion implantation or diffusion process, forming an emitter region doped with N-type impurities and a lead-out region of the collector region on the base region and the epitaxial layer by ion implantation or diffusion process, namely, selective P-type impurity doping is carried out on the N-type epitaxial layer to form a base region, selective N-type impurity doping is carried out on the P-type base region to form an emitter region, meanwhile, selective N-type impurity doping is carried out on the epitaxial layer to form a leading-out region of the collector region, an NPN transistor structure is finally realized through a lead, the surface of the transistor is covered with a silicon dioxide layer which is used as an insulating layer between the metal lead and the doping area of the NPN transistor, so that short circuit between different doping areas of the transistor through a metal connecting wire is avoided. The NPN transistor is formed in the epitaxial layer, and the base region width is determined by the difference between the diffusion junction depth of the P-type impurity and the diffusion junction depth of the N-type impurity, so that the traditional NPN transistor belongs to a longitudinal device.
The traditional NPN transistor has low early voltage and obvious early effect, influences the precision of a circuit in an integrated circuit with higher requirements, such as when the traditional NPN transistor is used for a reference source, and the output fluctuation amplitude of the reference source is increased due to the influence of the early effect. For an NPN transistor circuit with higher working voltage, the parasitic PMOS threshold voltage is lower due to lower impurity concentration on the surface of the epitaxial layer, and the lower limits of metal wiring and working voltage of the circuit are influenced.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned disadvantages of the prior art and providing a high early voltage bipolar device and a method of making the same.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
a bipolar device with high early voltage comprises 3 metal connecting wires and a substrate; an N buried layer, a first epitaxial layer, a second epitaxial layer and SiO are sequentially arranged above the substrate2A layer; 3 metal connecting wires respectively penetrate through SiO2The extraction region, the emission region and the P-type base region of the collector region are respectively connected after the extraction holes arranged on the layers; a leading-out region and a P-type base region of the collector region are positioned in the second epitaxial layer, and an emitter region is positioned in the P-type base region; p-type isolation regions are arranged on two sides of the bipolar device.
The invention further improves the following steps:
the impurity concentrations of the first epitaxial layer and the second epitaxial layer are both determined by formula (1):
wherein N isCIs the impurity concentration of the epitaxial layer, BVCBOIs the breakdown voltage between the extraction region of the collector region and the P-type base region, BVCEOThe breakdown voltage between the collector and emitter regions is β, which is the magnification factor.
The thickness of the first epitaxial layer is determined by equation (2):
W＞Xm＝(2ε0εsBVCBO/qNC)1/2(2)
where W is the thickness of the first epitaxial layer and X m is the space charge region width, ε0Is a vacuum dielectric constant of ∈sIs the dielectric constant of silicon material, and q is the electron electric quantity.
The thickness of the second epitaxial layer is 2-4 mu m.
The first epitaxial layer and the second epitaxial layer are both N-type epitaxial layers.
The junction depth of the extraction region of the collector region is 1/2 of the P-type base region.
The substrate is a silicon wafer.
A method for manufacturing a bipolar device with high early voltage comprises the following steps:
step 1: oxidizing the substrate, forming an oxide layer on the surface of the substrate, and forming an N-buried region and a P-buried region on the substrate through photoetching, ion implantation and diffusion processes;
step 2: carrying out a first epitaxial process on the substrate to form a first epitaxial layer;
and step 3: performing a second epitaxial process on the first epitaxial layer to form a second epitaxial layer;
and 4, step 4: carrying out PN junction isolation on the first epitaxial layer, the second epitaxial layer and the substrate to form P-type isolation regions, and carrying out oxidation, base region photoetching, ion implantation and diffusion processes on the second epitaxial layer among the formed P-type isolation regions to form P-type base regions;
and 5: respectively carrying out photoetching, ion implantation and diffusion processes in the second epitaxial layer and the P-type base region to respectively form a leading-out region and an emitter region of the collector region;
step 6: oxidizing the second epitaxial layer to form SiO2Layer of p-SiO2Etching holes on the layer, and forming leading-out holes at the contact parts of a leading-out region of the collector region, the emitter region and the P-type base region; the entire bipolar device is then subjected to metallization, alloying and passivation processes.
Compared with the prior art, the invention has the following beneficial effects:
the invention arranges a first epitaxial layer and a second epitaxial layer; the resistivity of the first epitaxial layer is high and thick, the thickness and the impurity concentration of the first epitaxial layer are determined according to the working voltage of a product, and the resistivity is further determined according to the impurity concentration; the second epitaxial layer is low in resistivity and thin in thickness, and the thickness of the second epitaxial layer is determined according to the junction depth of the base region of the product. Through the design of the double epitaxial layers, the longitudinal NPN transistor structure can effectively increase the early voltage, reduce the early effect and simultaneously improve the threshold voltage. For a 50V high-precision high-voltage bipolar integrated circuit, a traditional NPN transistor and the NPN transistor with a double-layer epitaxial structure are respectively adopted, and a test comparison result is shown in Table 1, so that the problem that the traditional NPN transistor has low early voltage, so that the precision of the circuit is influenced in an integrated circuit with higher demand is effectively solved, and when the circuit is used for a reference source, the output fluctuation amplitude of the reference source is increased due to the influence of the early effect; meanwhile, the problem that the lower limit of metal wiring and working voltage of a circuit is influenced by the fact that the threshold voltage of a parasitic PMOS (P-channel metal oxide semiconductor) transistor is lower due to the fact that the impurity concentration of the surface of an epitaxial layer of the traditional NPN transistor is lower is solved.
TABLE 1 comparison of parameters for NPN tubes of different configurations
According to the invention, two epitaxial layers with different thicknesses and resistivities are formed by two epitaxial processes, and the early voltage of the longitudinal NPN transistor obtained by the method is effectively improved, and the early effect is reduced; meanwhile, the method increases the impurity concentration on the surface of the epitaxial layer, so that the threshold voltage of the parasitic PMOS tube is increased, the metal wiring of the circuit is more convenient, and meanwhile, the range of the working voltage is enlarged, and the use requirement is met.
Drawings
FIG. 1 is a diagram of the early effect and early voltage of the present invention;
FIG. 2 is a schematic top view of a vertical NPN transistor;
FIG. 3 is a schematic top view of a parasitic PMOS transistor;
FIG. 4 is a schematic diagram of a conventional vertical NPN transistor in a vertical cross-section;
FIG. 5 is a schematic diagram of a longitudinal cross-sectional structure of an NPN transistor according to the present invention;
FIG. 6 is a schematic diagram of a conventional parasitic PMOS transistor with a longitudinal cross-sectional structure;
FIG. 7 is a schematic diagram of a longitudinal cross-sectional structure of a parasitic PMOS transistor according to the present invention.
Wherein: a 1-N buried layer; 2-a lead-out region of the collector region; 3-an emission area; 4-P type base region; 5-metal connecting wire; 6-a substrate; 7-a first epitaxial layer; 8-a second epitaxial layer; 9-SiO2A layer; 10-P type isolation regions.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the accompanying drawings:
referring to fig. 1, the early effect of an NPN transistor is: when the collector-emitter voltage of the bipolar transistor changes, the depletion width between the base and the collector also changes, resulting in a change in the base width, causing the NPN transistor Ic to increase with a change in Vce. This change is called the early effect. Extending the collector current to the left, and VCEIntersection V obtained by intersecting axesAReferred to as early voltage.
The relation between the space charge region and the concentrations of the base region and the collector region is as follows:
W∝((NB+NC)*Vbi/NBNC)1/2
wherein W is the space charge region width between the collector region and the base region, NBAnd NCCarrier concentration, V, of base and collector regions, respectivelybiThe self-built potential of the PN junction between the base region and the collector region.
The carrier concentration of the collector region is reduced to be far smaller than that of the base region, the width of a depletion region of a junction between the base region and the collector region is basically within the collector region, the influence of external voltage change on the width change of the base region is reduced, and accordingly early voltage is improved.
Under the condition of ensuring higher breakdown voltage, in order to increase the early voltage and reduce the early effect, the carrier concentration of a collector region needs to be reduced, and the resistivity of an epitaxial layer needs to be increased.
As the resistivity of the epitaxial layer increases, the field threshold voltage of the parasitic PNP transistor decreases, affecting the reliability of the integrated circuit. For field threshold voltage VTDoping concentration N with epitaxial layerepiProportional ratio, as shown in the following formula:
VT∝(Nepi)1/2
NPN transistor collection in integrated circuit manufacturing processThe zone process is in an epitaxial layer, and the doping concentration of the epitaxial layer is the carrier concentration of a collector zone, namely Nepi＝Nc. The higher the surface concentration of the epitaxial layer is, the larger the threshold voltage of the parasitic PMOS tube field is. Aiming at the influence mechanism of early voltage and threshold voltage of an NPN transistor, a novel longitudinal NPN transistor with a two-step epitaxial process structure is provided.
Referring to fig. 2 and 5, the high early voltage bipolar device of the present invention comprises 3 metal lines 5 and a substrate 6; an N buried layer 1, a first epitaxial layer 7, a second epitaxial layer 8 and SiO are sequentially arranged above the substrate 62A layer 9; 3 metal connecting wires 5 respectively penetrate through SiO2The extraction region 2 of the collector region, the emitter region 3 and the P-type base region 4 are respectively connected after the extraction holes arranged on the layer 9; the leading-out region 2 and the P-type base region 4 of the collector region are positioned in the second epitaxial layer 8, and the emitter region 3 is positioned in the P-type base region 4; p-type isolation regions 10 are disposed on both sides of the bipolar device.
Wherein, the substrate 6 is a silicon chip, P <111> is adopted, and the resistivity is 8-13 omega.cm; the first epitaxial layer 7 is a high-resistance thick epitaxial layer, and the thickness and the resistivity of the epitaxial layer are determined according to the working voltage of a product; the epitaxial layer impurity concentration of the first epitaxial layer 7 is calculated from equation (1) in consideration of the abrupt junction approximation:
wherein, BVCBOIs the breakdown voltage between the collector region 2 and the P-type base region 4, BVCEOThe breakdown voltage between the collector region 2 and the emitter region 3 is β as amplification factor, NC is the impurity concentration of the epitaxial layer, N is 2-4 generally, and N is the breakdown voltageCAnd checking the resistance value of the-rho C curve.
The thickness of the first epitaxial layer 7 is calculated according to the space charge region formula, as shown in formula (2):
W＞Xm＝(2ε0εsBVCBO/qNC)1/2(2)
wherein,w is the thickness of the first epitaxial layer 7, Xm is the space charge region width, ε0Is a vacuum dielectric constant of ∈sIs the dielectric constant of the material and q is the electron volume.
The second epitaxial layer 8 is a low-resistance thin epitaxial layer, the thickness of the second epitaxial layer 8 is determined according to the junction depth of a base region designed by a product, the junction depth of the emitter region 3 is designed to be 1/2 of the P-type base region 4, and the thickness of the second epitaxial layer 8 is generally 2-4 microns; the impurity concentration of the second epitaxial layer 8 is calculated by NC-ρCThe resistance is found by curve.
Referring to fig. 4, the conventional vertical NPN transistor includes 3 metal wirings 5 and a substrate 6; an N buried layer 1, a first epitaxial layer 7 and SiO are arranged above the substrate 6 in sequence2A layer 9; 3 metal connecting wires 5 respectively penetrate through SiO2The extraction region 2 of the collector region, the emitter region 3 and the P-type base region 4 are respectively connected after the extraction holes arranged on the layer 9; the extraction region 2 and the P-type base region 4 of the collector region are positioned inside the first epitaxial layer 7, and the emitter region 3 is positioned inside the P-type base region 4; p-type isolation regions 10 are disposed on both sides of the bipolar device.
Referring to fig. 3 and 7, the parasitic PMOS transistor of the present invention includes a metal line 5 and a substrate 6; an N buried layer 1, a first epitaxial layer 7, a second epitaxial layer 8 and SiO are sequentially arranged above the substrate 62A layer 9; 2P-type base regions 4 are arranged in the second epitaxial layer 8; the metal connecting line 5 is positioned on SiO2SiO in contact with 2P-type base regions 4 over layer 9 and metal line 52Portions 2 of layer 9 are joined together; the two sides of the parasitic PMOS tube are provided with P-type isolation regions 10.
Referring to fig. 6, the conventional parasitic PMOS transistor includes a metal line 5 and a substrate 6; an N buried layer 1, a first epitaxial layer 7 and SiO are arranged above the substrate 6 in sequence2A layer 9; 2P-type base regions 4 are arranged at the upper part of the first epitaxial layer 7; the metal connecting line 5 is positioned on SiO2SiO in contact with 2P-type base regions 4 over layer 9 and metal line 52The two parts of the layer 9 are joined together; the two sides of the parasitic PMOS tube are provided with P-type isolation regions 10.
The invention relates to a manufacturing method of a bipolar device with high early voltage, which comprises the following steps:
step 1: oxidizing the substrate 6, forming an oxide layer on the surface of the substrate 6, and forming an N-buried region and a P-buried region on the substrate 6 through photoetching, ion implantation and diffusion processes;
step 2: carrying out a first epitaxial process on the substrate 6 to form a first epitaxial layer 7;
and step 3: performing a second epitaxial process on the first epitaxial layer 7 to form a second epitaxial layer 8;
and 4, step 4: carrying out PN junction isolation on the first epitaxial layer 7, the second epitaxial layer 8 and the substrate to form a P-type isolation region 10, and carrying out oxidation, base region photoetching, ion implantation and diffusion processes on the second epitaxial layer 8 in the formed P-type isolation region 10 to form a P-type base region 4;
and 5: respectively carrying out photoetching, ion implantation and diffusion processes in the second epitaxial layer 8 and the P-type base region 4 to respectively form a leading-out region 2 and an emitter region 3 of the collector region;
step 6: oxidation to form SiO on the second epitaxial layer 82Layer 9, p-SiO2Etching holes on the layer 9, and forming leading-out holes at the contact parts of the leading-out region 2 of the collector region, the emitter region 3 and the P-type base region 4; the entire bipolar device is then subjected to metallization, alloying and passivation processes resulting in a high early voltage bipolar device as shown in figure 5.
Example 1
By adopting the novel longitudinal NPN transistor and applying the OP77 bipolar integrated circuit, the adopted double-layer epitaxy result is as follows:
1) the first epitaxial layer process is designed as follows: the thickness is 15 μm, and the resistivity is 6.0 omega cm;
2) the second epitaxial layer process is designed as follows: the thickness was 2 μm, and the resistivity was 3.2. omega. cm.
This structure result of use:
the voltage gain of the product is increased from 130db to 135db, and the use requirement is met.
Example 2
For a 50V high-precision high-voltage bipolar integrated circuit, the traditional epitaxial process conditions are as follows: the thickness is 13 μm, and the resistivity is 4 Ω · cm; the method adopts a double-layer epitaxy process, and the design of the first-layer epitaxy process is as follows: the thickness is 15 μm, 6 Ω · cm; the second layer epitaxy process is designed as follows: the thickness is 2 μm, and the resistivity is 3.2 Ω · cm;
the layout structure of the NPN tube is as follows: the base region is 26 μm × 26 μm, and the emitter region is 10 μm × 10 μm.
The parasitic PMOS under-metal dielectric structure is as follows: 600nm SiO2And 100nm of Si3N4。
Early voltage test conditions: ic 0.5mA, comparative test results are shown in Table 1.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (8)
1. A high early voltage bipolar device comprising 3 metal lines (5) and a substrate (6); an N buried layer (1), a first epitaxial layer (7), a second epitaxial layer (8) and SiO are sequentially arranged above the substrate (6)2A layer (9); 3 metal connecting wires (5) respectively penetrate through SiO2The extraction region (2) of the collector region, the emitter region (3) and the P-type base region (4) are respectively connected after the extraction holes arranged on the layer (9); a lead-out region (2) and a P-type base region (4) of the collector region are positioned in the second epitaxial layer (8), and the emitter region (3) is positioned in the P-type base region (4); p-type isolation regions (10) are arranged on two side edges of the bipolar device.
2. A high early voltage bipolar device according to claim 1, wherein the impurity concentration of said first epitaxial layer (7) and said second epitaxial layer (8) are both determined by equation (1):
wherein N isCIs the impurity concentration of the epitaxial layer, BVCBOIs the breakdown voltage between the leading-out region (2) of the collector region and the P-type base region (4), BVCEOThe breakdown voltage between the collector region (2) and the emitter region (3) is β, which is a magnification factor.
3. A high early voltage bipolar device according to claim 1, wherein the thickness of said first epitaxial layer (7) is determined by equation (2):
W＞Xm＝(2ε0εsBVCBO/qNC)1/2(2)
wherein W is the thickness of the first epitaxial layer (7), X m is the space charge zone width, ε0Is a vacuum dielectric constant of ∈sIs the dielectric constant of silicon material, and q is the electron electric quantity.
4. A high early voltage bipolar device according to claim 1, wherein the thickness of the second epitaxial layer (8) is 2-4 μm.
5. A high early voltage bipolar device according to claim 1, wherein said first epitaxial layer (7) and said second epitaxial layer (8) are both N-type epitaxial layers.
6. A high early voltage bipolar device according to claim 1, wherein the junction depth of the extraction region (2) of the collector region is 1/2 of the P-type base region (4).
7. A high early voltage bipolar device according to claim 1, wherein said substrate (6) is a silicon wafer.
8. A method for fabricating a bipolar device according to any one of claims 1 to 7, comprising the steps of:
step 1: oxidizing the substrate (6), forming an oxide layer on the surface of the substrate (6), and forming an N-buried region and a P-buried region on the substrate (6) through photoetching, ion implantation and diffusion processes;
step 2: carrying out a first epitaxial process on the substrate (6) to form a first epitaxial layer (7);
and step 3: carrying out a second epitaxial process on the first epitaxial layer (7) to form a second epitaxial layer (8);
and 4, step 4: carrying out PN junction isolation on the first epitaxial layer (7), the second epitaxial layer (8) and the substrate to form a P-type isolation region (10), and carrying out oxidation, base region photoetching, ion implantation and diffusion processes on the second epitaxial layer (8) between the formed P-type isolation regions (10) to form a P-type base region (4);
and 5: photoetching, ion implantation and diffusion processes are respectively carried out in the second epitaxial layer (8) and the P-type base region (4) to respectively form a leading-out region (2) and an emitter region (3) of the collector region;
step 6: oxidizing the second epitaxial layer (8) to form SiO2Layer (9) of SiO2Etching holes in the layer (9), and forming leading-out holes at the contact positions of the leading-out region (2) of the collector region, the emitter region (3) and the P-type base region (4); the entire bipolar device is then subjected to metallization, alloying and passivation processes.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111519245A (en) * | 2020-04-29 | 2020-08-11 | 西安微电子技术研究所 | Silicon substrate epitaxial layer growth method based on barrel type epitaxial furnace |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60123062A (en) * | 1983-12-08 | 1985-07-01 | Matsushita Electronics Corp | Manufacture of semiconductor integrated circuit |
| JPH07183308A (en) * | 1993-12-24 | 1995-07-21 | New Japan Radio Co Ltd | Manufacture of vertical bipolar transistor |
| US6011297A (en) * | 1997-07-18 | 2000-01-04 | Advanced Micro Devices,Inc. | Use of multiple slots surrounding base region of a bipolar junction transistor to increase cumulative breakdown voltage |
| CN103077966A (en) * | 2011-10-26 | 2013-05-01 | 索尼公司 | Semiconductor device |
-
2018
- 2018-09-10 CN CN201811052415.8A patent/CN109256421B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60123062A (en) * | 1983-12-08 | 1985-07-01 | Matsushita Electronics Corp | Manufacture of semiconductor integrated circuit |
| JPH07183308A (en) * | 1993-12-24 | 1995-07-21 | New Japan Radio Co Ltd | Manufacture of vertical bipolar transistor |
| US6011297A (en) * | 1997-07-18 | 2000-01-04 | Advanced Micro Devices,Inc. | Use of multiple slots surrounding base region of a bipolar junction transistor to increase cumulative breakdown voltage |
| CN103077966A (en) * | 2011-10-26 | 2013-05-01 | 索尼公司 | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111519245A (en) * | 2020-04-29 | 2020-08-11 | 西安微电子技术研究所 | Silicon substrate epitaxial layer growth method based on barrel type epitaxial furnace |
| CN111519245B (en) * | 2020-04-29 | 2021-07-20 | 西安微电子技术研究所 | Silicon substrate epitaxial layer growth method based on barrel type epitaxial furnace |
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