CN111696911A

CN111696911A - Electronic device

Info

Publication number: CN111696911A
Application number: CN202010029159.1A
Authority: CN
Inventors: M·阿加姆; J·皮杰卡克; J·C·J·让森斯
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2019-03-13
Filing date: 2020-01-10
Publication date: 2020-09-22

Abstract

The invention provides an electronic device. The invention discloses an electronic device. The electronic device may include a substrate defining a trench. In one embodiment, a semiconductor body may be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In one embodiment, an electronic component may be within the semiconductor body. The electronic component may be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along the upper surface, and is spaced apart from a bottom of the semiconductor body. In further embodiments, the electronic device may further include a first electronic component within the active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.

Description

Electronic device

Technical Field

The present disclosure relates to electronic devices and processes of forming electronic devices, and more particularly, to electronic devices including semiconductor bodies or isolation structures within trenches and processes of forming the same.

Background

Semiconductor dies may include different components, where one component may interfere with the operation of another component. For example, the power transistor may be isolated from the logic transistor such that the electric field of the power transistor does not adversely affect the operation of the logic transistor. Deep trench isolation may be used to electrically isolate the power transistor from the logic transistor; however, deep trench isolation occupies die area for electrical isolation only. Improvements in semiconductor die and more efficient use of die area are desired.

Drawings

Embodiments are shown by way of example in the drawings and the embodiments are not limited thereto.

Fig. 1 and 2 include illustrations of top and cross-sectional views of a portion of a workpiece including a substrate and a trench extending into the substrate.

Fig. 3 and 4 include illustrations of top and cross-sectional views of the workpiece of fig. 1 and 2, including an insulating layer and a semiconductor body within a trench.

Fig. 5 and 6 include illustrations of a cross-sectional view and a top view of a portion of the workpiece of fig. 3 and 4 after forming a resistor according to one embodiment.

Fig. 7 and 8 include illustrations of a cross-sectional view and a top view of a portion of the workpiece of fig. 3 and 4 after forming a resistor according to another embodiment.

Fig. 9 and 10 include illustrations of a cross-sectional view and a top view of a portion of the workpiece of fig. 3 and 4 after forming a resistor according to yet another embodiment.

Fig. 11 includes an illustration of a top view of a portion of the workpiece of fig. 3 and 4 after forming a diode according to another embodiment.

FIG. 12 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 11 including a diode according to an embodiment.

FIG. 13 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 11 including a set of diodes, according to an embodiment.

Fig. 14 includes a depiction of a circuit schematic of a resistor comprising single crystalline semiconductor material and another resistor comprising polycrystalline semiconductor material.

Fig. 15 includes an illustration of a physical design of the circuit schematic of fig. 14 according to an embodiment.

FIG. 16 includes a depiction of a circuit schematic of a resistor that may be used in a temperature sensing circuit.

Fig. 17 includes an illustration of a physical design of the circuit schematic of fig. 16 according to an embodiment.

Fig. 18 includes a depiction of a circuit schematic of an inverter including transistors and resistors within a semiconductor body.

Fig. 19 includes an illustration of a physical design of the circuit schematic of fig. 18 according to an embodiment.

Fig. 20 includes a depiction of a circuit schematic of a bipolar transistor with its base connected to a voltage divider.

Fig. 21 includes a depiction of a circuit schematic of a junction field effect transistor with its gate connected to a voltage divider.

Fig. 22 includes a depiction of a circuit schematic of a metal-insulator-semiconductor field effect transistor and electronic components that help protect the gate of the transistor.

Fig. 23 includes an illustration of a physical design of the circuit schematic of fig. 22 in accordance with an embodiment.

Fig. 24 includes an illustration of a physical design of the circuit schematic of fig. 22 according to another embodiment.

Fig. 25 includes an illustration of a physical design of the circuit schematic of fig. 22 according to yet another embodiment.

Fig. 26 includes a depiction of a circuit schematic of a switching circuit.

Fig. 27 includes an illustration of a physical design of the circuit schematic of fig. 26 according to an embodiment.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Disclosure of Invention

The problem to be solved by the invention is to increase the component density in an electronic device comprising isolation structures.

According to an aspect of the present invention, an electronic device is provided. The electronic device may include: a substrate defining a trench; a first electronic component within a first active region of the substrate, wherein the first active region is outside the trench; an isolation structure within the trench and adjacent to the first electronic component; and a second electronic component within the isolation structure.

In one embodiment, the isolation structure comprises: a semiconductor body including at least a portion located below the second electronic component; and an insulating layer disposed along the sides and bottom of the trench and electrically isolating the semiconductor body from the substrate.

In a particular embodiment, the first active region comprises a single crystalline semiconductor material and the semiconductor body and the second electronic component comprise a polycrystalline semiconductor material.

In another embodiment, the electronic device further comprises a third electronic component within the second active region of the substrate, wherein the isolation structure is disposed between the first and third electronic components.

In a particular embodiment, the first electronic component is a power transistor or a logic transistor and the third electronic component is the other of the power transistor or the logic transistor.

In a more particular embodiment, the first electronic component is a transistor and the second electronic component is a resistor or a diode, wherein the first electronic component is coupled to the second electronic component.

In another embodiment, the first electronic component is a first resistor, the second electronic component is a second resistor, and the first and second resistors are connected in parallel.

In one particular implementation, the first resistor has a body comprising a single crystalline semiconductor material and the second resistor has a body comprising a polycrystalline semiconductor material.

In another aspect, an electronic device is provided. The electronic device may include: a substrate defining a trench; a semiconductor body within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate; and a diode within the semiconductor body, wherein the semiconductor body and the diode comprise polycrystalline semiconductor material.

In a further aspect, an electronic device is provided. The electronic device may include: a substrate comprising a single crystal semiconductor material and defining a trench having a depth of at least 5 microns; a semiconductor body within the trench, wherein the semiconductor body comprises a polycrystalline semiconductor material, has an upper surface, has a resistivity of at least 0.05 ohm-cm, and is electrically isolated from the substrate; and a first electronic component within and along the upper surface of the semiconductor body, wherein the first electronic component is spaced apart from the bottom of the semiconductor body.

The technical effect achieved by the invention allows the semiconductor body within the isolation structure to be used to form one or more electronic components within the semiconductor body.

Detailed Description

The following description, in conjunction with the drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to help describe the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other embodiments may be employed based on the teachings as disclosed in this application.

The term "deep trench isolation" is intended to mean an isolation structure having a depth of at least 5 microns. Shallow trench isolation is shallower than deep trench isolation and typically has a depth of less than 1 micron.

The term "logic transistor" is intended to mean a transistor that is in placeIn the on state, the transistor can be at the drain and source (I)_DS) Or collector and emitter (I)_CE) Flows at most 0.1 ampere and can withstand the drain and source (V) of the transistor when in the off state_DS) Or collector and emitter (V)_CE) Up to 10 volts in between.

The term "power transistor" is intended to mean a transistor that, when in an on state, may be at the drain and source (I) of the transistor_DS) Or collector and emitter (I)_CE) Flows more than 1 ampere therebetween, and can withstand the drain and source (V) of the transistor when in an off state_DS) Or collector and emitter (V)_CE) At least 30 volts in between.

The terms "comprises," "comprising," "includes," "including," "has," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. In addition, unless expressly stated to the contrary, "or" means an inclusive or, rather than an exclusive or. For example, condition a or B is satisfied by either: a is true (or present) and B is false (or not present), a is false (or not present) and B is true (or present), and both a and B are true (or present).

In addition, "a" or "an" is used to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. The description is to be construed as including one, at least one, or the singular also includes the plural and vice versa unless it is explicitly stated that the contrary is intended. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, where more than one item is described herein, a single item may be substituted for the more than one item.

The group numbers correspond to columns in the periodic table of the elements based on the IUPAC periodic table, version 28/11/2016.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. Many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronics arts, without being described herein.

The resistor or diode may be formed in a portion of the electronic device that may not otherwise be used. In one embodiment, an electronic device may include a trench isolation structure, which may include a semiconductor body within a trench. In a particular embodiment, the trench isolation structure may be a deep trench isolation structure. The resistor or diode may be within the semiconductor body and, in one embodiment, may be along an upper surface of the semiconductor body, the upper surface lying along a plane substantially parallel to the major surface of the substrate. Active regions of the substrate may be disposed along opposite sides of the trench isolation structure. One or more resistors, diodes, or resistor-diode combinations may be within the semiconductor body and coupled to one or more electronic components within either or both active regions.

In one aspect, an electronic device may include: a substrate defining a trench having a depth of at least 5 microns; a semiconductor body within the trench, wherein the semiconductor body has an upper surface and a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate; and an electronic component within and along the upper surface and spaced from the bottom of the semiconductor body.

In another aspect, an electronic device may include: a substrate defining a trench; a semiconductor body within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate; and a diode within the semiconductor body.

In further aspects, an electronic device may include: a substrate defining a trench; a first electronic component within an active region of a substrate; an isolation structure within the trench and surrounding the first electronic component; and a second electronic component within the isolation structure. These concepts will be better understood upon reading the remainder of the specification in conjunction with the drawings.

Fig. 1 and 2 include a top view and a cross-sectional view of the substrate 100 after patterning the substrate 100 to define the trenches 120. Fig. 2 is a view along section line 2-2 in fig. 1. Substrate 100 has a major surface 110 and may include: a single crystal semiconductor material, which may contain a group 14 element, such as Si or Ge; or a compound semiconductor material such as SiC, SiGe, a III-V semiconductor such as GaAs, GaN, AlGaN, InP, or the like, or a II-VI semiconductor such as CdSe, PbTe, or the like. The substrate 100 has a relatively simple construction, such as a Si wafer with a substantially uniform dopant concentration, or may have a more complex structure that may include a buried doped layer, an undoped or lightly doped epitaxial layer over a heavily doped wafer, a buried oxide layer, another suitable construction, or a combination thereof.

The trench 120 may be used for a deep trench isolation structure that separates the active region 102 from the other active region 104. For more complex substrate configurations, the trench 120 may extend to or through a buried feature, such as a buried doped region, a buried oxide layer, or the like. The depth of the trench 120 may be at least 5 microns, at least 11 microns, or at least 20 microns. The trench 120 does not extend through the entire thickness of the substrate 100. In one embodiment, the trenches 120 have a depth of at most 95 microns, at most 75 microns, or at most 50 microns. The width of the trench 120 is sufficient to provide electrical isolation between electronic components that may be at least partially formed within the substrate 100 along the major surface 110. Although there is no theoretical limit to the width of the trench 120, as the width becomes larger, more active area is lost and the area of the electronic component is limited. In one embodiment, the width of the trench is at least 0.2 microns, at least 0.3 microns, or at least 0.5 microns, and in another embodiment, the width is at most 9.5 microns, at most 4 microns, or at most 2 microns.

Fig. 3 and 4 show top and cross-sectional views of the workpiece after forming an insulating layer 220 and filling the remaining portions of the trench 120 with a semiconductor body 240 having an upper surface 242. Fig. 4 is a view along section line 4-4 in fig. 3. The insulating layer 220 may include an oxide, a nitride, or an oxynitride. The insulating layer 220 may be formed by thermally oxidizing the substrate 100 to form the insulating layer 220 or by depositing the insulating layer 220. Insulating layer 220 is deposited to a thickness sufficient to be continuous along the sidewalls and bottom of trench 120 and not so thick as to completely fill trench 120. When expressed as a percentage of the width of the trench 120, the insulating layer 220 may have a thickness in the range of 0.2% to 20% of the width of the trench 120. In one embodiment, the insulating layer has a thickness of at least 20nm, at least 50nm, or at least 110nm, and in another embodiment, a thickness of at most 900nm, at most 500nm, or at most 200 nm.

The semiconductor body 240 may help reduce stress when the workpiece is processed by one or more high temperature operations (e.g., greater than 600℃.) in one embodiment, the semiconductor body 240 and the substrate 100 may comprise the same material, such as Si, such that the semiconductor body 240 and the substrate 100 have approximately the same coefficient of thermal expansion. As initially formed (prior to the selective doping operation), in one embodiment, the semiconductor body 240 has a high resistivity of at least 0.05 ohm-cm, at least 2 ohm-cm, or at least 20 ohm-cm. in another embodiment, the semiconductor body 240 has a resistivity of at most 100 milliohm-cm. in terms of dopant concentration, the semiconductor body 240 may be deposited as an undoped semiconductor layer. in another embodiment, the semiconductor body 240 may be n-type or p-type and have a resistivity of at most 1 × 10¹⁷Atom/cm³At most 1 × 10¹⁵Atom/cm³Or at most 1 × 10¹⁴Atom/cm³The dopant concentration of (c). The dopant concentration of the initially formed semiconductor body 240, whether undoped or doped, is referred to herein as the background dopant concentration.

After forming the insulating layer 220 and depositing a layer of semiconductor material for the semiconductor body 240, the insulating layer 220 and portions of the semiconductor material outside the trench 120 are removed. Isolation structure 200 is within trench 120, and in one embodiment, isolation structure 200 is a deep isolation structure. An insulating layer 220 is disposed between the semiconductor body 240 and the sidewalls and bottom of the trench 120. The insulating layer 220 electrically isolates the semiconductor body 240 from the substrate 100. In the illustrated embodiment, the active region 102 of the substrate 100 is laterally surrounded by an isolation structure 200, and another active region 104 is disposed along an opposite side of the isolation structure 200. As will be described later in this specification, electronic components may be formed within the

active regions

102 and 104 and the semiconductor body 240.

Exemplary electronic components that may be formed within the semiconductor body 240 may include at least one resistor, at least one diode, or a combination thereof. Thus, a more efficient use of space that would otherwise not be used can be achieved. The electronic components are disposed along or near the upper surface of the semiconductor body 240. In one embodiment, the current flowing through the electronic component may flow primarily in a direction substantially parallel to the upper surface 242 of the semiconductor body 240. The formation of electronic components can be integrated into the process flow without adding any additional masking operations or other processing steps. No complex vertical structures are required which may involve additional processing steps.

Fig. 5 and 6 illustrate a cross-sectional view and a top view of a resistor 500 that may be formed from a semiconductor body 240, in this embodiment, the resistor 500 is within the semiconductor body 240. the resistor 500 may be formed from a single doped region 522 having a dopant concentration higher than the dopant concentration of the semiconductor body 240. the resistance of the resistor 500 may be determined by the dopant concentration of the doped region 522, the distance between contacts to the doped region 522, and the width of the semiconductor body 520 (from the top view)¹⁸Atom/cm³To 5 × 10²¹Atom/cm³Within the range of (1). The depth of doped region 522 may be in the range of 0.02 microns to 0.5 microns. This depth may correspond to the pn junction depth of the doped region 522 or when the semiconductor body is a semiconductor body240 are undoped or have the same conductivity type as the doped regions 522, the dopant concentration of the doped regions 522 is at least 10% higher than the background dopant concentration of the semiconductor body 240.

A salicide block layer 620 is formed over the workpiece and an opening is formed where contact is to be made to the doped region 522. The salicide block layer 620 may include one or more films of oxide, nitride, or oxynitride. The thickness of the salicide block layer 620 may be in the range of 10nm to 200 nm. Salicide features 642 and 644 can be formed over the doped region 522. The

salicide components

642 and 644 may comprise TiSi₂、TaSi₂、CoSi₂、PtSi₂And the like. The

salicide members

642 and 644 may have a thickness in the range of 10nm to 200 nm.

An insulating layer 650 may be formed over the workpiece and patterned to define contact openings. The insulating layer 650 may include one or more films of oxide, nitride, or oxynitride. The thickness of the insulating layer 650 may be in the range of 0.1 to 5 micrometers.

Interconnects

662 and 664 are formed within the contact openings and over the doped regions 522. In one embodiment, the

interconnects

662 and 664 may include a bulk conductive film mainly containing Al or Cu. When the conductive layer comprises multiple films, an adhesion film or barrier film may be deposited prior to the bulk conductive film. The anti-reflection film may be formed over the body conductive film and may include a metal nitride film. The conductive layer may have a thickness in a range of 0.5 to 3 microns. The conductive layer may be patterned to form

interconnects

662 and 664. In another embodiment, the

salicide members

642 and 644 may be part of the

interconnects

662 and 664. In further embodiments, the

salicide members

642 and 644 may not be formed, and the

interconnects

662 and 664 may directly contact the doped region 522. In one embodiment, the formation of the salicide block layer 620, the

salicide members

642 and 644, the insulating layer 650, and the

interconnects

662 and 664 may be integrated with corresponding structures that form other electronic components within one or more active regions of the substrate 100.

In fig. 6 and other top views described later in this specification, the salicide block layer 620 and the insulating layer 650 are not shown to better illustrate the positional relationship between the different portions of the electronic device. In practice, the salicide block layer 620 covers the semiconductor body 240 and at least a portion of the

active regions

102 and 104 where salicide features will not be formed. The insulating layer 650 overlies all of the workpiece except for portions of the contact openings and scribe lanes.

Fig. 7 and 8 show a cross-sectional view and a top view of a resistor 700 that may be formed within a semiconductor body 240, the resistor 700 being similar to the resistor 500, except that the resistor 700 includes a well region 702 and doped

regions

722 and 724. the well region 702 may allow more control over the resistance of the resistor 700 than the resistor 500 depending on the dopant concentration of the doped regions 522. accordingly, the well region 702 allows the resistor 700 to achieve a resistance that is not possible for the resistor 500 due to the dopant concentration of the doped regions 522 and the physical constraints of the resistor 500. the well region 702 may have an n-type or p-type conductivity type¹⁷Atom/cm³At most 1 × 10¹⁶Atom/cm³Or at most 1 × 10¹⁵Atom/cm³In one embodiment, the dopant concentration is at least 1 × 10¹³Atom/cm³When the resistor 700 has a relatively low resistance, the dopant concentration may be at least 2 × 10¹⁷Atom/cm³At least 1 × 10¹⁸Atom/cm³Or at least 1 × 10¹⁹Atom/cm³. Well region 702 may have the same or a greater depth than

doped regions

722 and 724. In one embodiment, the depth of well region 702 is less than half the depth of trench 120, and typically less than one-quarter the depth of trench 120. In one embodiment, the depth of well region 702 is at least 0.02 microns, at least 0.3 microns, or at least 0.5 microns, and in another embodiment, well region 702 has a depth of at most 9 microns, at most 6 microns, or at most 3 microns.

Doped regions

722 and 724 may beTo have any of the dopant concentrations and depths as previously described with respect to doped region 522. Well region 702 may have a dopant concentration that is less than the dopant concentration of

doped regions

722 and 724.

The timing of the formation of the well region 702 may depend on the desired dopant concentration and depth of the well region 702. Well region 702 can be formed without adding an additional masking operation or another processing step. When the well region 702 is to have a relatively low dopant concentration and a relatively deep depth, the well region 702 may be formed simultaneously with an n-well or p-well of the body, drift, or base regions of the transistor formed within the active region of the substrate. When the well region 702 is to have a relatively low dopant concentration and a relatively shallow depth, the well region 702 may be formed simultaneously with enhancement or depletion regions of channel regions of transistors formed within the active region 102 of the substrate 100. When the well region 702 is to have a relatively high dopant concentration and a relatively shallow depth, the well region 702 may be formed simultaneously with Lightly Doped Drain (LDD) regions of transistors formed in the

active regions

102 or 104 of the substrate 100. The timing of the formation of

doped regions

722 and 724 can be any of the timings described with respect to the formation of doped region 522.

Fig. 9 and 10 show cross-sectional and top views of a resistor 900 that may be formed from semiconductor body 240. In this embodiment, the resistor 900 is within the semiconductor body 240. The dopant concentration of each of the doped

regions

722 and 724 is higher than the dopant concentration of the semiconductor body 240. A portion of semiconductor body 240 is disposed between

doped regions

722 and 724. In contrast to the embodiment shown in fig. 7 and 8 having well regions 702, the embodiment shown in fig. 9 and 10 does not include well regions or other doped regions between

doped regions

722 and 724. The resistance of the resistor 900 may be determined by the dopant concentration of the semiconductor body 240, the distance between the

doped regions

722 and 724 and the depth of the doped

regions

722 and 724, as well as the width and depth of the semiconductor body 240 (from a top view). In the embodiment shown, at least 50% of the current flowing through resistor 900 is at a depth up to the depth of

doped regions

722 and 724. Significantly less than 50% of the current through resistor 900 flows at a depth of greater than 1 micron below the depth of

doped regions

722 and 724 within semiconductor body 240.

In other embodiments, one or more diodes may be formed within the semiconductor body 240. Fig. 11-13 show top and cross-sectional views of a diode 1120 and a set of diodes 1130 that may be formed within semiconductor body 240. The illustrations in fig. 11-13 include exemplary layouts that are not meant to limit the scope of the invention as defined in the appended claims. Referring to fig. 11, the semiconductor body 240 includes a left side section 1142, a top section 1144, a right side section 1146, and a bottom section 1148. The semiconductor body 240 may include only the diode 1120 or the set of diodes 1130, but not both, or may include more than one of the diode 1120 or the set of diodes 1130. Furthermore, the diode 1120 and the set of diodes 1130 may be located within the same section of the semiconductor body 240, adjacent sections of the semiconductor body 240 or opposite sections of the semiconductor body 240 (as shown in fig. 11).

Fig. 12 includes a cross-sectional view of diode 1120 taken along section line 12-12 in fig. 11. The structure of diode 1120 includes doped

regions

1222, 1224, and 1226. The

doped regions

1222 and 1226 have a relatively high dopant concentration that forms ohmic contacts to the

salicide members

1242 and 1246 or interconnects 1262 and 1266 (if the

optional salicide members

1242 and 1246 are not present). Doped regions 1224 have a relatively lower dopant concentration than

doped regions

1222 and 1226. The breakdown voltage of diode 1120 may be determined by the dopant concentration of doped region 1224, and to a lesser extent, the dopant concentration of the doped region has an opposite conductivity type than doped region 1224. In one embodiment, doped region 1222 may be N⁺Region, doped region 1224 may be N^-The doped region 1226 may be P⁺And (4) a zone. Thus, the breakdown voltage of the diode is determined by the dopant concentration of doped region 1224 and to a lesser extent by the dopant concentration of doped region 1226. If the doped region 1224 is P^-Region, breakdown voltage is determined by the dopant concentration of doped region 1224 and to a lesser extent by the dopant concentration of doped region 1222.

As shown, doped

regions

1222, 1224, and 1226 have substantially the same depth. In the practice of the method, the first and second,any two or all of

doped regions

1222, 1224, and 1226 may have different depths. For example, the doped region 1222 may be doped with N⁺The source, drain, or emitter region is formed simultaneously, and the doped region 1226 may be formed with P⁺The source, drain or emitter regions are formed simultaneously. In another embodiment, doped regions 1224 may be aligned with well or base regions, N^-LDD regions, enhancement regions or depletion regions of the channel region are formed simultaneously. Accordingly, the depth of the doped region 1224 may vary based in part on its formation with another doped region in the active area of the substrate 100. In another embodiment, doped regions 1224 may not be used. The semiconductor body 240 may be located between the

doped regions

1222 and 1226. When the semiconductor body 240 is undoped, a P-intrinsic-N (PIN) diode may be formed.

In another embodiment, schottky diodes may be formed in place of or in conjunction with diodes 1120 either of

doped regions

1222 or 1226 may be removed and doped regions 1224 directly contact the salicide member or interconnect (if the salicide member is not present.) in one embodiment, doped regions 1226 are removed and doped regions 1224 are extended to contact the salicide member 1246. in one embodiment,

doped regions

1222 and 1224 have the same conductivity type¹⁹Ohm/cm³) To form an ohmic contact with the metal in the salicide member 1242 and the dopant concentration of the doped regions 1224 is insufficient to form an ohmic contact with the metal in the salicide member 1246. In this embodiment, a schottky diode is formed at the interface of the salicide member 1246 and the doped region 1224. In another embodiment, a pn diode and a schottky diode may be formed. The doped region 1222 is removed and the doped region 1224 is extended to contact the salicide member 1242.

Doped regions

1224 and 1226 have opposite conductivity types, and thus, a pn diode is formed at the pn junction between

doped regions

1224 and 1226. Similar to the previous embodiments, the dopant concentration of the doped regions 1224 is insufficient to form an ohmic contact with the salicide member 1242 and the doping is such thatThe dopant concentration of region 1226 is sufficiently high (e.g., at least 1 × 10)¹⁹Ohm/cm³) Sufficient to form an ohmic contact with the salicide member 1246. In this embodiment, a schottky diode is formed at the interface of the salicide member 1242 and the doped region 1224. In further embodiments, there is no salicide member present, and the metal within

interconnects

1262 and 1266 forms a schottky or ohmic contact, just like

salicide members

1242 and 1246.

Figure 13 includes a cross-sectional view of a set of diodes 1130, including

diodes

1132 and 1134. Diode 1132 includes doped

regions

1332, 1334, and 1336, and diode 1134 includes doped

regions

1352, 1354, and 1356.

Doped regions

1332 and 1352 are similar to doped region 1222 and may be formed as described with respect to doped region 1222, doped

regions

1334 and 1354 are similar to doped region 1224 and may be formed as described with respect to doped region 1224, and

doped regions

1336 and 1356 are similar to doped region 1226 and may be formed as described with respect to doped region 1226. The doped region 1332 is electrically connected to the interconnect 1362 via a salicide member 1342, and the doped region 1356 is electrically connected to the interconnect 1366 via a salicide member 1346. In one embodiment,

doped regions

1336 and 1352 have opposite conductivity types, and salicide member 1344 electrically shorts doped

regions

1336 and 1352 together to electrically connect

diodes

1132 and 1134. If the

salicide members

1342, 1344, and 1346 are not present, a contact opening in the insulating layer 650 can be formed over the doped

regions

1336 and 1352, and another interconnect can be formed within the contact opening to electrically short the

doped regions

1336 and 1352 together. More than two diodes may be connected in series. As the number of diodes increases, the breakdown voltage of a set of diodes 1130 increases and the voltage required to forward bias the diodes also increases. After reading this specification, skilled artisans will be able to design a set of diodes for a particular application.

Many different circuits may be used with the semiconductor body 240, providing at least one resistor or at least one diode for the circuit. In many of the subsequent figures, the interconnections will be shown with lines so that the positional relationship between the electronic components can be more clearly seen. In the top view illustration, the contacts are shown with Xs within the box and the interconnects are shown with lines. In practice, the interconnects may be at one or more different interconnect levels and may obscure portions of the electronics and their positional relationship to each other, which is why the actual interconnects are not shown.

In the circuit 1400 shown in fig. 14 and 15, a pair of

resistors

1420 and 1440 may be connected in parallel with the resistor 1420 in the active area 102 of the substrate 100 and the resistor 1440 within the semiconductor body 240 within the trench 120. Shallow trench isolation 1402 is covered with a portion of substrate 100 (not labeled in fig. 15) outside of the electronic component within active area 102, and shallow trench isolation 1404 is covered with a portion of substrate 100 (not labeled in fig. 15) outside of the electronic component within active area 104. In this embodiment, the resistor 1420 is located within a single crystalline semiconductor material and the resistor 1440 is located within a polycrystalline semiconductor material. The resistance of resistor 1420 increases with increasing temperature, while the resistance of resistor 1440 decreases with increasing temperature. Thus,

resistors

1420 and 1440 may be designed such that each at least partially cancels the other as temperature changes. In embodiments at room temperature (e.g., in the range of 20 ℃ to 25 ℃), the resistance of resistor 1420 may be within 50% of the resistance of resistor 1440. As the difference in resistance increases at a particular temperature (e.g., room temperature), the ability of

resistors

1420 and 1440 to compensate for each other may decrease.

In another circuit 1600 shown in fig. 16 and 17, a similar pair of

resistors

1620 and 1640 may be used as part of a temperature sensing circuit. A battery 1610 or other voltage source may be connected to the terminals of

resistors

1620 and 1640. The other terminals of

resistors

1620 and 1640 are electrically connected at node 1650. Output voltage (V)_OUT) May be measured between node 1650 and either terminal of battery 1610 or other voltage source. As shown in FIG. 16, V_OUTMeasured between the negative terminal of battery 1610 and node 1650. Similar to the previous embodiment, resistor 1620 is in active region 102 of substrate 100 and resistor 1640 is within semiconductor body 240 within trench 120. In anotherIn an embodiment, the positions of

resistors

1620 and 1640 may be reversed. Because temperature variations have an opposite effect on the resistance of

resistors

1620 and 1640, circuit 1600 may be more sensitive to temperature variations than a temperature sensing circuit that includes a resistor only within active region 102 or only within semiconductor body 240. Multiple temperature sensors may be used within the electronic device to provide a more complete temperature profile of the electronic device when the electronic device is used.

In the additional circuits shown in fig. 18 and 19, the inverter 1800 may include a resistor 1820 and a transistor 1840. A terminal of resistor 1820 is coupled to high voltage terminal 1802, and another terminal of resistor 1820 is coupled to a current carrying terminal of transistor 1840 at a node 1850 that is coupled to output terminal 1808. A control terminal of the transistor 1840 is coupled to the input terminal 1806, and another current-carrying terminal of the transistor 1840 is coupled to the low voltage terminal 1804. In one embodiment, the transistor 1840 is an enhancement-mode transistor. In the embodiment shown, the transistor 1840 is an n-channel Metal Insulator Semiconductor Field Effect Transistor (MISFET) and the high voltage terminal 1802 is at V_DDIs down and electrically connected to the terminal of resistor 1820, and the low voltage terminal 1804 is at V_SSAnd is electrically connected to a source electrode 1844 of the transistor 1840. The input terminal 1806 is electrically connected to a gate electrode 1846 of the transistor 1840, and the other terminal of the resistor 1820 and a drain electrode 1842 of the transistor 1840 are electrically connected to each other at a node 1850.

Resistor 1820 may be formed within semiconductor body 240. In one embodiment, resistor 1820 may have a relatively high resistance, e.g., greater than 0.1 milliohms, and typically in the range of 1 milliohm to 10 milliohms. The transistor 1840 may be formed within the active region 102 of the substrate 100. Interconnects at one or more interconnect levels may be used to connect the resistor 1820 and the transistor 1840 to each other and to connect the electronic components to their corresponding terminals, which may be connected to other portions of the electronics external to the inverter 1800.

Fig. 20 and 21 include circuits using voltage dividers in conjunction with transistors. In fig. 20, the circuit 2000 includes a bipolar transistor 2020 and

resistors

2042 and 2044. Bipolar transistor 2020 has an associated collector resistance, shown as resistor 2022, and an associated emitter resistance, shown as resistor 2024. In the illustrated embodiment, the transistor 2020 is an npn bipolar transistor. Terminals of the

resistors

2022 and 2042 are coupled to the high voltage terminal 2002, the other terminal of the resistor 2022 is coupled to the collector of the transistor 2020, a terminal of the resistor 2042, a base of the transistor 2020, and a terminal of the resistor 2044 are coupled to each other, a terminal of the resistor 2024 is coupled to the emitter of the transistor 2024, and the other terminal of the resistor 2044 and the other terminal of the resistor 2024 are coupled to the low voltage terminal 2004. In a particular embodiment, the high voltage terminal 2002 may be at V_CCAnd the low voltage terminal may be at V_EE. Circuit 2100 in fig. 21 is similar except that transistor 2020 and

resistors

2022 and 2024 are replaced by a junction field effect transistor 2120 having an associated drain resistance shown as resistor 2122 and an associated source resistance shown as resistor 2124. The high voltage terminal 2002 may be at V_DDAnd the low voltage terminal may be at V_SS. The

transistors

2020 and 2120 and their associated

resistors

2022, 2024, 2122, and 2124 may be within the active region of the substrate 100, and one or both of the

resistors

2042 and 2044 may be within the semiconductor body 240. In another embodiment, one of

resistors

2042 or 2044 may be within an active region of the substrate, and such active region may be the same or a different active region for

transistor

2020 or 2120.

Fig. 22-25 include illustrations of more complex circuitry 2200 that allow for different layout options for the circuitry 2200. Circuit 2200 includes resistor 2242,

diodes

2262 and 2264, and transistor 2222. Input terminal 2206 is coupled to a terminal of resistor 2242, and high voltage terminal 2202 is coupled to the cathode of diode 2262. The other terminal of the resistor 2242, the anode of the diode 2262, the cathode of the diode 2264, and the gate electrode of the transistor 2222 are coupled to each other. The low voltage terminal 2204 is coupled to the anode of a diode 2264. The current carrying terminal of transistor 2222 is coupled to other electronic components or terminals of the electronic device. In the embodiment shown, transistor 2222 is a MISFET, and in another embodiment (not shown), transistor 2222 may be a bipolar transistor. Circuit 2200 is well suited for high speed logic circuits (e.g., switching speeds of at least 1 MHz). Thus, the transistor 2222 may be a logic transistor. Resistor 2242 may help limit the current flowing to the gate electrode of transistor 2222.

Diodes

2262 and 2264 may help limit the voltage seen at the gate electrode that may occur during an electrostatic discharge event, voltage overshoot at input terminal 2206, and the like.

Transistor 2222 is in block 2220, resistor 2242 is in block 2240, and

diodes

2262 and 2264 are in block 2260.

Blocks

2220, 2240, and 2260 may correspond to different locations in different parts of the electronic device. Transistor 2222 (block 2220) may be located within an active region of substrate 100, resistor 2242 (block 2240) may be located within an active region of semiconductor body 240 or substrate 100, and diodes 2262 and 2264 (block 2260) may be located within an active region of semiconductor body 240 or substrate 100. As shown in fig. 23-25, the physical design of the circuit 2200 may be tailored to a particular application by placing components in boxes in various locations.

Fig. 23 includes a layout in which the electronic components of

blocks

2220 and 2260 are within the same active area of the substrate, and the electronic component of block 2240 is within semiconductor body 240. Transistor 2222 and

diodes

2262 and 2264 are separated from each other by shallow trench isolation 1402. In another embodiment,

diodes

2262 and 2264 may have a layout similar to the set of diodes 1130 shown in fig. 11 and 13. The drain region 2322 is coupled to another portion of the electronic device and the source region 2324 is coupled to another portion of the electronic device. In the illustrated embodiment, one end of gate electrode 2326 is electrically connected to N of diode 2262⁺P of diode 2264⁺And the other end of gate electrode 2326 is electrically connected to a terminal of resistor 2242 within semiconductor body 240. The other terminal of resistor 2242 is coupled to input terminal 2206. P of diode 2262⁺N of diode 2264 and area coupled to high voltage terminal 2202⁺And is coupled to low voltage terminal 2204.

Fig. 24 includes a layout wherein the electronic components of block 2220 are within the active area of the substrate and the electronic components of

blocks

2240 and 2260 are within the semiconductor body 240. Fig. 24 is similar to fig. 23 except that

diodes

2262 and 2264 are within a portion of semiconductor body 240 spaced apart from resistor 2242 and the shape of resistor 2242 changes. The resistor 2242 may be within the

active region

102 or 104, rather than within the semiconductor body 240, if needed or desired. Further, one of

diodes

2262 and 2264 may be within semiconductor body 240 and the other of

diodes

2262 and 2264 may be within

active region

102 or 104. Gate electrode 2326 extends to

diodes

2262 and 2264 and may be electrically connected to the anode of diode 2262 and the cathode of diode 2264 with a silicide member or interconnect.

Fig. 25 includes a layout in which the electronic components of

blocks

2220 and 2260 are in different active areas of the substrate, and the electronic component of block 2240 is in semiconductor body 240. In one embodiment, the different active regions are disposed along opposite sides of the trench 120 including the semiconductor body 240. In the illustrated embodiment, transistor 2222 is within active region 102 (not labeled in fig. 25), and

diodes

2262 and 2264 are within active region 104 (not labeled in fig. 25), and active region 104 is disposed along an opposite side of the deep trench isolation within trench 120 as compared to active region 102. In another embodiment, one of

diodes

2262 and 2264 may be within active region 104 and the other of

diodes

2262 and 2264 may be within active region 102. In further embodiments, one of

diodes

2262 and 2264 may be within semiconductor body 240 and the other of

diodes

2262 and 2264 may be within

active region

102 or 104.

After reading this specification, skilled artisans will appreciate that many other physical designs, including layouts, may be used to achieve the needs or desires of an application. The embodiments shown in fig. 23-25 are intended to be exemplary and not limiting to the scope of the invention.

Fig. 26 and 27 include a switching circuit 2600 that may be used as an energy converter, such as a buck converter, a voltage regulator, and the like. Circuit 2600 includes a high-side transistor 2622, a low-side transistor 2624,

diodes

2662 and 2664, and

resistors

2642 and 2644. The circuit may also include other electronic components not shown, such as inductors, capacitors, etc., coupled to the output terminal 2608.

Referring to fig. 26, a high-side transistor 2622 has a current-carrying terminal coupled to the high-voltage terminal 2602, a control terminal of the transistor 2622 is coupled to a high-side control circuit including a resistor 2642, and another current-carrying terminal of the transistor 2622 is coupled to a current-carrying terminal of a low-side transistor 2624 at a node 2650. A control terminal of the transistor 2624 is coupled to the low side control circuit including the resistor 2644, and another current carrying terminal of the transistor 2624 is coupled to the low voltage terminal 2604. In one embodiment,

transistors

2622 and 2624 are MISFETs, and in one particular embodiment, are n-channel MISFETs. A source of the high-side transistor 2622 is coupled to a drain of the low-side transistor 2624. The high-side control circuit may include a gate driver circuit for the transistor 2622 and the low-side control circuit may include a gate driver circuit for the transistor 2624. In one particular embodiment, each of the

transistors

2622 and 2624 is a power transistor.

A cathode of diode 2662 is coupled to high voltage terminal 2602, an anode of diode 2662 and a cathode of diode 2664 are coupled to node 2650, and an anode of diode 2664 is coupled to low voltage terminal 2604.

Diodes

2662 and 2664 may have a breakdown voltage (e.g., BV) lower than between current carrying terminals_DS) To protect

transistors

2622 and 2624 during voltage overshoot that may occur during switching operations of circuit 2600. Node 2650 is coupled to output terminal 2608.

In fig. 26, transistor 2622 and diode 2662 are within block 2610, transistor 2624 and diode 2664 are within block 2630, and

resistors

2642 and 2644 are within block 2640. In one embodiment, the electronic components within block 2610 are within active regions of substrate 100, resistors 2642 and 2644 (block 2640) are within semiconductor body 240, the electronic components within block 2630 are within different active regions of substrate 100, or may be on a separate die from the rest of circuit 2600.

Fig. 27 includes exemplary embodiments of components within

blocks

2610, 2630, and 2640. In this embodiment, each transistor and its corresponding diode are within the same active area, such that each diode provides good control over the voltage across its corresponding transistor to reduce the effects of voltage overshoot, which may be in the form of ringing at node 2650. The electronic components within

blocks

2610 and 2630 are arranged along opposite sides of the trench 120. Resistors 2642 and 2644 within block 2640 may be within portions of semiconductor body 240 within trench 120.

As shown in fig. 27,

shallow trench isolations

2612, 2614, 2616 and 2618 overlie the active regions of the substrate 100. For example, the shallow trench isolation 2612 may overlie the active region 102, the shallow trench isolation 2614 may overlie the active region 104, and the shallow trench isolation 2616 may overlie another active region, and the shallow trench isolation 2618 may overlie another active region. Although not shown, other electronic components may be formed within any active region. For example, other electronic components for the high-side control circuitry may be in the active area below the shallow trench isolation 2616, and other electronic components for the low-side control circuitry may be in the active area below the shallow trench isolation 2618.

In the illustrated embodiment, the transistor 2622 includes a source electrode 26224, a gate electrode 26224, and a drain electrode 26226. The drift region 26228 is shown in dashed lines because the drift region 26228 is located below the shallow trench isolation 2612. Diode 2662 is also located in the same active region as transistor 2622. The drain electrode 26222 is shown with P to the high voltage terminal 2602 and the diode 2662⁺The connection of the regions. The gate electrodes 26226 are connected to each other and coupled to a terminal of the resistor 2642, and another terminal of the resistor 2642 is coupled to another electronic component within the active region below the shallow trench isolation 2616. Source electrode 26224 is shown as having N to diode 2662⁺The connection of the regions.

In the illustrated embodiment, the transistor 2624 includes a source electrode 26244, a gate electrode 26246, and a drain electrode 26246. The drift region 26248 is shown in dashed lines because the drift region 26248 is located below the shallow trench isolation 2614. Diode 2664 is also located in the same active region as transistor 2624. Drain electrode 26242 is shown as having P to diode 2664⁺The connection of the regions. Grid electrodeThe electrodes 26246 are connected to each other and coupled to a terminal of a resistor 2644, and another terminal of the resistor 2644 is coupled to another electronic component within the active region below the shallow trench isolation 2618. Source electrode 26244 is shown as having N to low voltage terminal 2604 and diode 2664⁺The connection of the regions.

Source electrode 26224 of high-side transistor 2622, N of diode 2662⁺Region, drain electrode 26242 of low-side transistor 2624 and P of diode 2664⁺The regions are coupled to each other at node 2650. Node 2650 is coupled to output terminal 2608. In the illustrated embodiment, node 2650 is electrically connected to output terminal 2608. In another embodiment, a capacitor (not shown) may be coupled between the output node 2650 and the low voltage terminal 2604, and an inductor (not shown) may be coupled between the output node 2650 and the output terminal 2608. The capacitor and inductor may help reduce ringing at the output node 2650 during switching operations and reduce the amount of current surge to a load (not shown) coupled between the output terminal 2608 and the low voltage terminal 2604.

In addition to the circuit shown in fig. 27, many other physical designs may be used for the circuit of fig. 26. For example, one or both of

diodes

2662 and 2664 may be formed within semiconductor body 240. One or both of the

resistors

2642 and 2644 may be formed in the same active region corresponding to the

shallow trench isolation

2616 or 2618. In further embodiments, a semiconductor die may include a high-side transistor 2622 and its corresponding control circuitry, and another semiconductor die may include a low-side transistor 2624 and its corresponding control circuitry. Still further physical designs are possible.

After reading this description, the skilled person will understand that the physical design, including the shown layout, is simplified. In practice, more complex and densely packed components may be implemented using the concepts described herein. Further, the power transistor may have more contacts as shown to allow sufficient current to flow through such power transistor.

Embodiments described herein may be used to form resistors and diodes within a semiconductor body that does not otherwise include any electronic components. The semiconductor body may be a portion of a semiconductor material filling a trench that is part of a deep trench isolation structure. The semiconductor body may be separated from adjacent active regions by an insulating layer and, thus, the semiconductor body may include one or more electronic components coupled to electronic components within the active regions on either or both sides of the deep isolation trenches. The process of forming the electronic component within the semiconductor body may be integrated with existing process flows when forming the doped region of the electronic component in the active region. Therefore, no additional masking operations or process steps are required.

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Upon reading this specification, skilled artisans will appreciate that those aspects and embodiments are exemplary only, and do not limit the scope of the invention. Implementations may be in accordance with any one or more of the items listed below.

Embodiment 1. an electronic device may include: a substrate defining a trench having a depth of at least 5 microns; a semiconductor body within the trench, wherein the semiconductor body has an upper surface and a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate; and a first electronic component within and along the upper surface of the semiconductor body, wherein the first electronic component is spaced apart from the bottom of the semiconductor body.

Embodiment 2 the electronic device of embodiment 1, further comprising an insulating layer disposed between the semiconductor body and the sides and bottom of the trench.

Embodiment 3 the electronic device of embodiment 1, wherein the substrate comprises a single crystalline semiconductor material and the semiconductor body comprises a polycrystalline semiconductor material.

Embodiment 4 the electronic device of embodiment 1, wherein the first electronic component includes a first doped region within the semiconductor body, wherein a dopant concentration of the first doped region is higher than a background dopant concentration of the semiconductor body, and a portion of the semiconductor body outside of the first doped region is located vertically below and laterally beside the first doped region.

Embodiment 5 the electronic device of embodiment 4, wherein the first electronic component is a diode and further comprising a second doped region having an opposite conductivity type compared to the first doped region.

Embodiment 6 the electronic device of embodiment 4, wherein the first electronic component is a resistor including a first doped region, the first doped region being a well region extending to a depth less than half a depth of the trench.

Embodiment 7 the electronic device of embodiment 1, further comprising a first doped region and a second doped region spaced apart from the first doped region, wherein the first and second doped regions have the same conductivity type, each of the first and second doped regions has a dopant concentration higher than a dopant concentration of the semiconductor body, and a portion of the semiconductor body having a resistivity of at least 0.05 ohm-cm is disposed between the first and second doped regions.

Embodiment 8 an electronic device may include: a substrate defining a trench; a first electronic component within a first active region of the substrate, wherein the first active region is outside the trench; an isolation structure within the trench and adjacent to the first electronic component; and a second electronic component within the isolation structure.

Embodiment 9 the electronic device of embodiment 8, wherein the isolation structure comprises: a semiconductor body including at least a portion located below the second electronic component; and an insulating layer disposed along the sides and bottom of the trench and electrically isolating the semiconductor body from the substrate.

Embodiment 10 the electronic device of embodiment 9, wherein the first active region comprises a single crystalline semiconductor material and the semiconductor body and the second electronic component comprise a polycrystalline semiconductor material.

Embodiment 11 the electronic device of embodiment 8, further comprising a third electronic component within the second active region of the substrate, wherein the isolation structure is disposed between the first and third electronic components.

Embodiment 12. the electronic device of embodiment 11, wherein:

the first electronic component is a power transistor or a logic transistor, and

the third electronic component is the other of the power transistor or the logic transistor.

Embodiment 13 the electronic device of embodiment 12, wherein the power transistor comprises a metal insulator semiconductor field effect transistor, an insulated gate bipolar transistor, or a bipolar transistor.

Embodiment 14 the electronic device of embodiment 8, wherein the first electronic component is a transistor and the second electronic component is a resistor coupled to the transistor.

Embodiment 15 the electronic device of embodiment 8, wherein the first electronic component is a transistor and the second electronic component is a diode coupled to the transistor.

Embodiment 16 the electronic device according to embodiment 8, wherein the first electronic component is a first resistor, the second electronic component is a second resistor, and the first and second resistors are connected in parallel.

Embodiment 17 the electronic device of embodiment 16, wherein the first resistor has a body comprising a single crystalline semiconductor material and the second resistor has a body comprising a polycrystalline semiconductor material.

Embodiment 18 an electronic device may include: a substrate defining a trench; a semiconductor body within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate; and a diode within the semiconductor body.

Embodiment 19 the electronic device of embodiment 18, wherein the semiconductor body and diode comprise polycrystalline semiconductor material.

Embodiment 20 the electronic device of embodiment 19, further comprising a first electronic component and a second electronic component, wherein the isolation structure comprises a semiconductor body and an insulating layer electrically isolating the semiconductor body from the substrate, the first electronic component is along a first side of the isolation structure, the second electronic component is along a second side of the isolation structure opposite the first side, and each of the first electronic component, the second electronic component, or the first and second electronic components is coupled to a diode.

Further embodiments may include any of the following items.

1. An electronic device, comprising:

a substrate defining a trench;

a first electronic component within a first active region of the substrate, wherein the first active region is outside the trench;

an isolation structure within the trench and adjacent to the first electronic component; and

a second electronic component within the isolation structure.

2. The electronic device of item 1, wherein the isolation structure comprises:

a semiconductor body including at least a portion located below the second electronic component;

to know

An insulating layer disposed along the sides and bottom of the trench and electrically isolating the semiconductor body from the substrate.

3. The electronic device of item 2, wherein the first active region comprises a single crystalline semiconductor material and the semiconductor body and the second electronic component comprise a polycrystalline semiconductor material.

4. The electronic device of any of items 1-3, further comprising a third electronic component within the second active region of the substrate, wherein the isolation structure is disposed between the first and third electronic components.

5. The electronic device of item 4, wherein:

the first electronic component is a power transistor or a logic transistor, and

6. The electronic device of any of items 1-3, wherein the first electronic component is a transistor and the second electronic component is a resistor or a diode, wherein the first electronic component is coupled to the second electronic component.

7. The electronic device according to any one of items 1 to 3, wherein the first electronic component is a first resistor, the second electronic component is a second resistor, and the first and second resistors are connected in parallel.

8. The electronic device of item 7, wherein the first resistor has a body comprising a single crystalline semiconductor material and the second resistor has a body comprising a polycrystalline semiconductor material.

9. An electronic device, comprising:

a substrate defining a trench;

a semiconductor body within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate; and

a diode, which is within the semiconductor body,

wherein the semiconductor body and the diode comprise polycrystalline semiconductor material.

10. An electronic device, comprising:

a substrate comprising a single crystal semiconductor material and defining a trench having a depth of at least 5 microns;

a semiconductor body within the trench, wherein the semiconductor body comprises a polycrystalline semiconductor material, has an upper surface, has a resistivity of at least 0.05 ohm-cm, and is electrically isolated from the substrate; and

a first electronic component within and along the upper surface of the semiconductor body, wherein the first electronic component is spaced apart from the bottom of the semiconductor body.

It should be noted that not all of the activities described above in the general description or the examples are required, that a portion of a particular activity may not be required, and that one or more additional activities may be performed in addition to those described. Also, the order in which activities are listed are not necessarily the order in which the activities are performed.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or feature of any or all the claims.

The description and illustrations of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The description and drawings are not intended to be an exhaustive or comprehensive description of all the elements and features of apparatus and systems that utilize the structures or methods described herein. Separate embodiments may also be provided in combination in a single embodiment, but rather, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to a value being expressed as a range includes all values within that range. Many other embodiments will be apparent to those of skill in the art upon reading this specification. Other embodiments may be utilized and derived from the disclosure, such that structural substitutions, logical substitutions, or additional changes may be made without departing from the scope of the disclosure. Accordingly, the present disclosure is to be considered as illustrative and not restrictive.

Claims

1. An electronic device, comprising:

a substrate defining a trench;

a second electronic component within the isolation structure.

2. The electronic device of claim 1, wherein the isolation structure comprises:

a semiconductor body including at least a portion located below the second electronic component; and

an insulating layer disposed along sides and a bottom of the trench and electrically isolating the semiconductor body from the substrate.

3. The electronic device of claim 2, wherein the first active region comprises a single crystalline semiconductor material and the semiconductor body and the second electronic component comprise a polycrystalline semiconductor material.

4. The electronic device of any of claims 1-3, further comprising a third electronic component within a second active region of the substrate, wherein the isolation structure is disposed between the first and third electronic components.

5. The electronic device of claim 4, wherein:

the first electronic component is a power transistor or a logic transistor, and

6. The electronic device of any of claims 1-3, wherein the first electronic component is a transistor and the second electronic component is a resistor or a diode, wherein the first electronic component is coupled to the second electronic component.

7. The electronic device according to any one of claims 1 to 3, wherein the first electronic component is a first resistor, the second electronic component is a second resistor, and the first and second resistors are connected in parallel.

8. The electronic device of claim 7, wherein the first resistor has a body comprising a single crystalline semiconductor material and the second resistor has a body comprising a polycrystalline semiconductor material.

9. An electronic device, comprising:

a substrate defining a trench;

a diode within the semiconductor body,

10. An electronic device, comprising:

a first electronic component within and along an upper surface of the semiconductor body, wherein the first electronic component is spaced apart from a bottom of the semiconductor body.