CN109244141A - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN109244141A CN109244141A CN201811149857.4A CN201811149857A CN109244141A CN 109244141 A CN109244141 A CN 109244141A CN 201811149857 A CN201811149857 A CN 201811149857A CN 109244141 A CN109244141 A CN 109244141A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000002360 preparation method Methods 0.000 title claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 105
- 229920005591 polysilicon Polymers 0.000 claims abstract description 102
- 239000002184 metal Substances 0.000 claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 125000006850 spacer group Chemical group 0.000 claims abstract description 29
- 238000002347 injection Methods 0.000 claims description 32
- 239000007924 injection Substances 0.000 claims description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 1
- 230000001413 cellular effect Effects 0.000 abstract description 19
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The present invention provides a kind of semiconductor devices, including grid and gate metal layer, the grid includes a plurality of polysilicon gate disposed in parallel, gate liner, grid cabling, the grid finger positioned at the middle part of the semiconductor devices for connecting the polysilicon gate and the gate liner, the grid finger includes multiple spaced polysilicon spacers, the polysilicon spacers connect two adjacent polysilicon gates, the upper surface of the multicrystalline silicon substrate and the grid cabling has offered contact hole, and the contact hole is for filling the gate metal layer.This semiconductor devices considerably increases the consistency that cellular is switched on or off, and reduces the loss of semiconductor devices, avoids the overcurrent of cellular from failing, increases the reliability of semiconductor devices.
Description
Technical field
The present invention relates to technology of semiconductor chips field more particularly to a kind of semiconductor devices and its manufacturing methods.
Background technique
Since vertical double diffused metal-oxide semiconductor field effect transistor (VDMOS) occurs, electron electric power is obtained
It rapidly develops, due to its unique high input impedance, low driving power, high switching speed, superior frequency characteristic and very
The features such as thermal stability got well, it is widely used in Switching Power Supply, automotive electronics, motor driving, each neck such as high frequency oscillator
Domain.
There are three electrodes for vertical double diffused metal-oxide semiconductor field effect transistor semiconductor devices, except drain electrode position
Other than chip back, grid and source electrode are respectively positioned on chip front side, current vertical double diffused metal-oxide semiconductor field effect
In transistor semiconductor device structure, the more complicated connection type for grid, each polysilicon gate passes through surrounding
The connection of grid cabling, and be connected in gate liner by grid cabling.When opening, one important to examine semiconductor devices
It measures all cellulars sought to so that in active area while opening or closing, that is, when applying a positive electricity in gate liner
When pressure, to make all polysilicon gates while generate this positive voltage, but since polysilicon itself has resistance,
The cellular remoter apart from gate liner, unlatching it is slower, this will lead to semiconductor devices switch when, it cannot be guaranteed that cellular is same
When be switched on and off, and loss concentrate on certain cellulars, so as to cause cellular overcurrent fail.
Summary of the invention
For overcome the deficiencies in the prior art, the purpose of the present invention is to provide one kind to be not take up excessive chip area and energy
Guarantee the semiconductor devices and preparation method thereof that cellular is switched on or off simultaneously.
In order to solve the above technical problems, the present invention adopts the following technical solutions: a kind of semiconductor devices comprising grid and
Gate metal layer, the grid include a plurality of polysilicon gate disposed in parallel, gate liner, the connection polysilicon gate and
The grid cabling of the gate liner, the grid finger positioned at the middle part of the semiconductor devices, the grid finger include more
A spaced polysilicon spacers, the polysilicon spacers connect two adjacent polysilicon gates, the multicrystalline silicon substrate
Contact hole is offered with the upper surface of the grid cabling, the contact hole is for filling the gate metal layer.
Design concept according to the present invention, semiconductor devices of the present invention further include:
Substrate；
It is formed in the epitaxial layer of the upper surface of the substrate；
The grid oxic horizon being formed between the upper surface of the substrate and the lower surface of the grid；
Form the dielectric layer on the outside of the upper surface and the grid of the epitaxial layer.
Design concept according to the present invention, semiconductor devices of the present invention further include being covered on the polysilicon gate pair
The drain metal layer of the source metal of the top for the dielectric layer answered and the lower surface for being formed in the substrate.
The spacing of design concept according to the present invention, source metal of the present invention and the gate metal layer is 4-7 μ
m。
Design concept according to the present invention, semiconductor devices of the present invention further include prolonging from the upper surface of the epitaxial layer
It extends to the body area inside the epitaxial layer and extends to the source region inside the body area from the upper surface in the body area.
Design concept according to the present invention, the width of polysilicon gate of the present invention are 7~10 μm, and spacing is 7~10 μ
m。
Design concept according to the present invention, the length of polysilicon spacers of the present invention are 15-20 μm.
The present invention also provides a kind of preparation methods of semiconductor devices, comprising the following steps:
S1: providing substrate, forms epitaxial layer in the upper surface of the substrate, is formed initially in the upper surface of the epitaxial layer
Oxide layer deposits one layer of polysilicon layer in the upper surface of the initial oxide layer；
S2: it etches the polysilicon layer and forms parallel a plurality of polysilicon gate, gate liner, the connection polysilicon gate
The grid cabling of pole and the gate liner, the grid finger in the middle part of semiconductor devices, the grid finger includes multiple
Spaced polysilicon spacers, the polysilicon spacers connect two adjacent polysilicon gates；
S3: it injects and drives in form body area by autoregistration；
S4: the upper surface of the initial oxide layer between polysilicon gate is laid with source region photoresist, forms the first source region note
Enter area and the second source region injection region, first source region injection region is located at the two sides of grid finger and is located at polysilicon gate and institute
It states between photoresist, first source region is injected between spaced gate liner in second source region injection region
Area and the second source region injection region are injected and drive in form source region by autoregistration；
S5: it etches the oxide layer and forms spaced grid oxic horizon, in the grid oxic horizon and the grid
Outside formed dielectric layer；
S6: contact hole is formed in the upper surface of the grid cabling and the grid finger；
S7: one layer of metal layer is deposited in the upper surface of the dielectric layer and the epitaxial layer, the metal layer is etched and is formed
The gate metal layer and source metal at interval.
Design concept according to the present invention further includes forming leakage in the lower surface of the substrate in step S7 of the present invention
Pole metal layer.
Design concept according to the present invention, in step S6 of the present invention, in contact hole deposit metal and with the grid
Metal layer is shorted.
Semiconductor devices needs the cellular in active area while opening, but apply voltage in gate liner when opening
When, since polysilicon gate itself has resistance and to the distance of gate liner difference, the unlatching of the cellular of active area speed
It spends not identical.Grid finger is arranged at the middle part of semiconductor devices in the present invention, and grid finger is connected two-by-two by multiple compartment of terrain
The polysilicon spacers of adjacent polysilicon gate form, gate metal is covered above grid finger, reduce polysilicon gate with this
To the distance of gate liner in the middle part of pole, while contact hole is formed on grid cabling and polysilicon spacers, contact hole and grid gold
Belong to and being shorted, since metallic resistance is much smaller than polysilicon resistance, the pressure drop on grid cabling and polysilicon spacers at this time substantially can be with
It ignores, considerably increases the consistency that cellular is switched on or off, greatly reduce the loss of semiconductor devices, avoid cellular
Overcurrent failure, increase the reliability of semiconductor devices, and grid finger is located at the middle part of semiconductor devices, it is only necessary to one
Grid finger can be realized, and can also realize the function of cellular in the lower section of grid finger, will not excessive chip occupying area
It causes to waste.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the top view of the grid for the semiconductor devices that one embodiment of the invention provides；
Fig. 2 is the flow diagram of the manufacturing method for the semiconductor devices that one embodiment of the invention provides；
Fig. 3 to Fig. 6 is the preparation process figure for the semiconductor devices that one embodiment of the invention provides；
Fig. 9 is the body area preparation process top view for the semiconductor devices that one embodiment of the invention provides；
Figure 12 is the source region preparation process top view for the semiconductor devices that one embodiment of the invention provides
Fig. 7, Figure 10, Figure 13, Figure 15, Figure 17, Figure 19, Figure 21, Figure 22, Figure 24 are partly leading for one embodiment of the invention offer
The schematic diagram of the section structure along A-A ' of the preparation process of body device；
Fig. 8, Figure 11, Figure 14, Figure 16, Figure 18, Figure 20, Figure 23, Figure 25 are the semiconductor devices that one embodiment of the invention provides
The schematic diagram of the section structure along B-B ' of the preparation process of part；
Figure 26 is the gate metal layer for the semiconductor devices that one embodiment of the invention provides and the top view of source metal.
In figure: 10, grid；10a, polysilicon layer；11, polysilicon gate；12, grid cabling；13, gate liner；14, grid
Pole finger；14a, polysilicon spacers；15, contact hole；20, substrate；30, epitaxial layer；40, grid oxic horizon；40a, initial oxidation
Layer；50, body area；50a, body area injection region；51, source region；51a, source region photoresist；51b, the first source region injection region；51c, second
Source region injection region；60, dielectric layer；70, gate metal layer；80, source metal；90, drain metal layer.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
In the following, the invention will be further described in conjunction with attached drawing and specific embodiment:
As shown in Figure 1, the present invention provides a kind of semiconductor devices, including grid 10 and gate metal layer 70, the grid
10 include the grid of a plurality of polysilicon gate 11, gate liner 13, the connection polysilicon gate 11 and the gate liner 13
Cabling 12, the grid finger 14 positioned at the middle part of the semiconductor, the grid finger 14 include multiple spaced polycrystalline
Silicon pads 14a, and the polysilicon spacers 14a connects two adjacent polysilicon gates 11, the polysilicon spacers 14a and described
The upper surface of grid cabling 12 offers contact hole 15, and the contact hole 15 is for filling the gate metal layer 70.
Grid finger 14 is arranged at the middle part of semiconductor devices in the present invention, and grid finger 14 includes multiple spaced more
Crystal silicon pads 14a, and the polysilicon spacers 14a connects two adjacent polysilicon gates 11, and in grid finger 14 and grid
The top of cabling 12 opens up contact hole 15, and filling metal and gate metal layer 70 are shorted in contact hole 15, grid finger 14 and grid
The top of pole cabling 12 forms one layer of gate metal layer 70, since metallic resistance is much smaller than polysilicon resistance, grid cabling at this time
12 and grid finger 14 on pressure drop can be ignored substantially, and since the formation of grid finger 14 shortens polysilicon gate
11 to gate liner 13 distance, shorten the opening time of cellular, increase in active area all cellulars while opening or closing
The consistency closed.
Preferably, semiconductor devices of the present invention further include:
Substrate 20；
It is formed in the epitaxial layer 30 of the upper surface of the substrate 20；
The grid oxic horizon 40 being formed between the upper surface of the substrate 20 and the lower surface of the grid 10；
Form the dielectric layer 60 in 10 outside of upper surface and the grid of the epitaxial layer 30.
Preferably, semiconductor devices of the present invention further includes being covered on the corresponding dielectric layer 60 of the polysilicon gate 11
Top source metal 80 and be formed in the substrate 20 lower surface drain metal layer 90.
Preferably, the spacing of source metal 80 and the gate metal layer 70 of the present invention be 4-7 μm, keep this away from
From the gate metal short circuit that can be prevented on subsequent source metal and grid finger 14.
Preferably, semiconductor devices of the present invention further includes extending to the extension from the upper surface of the epitaxial layer 30
Body area 50 inside floor 30 and the source region 51 inside the body area 50 is extended to from the upper surface in the body area 50.
Preferably, the width of polysilicon gate 11 of the present invention is 7~10 μm, and spacing is 7~10 μm.
Preferably, the length of polysilicon spacers 14a of the present invention is 15-20 μm.
Referring to Fig. 2, a kind of manufacturing method of semiconductor devices comprising following steps:
S1: providing substrate 20, epitaxial layer 30 is formed in the upper surface of the substrate 20, in the upper surface of the epitaxial layer 30
Initial oxide layer 40a is formed, deposits one layer of polysilicon layer 10a in the upper surface of the initial oxide layer 40a；
S2: etch the polysilicon layer 10a formed parallel a plurality of polysilicon gate 11, gate liner 13, connection described in
Polysilicon gate 11 and the grid cabling 12 of the gate liner 13, the grid finger 14 positioned at the middle part of semiconductor devices, institute
Stating grid finger 14 includes multiple spaced polysilicon spacers 14a, and the polysilicon spacers 14a connects adjacent more than two
Polysilicon gate 11；
S3: it injects and drives in form body area 50 by autoregistration；
S4: the initial oxide layer 40a between polysilicon gate 11 upper surface is laid with source region photoresist 51a, forms the
One source region injection region 51b and the second source region injection region 51c, 51 injection region of the first source region be located at the two sides of grid finger 14 and
Between polysilicon gate 11 and the source electrode photoresist 51a, second source region injection region 51b is located at spaced grid
Between pole liner 13, shape is injected and driven in by autoregistration to first source region injection region 51b and the second source region injection region 51c
At source region 51；
S5: it etches the initial oxide layer 40a and forms spaced grid oxic horizon 40, in the grid oxic horizon 40
Dielectric layer 60 is formed with the outside of the grid 10；
S6: contact hole 15 is formed in the upper surface of the grid cabling 12 and grid finger 14；
S7: one layer of metal layer is deposited in the upper surface of the dielectric layer 60 and the epitaxial layer 30, etches the metal layer
Form gate metal layer 70 and source metal 80.
3-26 with reference to the accompanying drawings elaborates the manufacturing method of the semiconductor devices.
Referring to figure 3. to Fig. 6, step S1 is executed: substrate 20 is provided, form epitaxial layer in the upper surface of the substrate 20
30, initial oxide layer 40a is formed in the upper surface of the epitaxial layer 30, deposits one in the upper surface of the initial oxide layer 40a
Layer polysilicon layer 10a.
Specifically, in the present embodiment, the substrate 20 is N-type substrate 20, and the epitaxial layer 30 is N-type epitaxy layer 30,
Preferably, the substrate 20 is N-type heavily doped silicon substrate 20, and the epitaxial layer 30 is N-type lightly doped epitaxial layer 30.
Further, one layer of initial oxide layer 40a is formed by thermal oxidation method in the upper surface of the epitaxial layer 30, preferably
Ground, the temperature of high temperature oxidation process can be 900-1100 DEG C, and the thickness of the initial oxide layer 40a can be according to semiconductor devices
Design depending on.
Further, one layer of polysilicon is deposited using chemical vapor deposition process in the upper surface of the initial oxide layer 40
Layer 10a.
Fig. 7 and Fig. 8 are please referred to, step S2 is executed: etching the polysilicon layer 10a and form parallel a plurality of polysilicon gate
11, gate liner 13, the connection polysilicon gate 11 and the gate liner 13 grid cabling 12, be located at semiconductor devices
Middle part grid finger 14, the grid finger 14 includes multiple spaced polysilicon spacers 14a, polysilicon lining
Pad 14a connects two adjacent polysilicon gates 11.
Specifically, it is laid with a layer photoresist layer in the upper surface of the polysilicon layer 10a, using with 10 figure of grid
Mask plate is exposed the photoresist layer as exposure mask, then develops, and is formed and the grid on the photoresist layer
The consistent window of 10 figure of pole, using the photoresist as exposure mask, from the window pair of the photoresist layer by the way of etching
The polysilicon layer 10a performs etching to form grid 10, and the grid includes parallel a plurality of polysilicon gate 11, gate liner
13, grid cabling 12, the grid in the middle part of semiconductor devices of the polysilicon gate 11 and the gate liner 13 are connected
Finger 14, in detail, the grid finger 14 include multiple spaced polysilicon spacers 14a, the polysilicon spacers 14a
Connect two adjacent polysilicon gates 11.
Fig. 9 to Figure 11 is please referred to, step S3 is executed: injecting and drive in form body area 50 by autoregistration；
Specifically, using the multiple polysilicon gate 11 as injection window, i.e., between a plurality of polysilicon gate 11
Gap carries out ion implanting, the body area by self-registered technology as body area injection region 50a, to body area injection region 50a
50 be the area PXing Ti 50, it is preferable that injection ion is B, Implantation Energy 80-120KeV, implantation dosage 3E13-8E13, into one
Step ground carries out high temperature to injection ion and drives in, it is preferable that and driving in temperature is 1100-1150 DEG C, and driving in the time is 80-200min,
After driving in, injection ion can be towards the inside divergent contour adult area 50 of epitaxial layer 30.
Figure 12 to Figure 14 is please referred to, step S4: the upper surface of the initial oxide layer 40a between polysilicon gate 11 is executed
It is laid with source region photoresist 51a, forms the first source region injection region 51b and the second source region injection region 51c, first source region 51 is injected
Area is located at the two sides of grid finger 14 and between polysilicon gate 11 and the source electrode photoresist 51a, second source region
Injection region 51b is between spaced gate liner 13, to first source region injection region 51b and the second source region injection region
51c injects and drives in form source region 51 by autoregistration.
Preferably, the ion of injection is N-type ion, temperature when driving in lower than source region 51 the temperature that drives in, described second
The length of the source region injection region 51c grid finger is 8-14 μm long.
Figure 15 to Figure 20 is please referred to, step S6 is executed: etching the initial oxide layer 40a and form spaced grid oxygen
Change layer 40, forms dielectric layer 60 in the outside of the grid oxic horizon 40 and the grid 10.
Specifically, the initial oxide layer 40a in 10 outside of grid is removed using wet etching, using chemical vapor deposition work
Skill deposits one layer of initial medium layer 60, the initial medium in the upper surface of the epitaxial layer 30 and the upper surface of the grid 10
Layer 60 can be silica or silicon nitride, performs etching to be formed to the initial medium layer 60 and is covered on the grid and described
The dielectric layer 60 of 40 epitaxial layer 30 of grid oxic horizon.
Referring to figure 2. 1, it executes step S6: forming contact hole 15 on the grid cabling 12 and grid finger 14；
Specifically, a layer photoresist layer is covered in the upper surface of the grid 10 and the epitaxial layer 30, is connect using having
The mask plate of 15 figure of contact hole is exposed the photoresist layer as exposure mask, then develops, on the photoresist layer
Formation and the consistent window of 15 figure of contact hole, using the photoresist as exposure mask, from the light by the way of etching
The window of photoresist layer performs etching the grid 10 to be formed on the grid cabling 12 and the polysilicon spacers 14a and contact
Hole 15.
Referring to figure 2. 2 to Figure 26, step S6: deposited metal is executed, the metal layer is etched and forms gate metal layer 70
With source metal 80；
One layer of metal layer is deposited in the upper surface of the epitaxial layer 30 and the dielectric layer 60, the metal layer is carved
Erosion forms gate metal layer 70 and source metal 80, and wherein gate metal layer 70 is covered on gate liner 13, grid cabling 12
With 14 top of grid finger, source metal is covered on 14 two sides of grid finger, it is preferable that the gate metal layer 70 and source
The spacing of pole metal layer 80 is 4-7 μm.Further, drain metal layer 90 is formed in the lower surface of the substrate 20, specifically
Processing step is same as the prior art, and this is no longer going to repeat them.
Semiconductor devices needs the cellular in active area 51 while opening, but apply in gate liner 13 when opening
It is with resistance and different to the distance of gate liner 13 due to polysilicon gate 11 itself when voltage, the member of active area 51
The opening speed of born of the same parents is not identical.Grid finger 14 is arranged at the middle part of semiconductor devices in the present invention, and grid finger 14 is by multiple
Compartment of terrain connects the polysilicon spacers 14a composition of polysilicon gate 11 adjacent two-by-two, covering grid gold above grid finger 14
Belong to, the face of entire semiconductor devices not will increase to reduce by 11 middle part of polysilicon gate to the distance of gate liner 13 and with this
Product, while contact hole 15 is formed on grid cabling 12 and polysilicon spacers 14a, contact hole 15 and gate metal are shorted, due to
Metallic resistance is much smaller than polysilicon resistance, and the pressure drop on grid cabling 12 and polysilicon spacers 14a can be ignored not substantially at this time
Meter, considerably increases the consistency that cellular is switched on or off, greatly reduces the loss of semiconductor devices, avoid the excessively electric of cellular
It is lost effect, increases the reliability of semiconductor devices, and grid finger 14 is located at the middle part of semiconductor devices, it is only necessary to a grid
Pole finger 14 can be realized, and can also realize the function of cellular in the lower section of grid finger 14, will not excessive chip occupying area
It causes to waste, preparation process is routinely simple, not will increase extra cost.
The foregoing is merely one embodiment of the present of invention, are not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
1. a kind of semiconductor devices, which is characterized in that it includes grid and gate metal layer, and the grid includes disposed in parallel
A plurality of polysilicon gate, the grid cabling for connecting the polysilicon gate and the gate liner, is located at described half at gate liner
The grid finger at the middle part of conductor device, the grid finger include multiple spaced polysilicon spacers, the polysilicon
The upper surface of two adjacent polysilicon gates of liner connection, the polysilicon spacers and the grid cabling offers contact
Hole, the contact hole is for filling the gate metal layer.
2. a kind of semiconductor devices according to claim 1, which is characterized in that the semiconductor devices further include:
Substrate；
It is formed in the epitaxial layer of the upper surface of the substrate；
The grid oxic horizon being formed between the upper surface of the substrate and the lower surface of the grid；
It is formed in the outside of the grid and is located at the dielectric layer of the upper surface of the epitaxial layer.
3. a kind of semiconductor devices according to claim 2, which is characterized in that the semiconductor devices further includes being covered on
The source metal of the top of the corresponding dielectric layer of the polysilicon gate and be formed in the substrate lower surface drain electrode gold
Belong to layer.
4. a kind of semiconductor devices according to claim 3, which is characterized in that the source metal and grid gold
The spacing for belonging to layer is 4-7 μm.
5. a kind of semiconductor devices according to claim 2, which is characterized in that the semiconductor devices further includes described in
The body area and extended in the body area from the upper surface in the body area that the upper surface of epitaxial layer extends to inside the epitaxial layer
The source region in portion.
6. a kind of semiconductor devices according to claim 1, which is characterized in that the width of the polysilicon gate be 7~
10 μm, the spacing between adjacent polysilicon grid is 7~10 μm.
7. a kind of semiconductor devices according to claim 1, which is characterized in that the length of the polysilicon spacers is 15-
20μm。
8. a kind of preparation method of semiconductor devices, which comprises the following steps:
S1: providing substrate, forms epitaxial layer in the upper surface of the substrate, forms initial oxidation in the upper surface of the epitaxial layer
Layer deposits one layer of polysilicon layer in the upper surface of the initial oxide layer；
S2: etch the polysilicon layer formed parallel a plurality of polysilicon gate, gate liner, the connection polysilicon gate and
The grid cabling of the gate liner, the grid finger positioned at the middle part of the semiconductor devices, the grid finger include more
A spaced polysilicon spacers, the polysilicon spacers connect two adjacent polysilicon gates；
S3: it injects and drives in form body area by autoregistration；
S4: the upper surface of the initial oxide layer between polysilicon gate is laid with source region photoresist, forms the first source region injection region
With the second source region injection region, first source region injection region is located at the two sides of grid finger and is located at polysilicon gate and the light
Between photoresist, second source region injection region between spaced gate liner, to first source region injection region with
Second source region injection region is injected and drives in form source region by autoregistration；
S5: etching the oxide layer and form spaced grid oxic horizon, in the outer of the grid oxic horizon and the grid
Side forms dielectric layer；
S6: contact hole is formed in the upper surface of the grid cabling and the grid finger；
S7: one layer of metal layer is deposited in the upper surface of the dielectric layer and the epitaxial layer, the metal layer is etched and forms interval
Gate metal layer and source metal.
9. a kind of preparation method of semiconductor devices according to claim 8, which is characterized in that also wrapped in the step S7
It includes and forms drain metal layer in the lower surface of the substrate.
10. a kind of preparation method of semiconductor devices according to claim 8, which is characterized in that in the step S6, institute
It states deposit metal in contact hole and is shorted with the gate metal layer.
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| CN1416178A (en) * | 2001-05-09 | 2003-05-07 | 株式会社东芝 | Semiconductor device |
| CN103579322A (en) * | 2013-11-13 | 2014-02-12 | 国家电网公司 | IGBT device capable of improving switch-on and switch-off speed and switch-on and switch-off uniformity and manufacturing method thereof |
| CN105122457A (en) * | 2013-03-31 | 2015-12-02 | 新电元工业株式会社 | Semiconductor device |
| US20160027736A1 (en) * | 2014-07-28 | 2016-01-28 | Renesas Electronics Corporation | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1416178A (en) * | 2001-05-09 | 2003-05-07 | 株式会社东芝 | Semiconductor device |
| CN105122457A (en) * | 2013-03-31 | 2015-12-02 | 新电元工业株式会社 | Semiconductor device |
| CN103579322A (en) * | 2013-11-13 | 2014-02-12 | 国家电网公司 | IGBT device capable of improving switch-on and switch-off speed and switch-on and switch-off uniformity and manufacturing method thereof |
| US20160027736A1 (en) * | 2014-07-28 | 2016-01-28 | Renesas Electronics Corporation | Semiconductor device |
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