CN109216352B - BCD semiconductor integrated device - Google Patents

BCD semiconductor integrated device Download PDF

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Publication number
CN109216352B
CN109216352B CN201811069367.3A CN201811069367A CN109216352B CN 109216352 B CN109216352 B CN 109216352B CN 201811069367 A CN201811069367 A CN 201811069367A CN 109216352 B CN109216352 B CN 109216352B
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well
layer
low
isolation
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CN109216352A (en
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乔明
叶力
朱旭晗
李珂
林祺
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a BCD semiconductor integrated device, which comprises 13 devices, wherein the 13 devices share a P-type substrate and an N-type epitaxial layer, and the electrical isolation between the devices is realized by an isolation electrode extending into a deep P-sink layer and a deep P-sink layer of the P-type substrate between each two parts, the invention utilizes an oxide layer medium of a low-threshold voltage MOS tube as a gate oxide layer of a low-threshold high-voltage power LDMOS device, sets a surface low-concentration well region of the low-threshold voltage MOS tube as a well region of the low-threshold high-voltage power LDMOS device, and leads a JFET (junction field effect transistor) in a mode that a gate electrode is arranged at a symmetrical axis to lead in a JFET (junction field effect transistor) to ensure that a current path of the low-threshold voltage LDMOS is different from a main PN junction bearing breakdown voltage, thereby avoiding the problem of early punch-through of the devices caused by the low-concentration well region, therefore, the invention utilizes the low-threshold MOS tube and, and any process menu and mask plate are not required to be added.

Description

BCD semiconductor integrated device
Technical Field
The invention belongs to the field of semiconductor power devices, and particularly relates to a BCD semiconductor device with compatible processes. The BCD semiconductor device integrates power LDMOS, CMOS, Bipolar, low-threshold NMOS, low-threshold PMOS, low-threshold LDMOS, power diodes and the like.
Background
With the increasing electric degree of industry, the requirement on high-voltage and high-current devices is higher and higher. Different application conditions have more and more requirements on the threshold voltage and the breakdown voltage of the device, the threshold voltage of the conventional LDMOS structure is generally more than 1.5V, and the threshold voltage of the low-threshold MOS tube can be as low as 0.1V or even less than 0.1V. The invention develops a BCD semiconductor device integrating a low-threshold LDMOS device based on a low-threshold voltage design of a high-voltage LDMOS device.
Disclosure of Invention
Aiming at the problem that the conventional BCD process platform cannot realize low threshold voltage, the BCD process platform integrated with the low-threshold LDMOS is developed by utilizing the characteristic of low threshold voltage of a low-voltage MOS structure.
The technical scheme adopted by the invention for solving the technical problems is as follows: the method comprises the steps of utilizing an oxide layer medium of a low-threshold-voltage MOS tube as a gate oxide layer of a low-threshold-voltage high-voltage LDMOS device, setting a surface low-concentration well region of the low-threshold-voltage MOS tube as a well region of the low-threshold-voltage high-voltage LDMOS device, and leading a JFET (junction field effect transistor) into a gate electrode at a symmetry axis, so that a low-threshold-voltage LDMOS current path is different from a main PN junction bearing breakdown voltage, and the problem of early punch-through of the device caused by the low-concentration well region.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a BCD semiconductor integrated device comprises 13 devices, namely a low-threshold nMOS (n-channel metal oxide semiconductor) tube 101, a low-threshold pMOS tube 102, a low-threshold nLDMOS (n-channel metal oxide semiconductor) tube 103, a low-threshold pLDMOS (p-channel metal oxide semiconductor) tube 104, an NMOS (n-channel metal oxide semiconductor) tube 105, a PMOS (p-channel metal oxide semiconductor) tube 106, an nLDMOS (n-channel metal oxide semiconductor) tube 107, a pLDMOS (p-channel metal oxide semiconductor) tube 108, a first NPN tube 109, a first PNP tube 110, a; the 13 devices share one P-type substrate 10 and one N-type epitaxial layer 9, and each part is electrically isolated from the other parts through an isolation electrode 30 extending into the P-type substrate 10 and above the deep P-sink layer 12:
the low-threshold nMOS transistor 101 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a low-concentration P well 4 formed on the surface of the N-type epitaxial layer 9 through ion implantation, two heavily doped N-type contacts 1 and a P-type contact 2 arranged on the inner surface of the low-concentration P well 4, an STI (shallow trench isolation) oxide layer 23 with the surface playing a role of isolation, a gate oxide layer 21 arranged on the surface of a semiconductor and connecting the two N-type contacts 1, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 and a drain electrode 33 respectively arranged above the two N-type contacts 1, and a body contact electrode 39 arranged on the P-type contact 2;
the low-threshold pMOS transistor 102 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a low-concentration N well 3 formed on the surface of the N-type epitaxial layer 9 through ion implantation, two heavily doped P-type contacts 2 and an N-type contact 1 which are arranged on the inner surface of the low-concentration N well 3, an STI (shallow trench isolation) oxide layer 23 with an isolation effect on the surface, a gate oxide layer 21 arranged on the surface of a semiconductor and used for connecting the two P-type contacts 2, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 and a drain electrode 33 respectively arranged above the two P-type contacts 2, and a body contact electrode 39 arranged on the N-type;
the low-threshold nLDMOS tube 103 includes: an N-type epitaxial layer 9 formed epitaxially on a P-type substrate 10, a second N-well 7 formed by diffusion on the surface of the N-type epitaxial layer 9, two low-concentration P wells 4 formed in a second N well 7 through ion implantation, wherein the two low-concentration P wells 4 are separated by the second N well 7, the inner surfaces of the low-concentration P wells 4 respectively comprise a heavily doped N-type contact 1 and a P-type contact 2 adjacent to the heavily doped N-type contact 1, the two N-type contacts 1 are respectively arranged on the surfaces of the left side and the right side of the second N well 7, an STI oxide layer 23 with an isolation effect is arranged on the surface, a gate oxide layer 21 is arranged on the surface of a semiconductor and connects the heavily doped N-type contacts 1 on the inner surfaces of the two low-concentration P wells 4, a gate electrode 31 is arranged on the gate oxide layer 21, a source electrode 32 is positioned above the N-type contact 1 on the surface of the low-concentration P well and the P-type contact 2 adjacent to the source electrode to short-circuit the source electrode, and a drain electrode 33 is;
low-threshold pLDMOS tube 104 includes: an N-type epitaxial layer 9 formed epitaxially on a P-type substrate 10, a second P-well 8 formed by diffusion on the surface of the N-type epitaxial layer 9, two low-concentration N wells 3 formed in a second P well 8 through ion implantation, wherein the two low-concentration N wells 3 are separated by the second P well 8, the inner surfaces of the low-concentration N wells 3 respectively comprise a heavily doped N-type contact 1 and a P-type contact 2 adjacent to the heavily doped N-type contact 1, two P-type contacts 2 respectively arranged on the surfaces of the left side and the right side of the second P well 8, an STI oxide layer 23 with an isolation effect on the surface, a gate oxide layer 21 is arranged on the surface of a semiconductor and connects the heavily doped P-type contacts 2 on the inner surfaces of the two low-concentration N wells 3, a gate electrode 31 is arranged on the gate oxide layer 21, a source electrode 32 is positioned above the N-type contact 1 on the surface of the low-concentration P well and the P-type contact 2 adjacent to the low-concentration N well and is in short circuit with the source electrode 32, and a drain electrode 33;
the NMOS transistor 105 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a first P well 6 formed on the surface of the N-type epitaxial layer 9 through ion implantation, two heavily doped N-type contacts 1 and one P-type contact 2 arranged on the inner surface of the first P well 6, an STI (shallow trench isolation) oxide layer 23 with the surface playing a role of isolation, a gate oxide layer 21 arranged on the surface of a semiconductor and connecting the two N-type contacts 1, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 and a drain electrode 33 respectively arranged above the two N-type contacts 1, and a body contact electrode 39 arranged on the P-type contact 2;
the PMOS transistor 106 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a first N-well 5 formed on the surface of the N-type epitaxial layer 9 through ion implantation, two heavily doped P-type contacts 2 and an N-type contact 1 which are arranged on the inner surface of the first N-well 5, an STI (shallow trench isolation) oxide layer 23 with the surface playing a role of isolation, a gate oxide layer 21 arranged on the surface of a semiconductor and connecting the two P-type contacts 2, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 and a drain electrode 33 respectively arranged above the two P-type contacts 2, and a body contact electrode 39 arranged on the N-type contact 1;
the nLDMOS transistor 107 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second N-well 7 formed on the surface of the N-type epitaxial layer 9 through diffusion, a first P-well 6 formed in the middle of the second N-well 7 through ion implantation, two heavily doped N-type contacts 1 arranged on the inner surface of the first P-well 6, a P-type contact 2 arranged between the two N-type contacts 1, two N-type contacts 1 respectively arranged on the surfaces of the left side and the right side of the second N-well 7, STI oxide layers 23 with the surfaces playing an isolating role, two gate oxide layers 21 both arranged on the surface of a semiconductor, a gate oxide layer 21 respectively covering the surfaces of the left side and the right side of the first P-well 6 and covering the part of the heavily doped N-type contacts 1 on the inner surface of the first P-well 6 and the surface of the second N-well 7, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 arranged on the surface of the first P-well 6 and above one P-, the two N-type contacts 1 and the P-type contact 2 between the two N-type contacts are in short circuit, and the drain electrode 33 is positioned on the surface of the N-type contact 1 of the second N well 7;
pLDMOS tube 108 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second P-well 8 formed on the surface of the N-type epitaxial layer 9 through diffusion, a first N-well 5 formed in the middle of the second P-well 8 through ion implantation, an N-type contact 1 arranged between two heavily doped P-type contacts 2 on the inner surface of the first N-well 5 and two P-type contacts 2, two P-type contacts 2 respectively arranged on the surfaces of the left side and the right side of the second P-well 8, STI oxide layers 23 with the surfaces playing an isolating role, two gate oxide layers 21 both arranged on the surface of a semiconductor, a gate oxide layer 21 respectively covering the surfaces of the left side and the right side of the first N-well 5 and covering the heavily doped P-type contacts 2 on the inner surface of the first N-well 5 and the surface of the second P-well 8, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 arranged on the surface of the first N-well 5 and one N-type contact 1 between the two, two P-type contacts 2 and one N-type contact 1 between the two P-type contacts are in short circuit, and a drain electrode is positioned on the surface of the P-type contact 2 of the second P well 8;
the first NPN transistor 109 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second N well 7 formed on the surface of the N-type epitaxial layer 9 through diffusion, a first P well 6 formed in the middle of the second N well 7 through ion implantation, an N-type contact 1 arranged on the inner surface of the first P well 6 in a heavily doped mode and a P-type contact 2 isolated from the first P well in a medium mode, an N-type contact 1 arranged on the inner surface of the second N well 7 in a heavily doped mode, an STI oxide layer 23 with the surface playing an isolating role, an emitter 38 arranged on the surface of the N-type contact 1 in the first P well 6, a base 36 arranged on the surface of the P-type contact 2 in the first P well 6 and a collector 37 arranged on the surface of the N-type contact 1 in the second N well 7;
the first type of PNP tube 110 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second P well 8 formed on the surface of the N-type epitaxial layer 9 through diffusion, a first N well 5 formed in the middle of the second P well 8 through ion implantation, an N-type contact 1 arranged on the inner surface of the first N well 5 in a heavily doped mode and a P-type contact 2 isolated from the first N well in a medium mode, a P-type contact 2 arranged on the inner surface of the second P well 8 in a heavily doped mode, an STI oxide layer 23 with the surface playing an isolation role, an emitter 38 arranged on the surface of the P-type contact 2 in the first N well 5, a base 36 arranged on the surface of the N-type contact 1 in the first N well 5 and a collector 37 arranged on the surface of the P-type contact 2 in the second P well 8;
the second NPN transistor 111 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second N-well 7 formed on the surface of the N-type epitaxial layer 9 through diffusion, a low-concentration P-well 4 formed in the middle of the second N-well 7 through ion implantation, an N-type contact 1 arranged on the inner surface of the low-concentration P-well 4 and heavily doped, a P-type contact 2 isolated from the N-type contact 1 through a medium, an N-type contact 1 arranged on the inner surface of the second N-well 7 and heavily doped, an STI oxide layer 23 with an isolation function on the surface, an emitter 38 arranged on the surface of the N-type contact 1 in the low-concentration P-well 4, a base 36 arranged on the surface of the P-type contact 2 in the low-concentration P-well 4, and a collector 37 arranged on the surface of the N;
the second type of PNP tube 112 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second P-well 8 formed on the surface of the N-type epitaxial layer 9 through diffusion, a low-concentration N-well 3 formed in the middle of the second P-well 8 through ion implantation, an N-type contact 1 arranged on the inner surface of the low-concentration N-well 3 and heavily doped, a P-type contact 2 isolated from the N-type contact 1 in a medium mode, a P-type contact 2 arranged on the inner surface of the second P-well 8 and heavily doped, an STI oxide layer 23 with the surface playing an isolating role, an emitter 38 arranged on the surface of the P-type contact 2 in the low-concentration N-well 3, a base 36 arranged on the surface of the N-type contact 1 in the low-concentration N-well 3, and a collector 37 arranged on the surface of the;
the power diode 113 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second P well 8 formed on the surface of the N-type epitaxial layer 9 through diffusion, an N-type contact 1 arranged on the inner surface of the second P well 8 in a heavily doped mode, a P-type contact 2 isolated from the N-type contact 1 in a medium mode, an STI oxide layer 23 with the surface playing a role in isolation, a cathode 35 arranged on the surface of the N-type contact 1 and an anode 34 arranged on the surface of the P-type contact 2.
As a preferred mode, the isolation mode among all devices is replaced by a mode of adopting a deep groove to etch and then filling a medium to realize isolation, the deep medium groove 20 is filled with an oxide layer and a silicon nitride medium, and the bottom of the deep medium groove 20 extends into the P-type substrate 10 or is tangent to the upper surface of the P-type substrate 10; the top of the deep trench 20 is connected to the STI oxide 23.
As the preferred mode, the isolation mode among each device is replaced by adopting an isolation ring, an N-type buried layer and an N-sink layer 11, each part is isolated by utilizing a reverse bias PN junction, an NBL layer 13 is arranged between a P-type substrate 10 and an N-type epitaxial layer 9, the isolation mode is realized by surface ion implantation or high-energy ion implantation before the N-type epitaxial layer 9 grows, the N-sink layer 11 is arranged between each device, the lower surface of the N-sink layer 11 extends into the NBL layer 13 or is tangent to the NBL layer, and the upper surface of the N-sink layer 11 penetrates through an STI oxide layer 23 and is led out of the surface through an isolation electrode 30; the positive high voltage applied by the isolation electrode 30 is transmitted to the NBL layer 13 through the N-sink layer 11, and the N-sink layer 11, the NBL layer 13 and the N-type epitaxial layer 9 form reverse bias PN solid device isolation.
As the preferred mode, the isolation mode among each device is replaced by adopting an isolation ring, an N-type buried layer and an N-sink layer 11, each part is isolated by utilizing a reverse bias PN junction, an NBL layer 13 is arranged between a P-type substrate 10 and a P-type epitaxial layer 14, the isolation mode is realized by surface ion implantation or high-energy ion implantation before the P-type epitaxial layer 14 grows, the N-sink layer 11 is arranged between each device, the lower surface of the N-sink layer 11 extends into the NBL layer 13 or is tangent to the NBL layer, and the upper surface of the N-sink layer 11 penetrates through an STI oxide layer 23 and is led out of the surface through an isolation electrode 30; the positive high voltage applied by the isolation electrode 30 is transmitted to the NBL layer 13 through the N-sink layer 11, and the N-sink layer 11, the NBL layer 13 and the P-type epitaxial layer 14 form reverse bias PN solid device isolation.
As a preferable mode, an SOI substrate is adopted, an oxide layer 24 is arranged between a P-type substrate 10 and an N-type epitaxial layer 9, the isolation mode between the devices is replaced by a deep groove etching mode, then a medium is filled to form a deep medium groove 20, the lower end face of the deep medium groove 20 is connected with the oxide layer 24, and the deep medium groove 20 and the oxide layer 24 jointly realize the isolation between the devices.
As a preferable mode, an SOI substrate is adopted, the epitaxial layer is a P-type epitaxial layer 14, an oxide layer 24 is arranged between the P-type substrate 10 and the P-type epitaxial layer 14, the isolation mode between the devices is replaced by adopting a deep groove etching mode and then filling a medium to form a deep medium groove 20, the lower end face of the deep medium groove 20 is connected with the oxide layer 24, and the deep medium groove 20 and the oxide layer 24 jointly realize the isolation between the devices.
As a preferred mode, the isolation of the device is realized by adopting a LOCOS thermal growth oxide layer.
Preferably, the P-sink and N-sink for isolation are formed by multiple implants.
Preferably, the low-threshold NMOS tube, the low-threshold PMOS tube, the low-threshold nLDMOS tube and the low-threshold pLDMOS tube use channel-adjusting injection to realize low concentration of a channel.
Preferably, the semiconductor material used is silicon or silicon carbide.
The working principle of the low-threshold power device integrated in the present embodiment is described below by taking the low-threshold nLDMOS as an example,
when the LDMOS is in an on state, the gate electrode 31 enables the surface carrier of the second N well 7 below to be inverted through an external voltage, and the electrons of the source electrode 32-N type contact 1-low concentration P well 4 surface inversion layer-JFET region-Nwell region-N type contact 1-drain electrode 33 are formed to move directionally, because the low concentration P well 4 is low in concentration, the gate oxide layer 21 is thin, and the threshold voltage of the device can be reduced to be lower than 0.1V; when the LDMOS is in an off state, the voltages applied to the gate electrode 31 and the source electrode 32 are 0, the high voltage is applied to the drain electrode 33, the voltage is mainly dropped to the PN junction of the second N well 7 and the low concentration P well 4, the device can not punch through by adjusting the width of the low concentration P well 4, and finally the LDMOS device with high breakdown voltage and low threshold voltage is realized.
The working principle of the low-threshold pLDMOS is similar.
The invention has the beneficial effects that: by utilizing the low-threshold MOS tube and the conventional LDMOS in the conventional BCD process platform, the low-threshold LDMOS with completely compatible process is realized without adding any process menu and mask.
Drawings
Fig. 1 shows a BCD semiconductor integrated device of embodiment 1;
fig. 2 shows a BCD semiconductor integrated device of embodiment 2;
fig. 3 shows a BCD semiconductor integrated device of embodiment 3;
fig. 4 shows a BCD semiconductor integrated device of embodiment 4;
fig. 5 shows a BCD semiconductor integrated device of embodiment 5;
fig. 6 shows a BCD semiconductor integrated device of embodiment 6;
fig. 7 shows a BCD semiconductor integrated device of embodiment 7.
The power diode comprises a power diode, a first NPN tube, a second PNP tube, a third PNP tube, a fourth PNP tube;
1 is N type contact, 2 is P type contact, 3 is low concentration N trap, 4 is low concentration P trap, 5 is first N trap, 6 is first P trap, 7 is second N trap, 8 is second P trap, 9 is N type epitaxial layer, 10 is P type substrate, 11 is N-sink layer, 12 is dark P-sink layer, 13 is NBL layer, 14 is P type epitaxial layer, 20 is deep dielectric groove, 21 is gate oxide, 23 is STI oxide layer, 24 is the oxide layer, 30 is the isolated electrode: 31 is a gate electrode, 32 is a source electrode, 33 is a drain electrode, 34 is an anode, 35 is a cathode, 36 is a base, 37 is a collector, 38 is an emitter, 39 is a body contact electrode, 41 is a channel injection low concentration N-type region, and 42 is a channel injection low concentration P-type region.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
As shown in fig. 1, a BCD semiconductor integrated device is characterized by including 13 devices, which are respectively: a low-threshold nMOS tube 101, a low-threshold pMOS tube 102, a low-threshold nLDMOS tube 103, a low-threshold pLDMOS tube 104, an NMOS tube 105, a PMOS tube 106, an nLDMOS tube 107, a pLDMOS tube 108, a first NPN tube 109, a first PNP tube 110, a second NPN tube 111, a second PNP tube 112 and a power diode 113; the 13 devices share one P-type substrate 10 and one N-type epitaxial layer 9, and each part is electrically isolated from the other parts through an isolation electrode 30 extending into the P-type substrate 10 and above the deep P-sink layer 12:
the low-threshold nMOS transistor 101 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a low-concentration P well 4 formed on the surface of the N-type epitaxial layer 9 through ion implantation, two heavily doped N-type contacts 1 and a P-type contact 2 arranged on the inner surface of the low-concentration P well 4, an STI (shallow trench isolation) oxide layer 23 with the surface playing a role of isolation, a gate oxide layer 21 arranged on the surface of a semiconductor and connecting the two N-type contacts 1, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 and a drain electrode 33 respectively arranged above the two N-type contacts 1, and a body contact electrode 39 arranged on the P-type contact 2;
the low-threshold pMOS transistor 102 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a low-concentration N well 3 formed on the surface of the N-type epitaxial layer 9 through ion implantation, two heavily doped P-type contacts 2 and an N-type contact 1 which are arranged on the inner surface of the low-concentration N well 3, an STI (shallow trench isolation) oxide layer 23 with an isolation effect on the surface, a gate oxide layer 21 arranged on the surface of a semiconductor and used for connecting the two P-type contacts 2, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 and a drain electrode 33 respectively arranged above the two P-type contacts 2, and a body contact electrode 39 arranged on the N-type;
the low-threshold nLDMOS tube 103 includes: an N-type epitaxial layer 9 formed epitaxially on a P-type substrate 10, a second N-well 7 formed by diffusion on the surface of the N-type epitaxial layer 9, two low-concentration P wells 4 formed in a second N well 7 through ion implantation, wherein the two low-concentration P wells 4 are separated by the second N well 7, the inner surfaces of the low-concentration P wells 4 respectively comprise a heavily doped N-type contact 1 and a P-type contact 2 adjacent to the heavily doped N-type contact 1, the two N-type contacts 1 respectively arranged on the surfaces of the left side and the right side of the second N well 7, an STI oxide layer 23 with an isolation effect on the surface, a gate oxide layer 21 arranged on the surface of a semiconductor and connecting the two N-type contacts 1, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 arranged above the N-type contact 1 on the surface of the low-concentration P well and the P-type contact 2 adjacent to the N-type contact 1 to the surface of the low-concentration P well to short-circuit the N-type contact 1, and;
low-threshold pLDMOS tube 104 includes: an N-type epitaxial layer 9 formed epitaxially on a P-type substrate 10, a second P-well 8 formed by diffusion on the surface of the N-type epitaxial layer 9, two low-concentration N wells 3 formed in a second P well 8 through ion implantation, wherein the two low-concentration N wells 3 are separated by the second P well 8, the inner surfaces of the low-concentration N wells 3 respectively comprise a heavily doped N-type contact 1 and a P-type contact 2 adjacent to the heavily doped N-type contact 1, two P-type contacts 2 respectively arranged on the surfaces of the left side and the right side of the second P well 8, an STI oxide layer 23 with an isolation effect on the surface, a gate oxide layer 21 arranged on the surface of a semiconductor and connecting the two P-type contacts 2, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 arranged above the N-type contact 1 on the surface of the low-concentration P well and the P-type contact 2 adjacent to the N-type contact 1 and short-connected to the N-type contact 2, and a drain electrode 33 arranged on the surface of the P;
the NMOS transistor 105 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a first P well 6 formed on the surface of the N-type epitaxial layer 9 through ion implantation, two heavily doped N-type contacts 1 and one P-type contact 2 arranged on the inner surface of the first P well 6, an STI (shallow trench isolation) oxide layer 23 with the surface playing a role of isolation, a gate oxide layer 21 arranged on the surface of a semiconductor and connecting the two N-type contacts 1, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 and a drain electrode 33 respectively arranged above the two N-type contacts 1, and a body contact electrode 39 arranged on the P-type contact 2;
the PMOS transistor 106 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a first N-well 5 formed on the surface of the N-type epitaxial layer 9 through ion implantation, two heavily doped P-type contacts 2 and an N-type contact 1 which are arranged on the inner surface of the first N-well 5, an STI (shallow trench isolation) oxide layer 23 with the surface playing a role of isolation, a gate oxide layer 21 arranged on the surface of a semiconductor and connecting the two P-type contacts 2, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 and a drain electrode 33 respectively arranged above the two P-type contacts 2, and a body contact electrode 39 arranged on the N-type contact 1;
the nLDMOS transistor 107 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second N-well 7 formed on the surface of the N-type epitaxial layer 9 through diffusion, a first P-well 6 formed in the middle of the second N-well 7 through ion implantation, two heavily doped N-type contacts 1 arranged on the inner surface of the first P-well 6, a P-type contact 2 arranged between the two N-type contacts 1, two N-type contacts 1 respectively arranged on the surfaces of the left side and the right side of the second N-well 7, STI oxide layers 23 with the surfaces playing an isolating role, two gate oxide layers 21 both arranged on the surface of a semiconductor, a gate oxide layer 21 respectively covering the surfaces of the left side and the right side of the first P-well 6 and covering the part of the heavily doped N-type contacts 1 on the inner surface of the first P-well 6 and the surface of the second N-well 7, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 arranged on the surface of the first P-well 6 and above one P-, the two N-type contacts 1 and the P-type contact 2 between the two N-type contacts are in short circuit, and the drain electrode 33 is positioned on the surface of the N-type contact 1 of the second N well 7;
pLDMOS tube 108 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second P-well 8 formed on the surface of the N-type epitaxial layer 9 through diffusion, a first N-well 5 formed in the middle of the second P-well 8 through ion implantation, an N-type contact 1 arranged between two heavily doped P-type contacts 2 on the inner surface of the first N-well 5 and two P-type contacts 2, two P-type contacts 2 respectively arranged on the surfaces of the left side and the right side of the second P-well 8, STI oxide layers 23 with the surfaces playing an isolating role, two gate oxide layers 21 both arranged on the surface of a semiconductor, a gate oxide layer 21 respectively covering the surfaces of the left side and the right side of the first N-well 5 and covering the partial heavily doped P-type contacts 2 on the inner surface of the first N-well 5 and the surface of the second P-well 8, a gate electrode 31 arranged on the gate oxide layer 21, a source electrode 32 arranged on the surface of the first N-well 5 and above one N-type contact 1, two P-type contacts 2 and one N-type contact 1 between the two P-type contacts are in short circuit, and a drain electrode is positioned on the surface of the P-type contact 2 of the second P well 8;
the first NPN transistor 109 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second N well 7 formed on the surface of the N-type epitaxial layer 9 through diffusion, a first P well 6 formed in the middle of the second N well 7 through ion implantation, an N-type contact 1 arranged on the inner surface of the first P well 6 in a heavily doped mode and a P-type contact 2 isolated from the first P well in a medium mode, an N-type contact 1 arranged on the inner surface of the second N well 7 in a heavily doped mode, an STI oxide layer 23 with the surface playing an isolating role, an emitter 38 arranged on the surface of the N-type contact 1 in the first P well 6, a base 36 arranged on the surface of the P-type contact 2 in the first P well 6 and a collector 37 arranged on the surface of the N-type contact 1 in the second N well 7;
the first type of PNP tube 110 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second P well 8 formed on the surface of the N-type epitaxial layer 9 through diffusion, a first N well 5 formed in the middle of the second P well 8 through ion implantation, an N-type contact 1 arranged on the inner surface of the first N well 5 in a heavily doped mode and a P-type contact 2 isolated from the first N well in a medium mode, a P-type contact 2 arranged on the inner surface of the second P well 8 in a heavily doped mode, an STI oxide layer 23 with the surface playing an isolation role, an emitter 38 arranged on the surface of the P-type contact 2 in the first N well 5, a base 36 arranged on the surface of the N-type contact 1 in the first N well 5 and a collector 37 arranged on the surface of the P-type contact 2 in the second P well 8;
the second NPN transistor 111 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second N-well 7 formed on the surface of the N-type epitaxial layer 9 through diffusion, a low-concentration P-well 4 formed in the middle of the second N-well 7 through ion implantation, an N-type contact 1 arranged on the inner surface of the low-concentration P-well 4 and heavily doped, a P-type contact 2 isolated from the N-type contact 1 through a medium, an N-type contact 1 arranged on the inner surface of the second N-well 7 and heavily doped, an STI oxide layer 23 with an isolation function on the surface, an emitter 38 arranged on the surface of the N-type contact 1 in the low-concentration P-well 4, a base 36 arranged on the surface of the P-type contact 2 in the low-concentration P-well 4, and a collector 37 arranged on the surface of the N;
the second type of PNP tube 112 includes: an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second P-well 8 formed on the surface of the N-type epitaxial layer 9 through diffusion, a low-concentration N-well 3 formed in the middle of the second P-well 8 through ion implantation, an N-type contact 1 arranged on the inner surface of the low-concentration N-well 3 and heavily doped, a P-type contact 2 isolated from the N-type contact 1 in a medium mode, a P-type contact 2 arranged on the inner surface of the second P-well 8 and heavily doped, an STI oxide layer 23 with the surface playing an isolating role, an emitter 38 arranged on the surface of the P-type contact 2 in the low-concentration N-well 3, a base 36 arranged on the surface of the N-type contact 1 in the low-concentration N-well 3, and a collector 37 arranged on the surface of the;
the power diode 113 includes: the semiconductor device comprises an N-type epitaxial layer 9 formed on a P-type substrate 10 in an epitaxial mode, a second P well 8 formed on the surface of the N-type epitaxial layer 9 through diffusion, an N-type contact 1 arranged on the inner surface of the second P well 8 in a heavily doped mode, a P-type contact 2 isolated from the N-type contact 1 in a medium mode, an STI oxide layer 23 with the surface playing a role in isolation, a cathode 35 arranged on the surface of the N-type contact 1 and an anode 34 arranged on the surface of the P-type contact 2.
In this embodiment, the low-threshold LDMOS and the low-threshold MOS transistor share the same gate oxide layer process and the same well region, and the low-threshold voltage is realized by the low-concentration well region to enhance the control of the gate electrode on the channel carriers. The low-threshold LDMOS device is generally short in channel, a JFET (junction field effect transistor) area is formed below a gate electrode by arranging the gate electrode in the center of the device, so that the short-channel effect can be effectively reduced, the voltage resistance and the current in the conduction direction of the device are different, and the device is prevented from being broken through and broken down. The present embodiment defines only the doping species for the low concentration N-well 3 and the low concentration P-well 4. The conventional LDMOS and low-threshold LDMOS drift regions are formed by ion implantation, and a second N-well 7 is formed by ion implantation of N-type impurities and a second P-well 8 is formed by P-type impurities, generally, the second N-well 7 is deeper than the low-concentration P-well 4 and the first P-well 6, and the second P-well 8 is deeper than the low-concentration N-well 3 and the first N-well 5. In this embodiment, the depth contrast between the low concentration N well 3 and the low concentration P well 4, the depth contrast between the first N well 5 and the first P well 6, the depth contrast between the second N well 7 and the second P well 8, and the depth contrast between the N-type contact 1 and the P-type contact 2 are not limited, and may be designed by a specific process.
Example 2
As shown in fig. 2, a BCD semiconductor device of the present embodiment is different from embodiment 1 in that: the isolation mode among each device is that a deep groove is etched and then is filled with a medium to realize isolation, the deep medium groove 20 is filled with an oxide layer and a silicon nitride medium, and the bottom of the deep medium groove 20 extends into the P-type substrate 10 or is tangent to the upper surface of the P-type substrate 10; the top of the deep trench 20 is connected to the STI oxide 23.
Example 3
As shown in fig. 3, a BCD semiconductor device of the present embodiment is different from embodiment 1 in that: the isolation mode among each device adopts an isolation ring, an N-type buried layer and an N-sink layer 11, each part is isolated by utilizing a reverse bias PN junction, an NBL layer 13 is arranged between a P-type substrate 10 and an N-type epitaxial layer 9, the isolation mode is realized by surface ion implantation or high-energy ion implantation before the growth of the N-type epitaxial layer 9, the N-sink layer 11 is arranged between each device, the lower surface of the N-sink layer 11 extends into the NBL layer 13 or is tangent to the NBL layer, and the upper surface of the N-sink layer 11 penetrates through an STI oxide layer 23 and is led out of the surface through an isolation electrode 30; the positive high voltage applied by the isolation electrode 30 is transmitted to the NBL layer 13 through the N-sink layer 11, and the N-sink layer 11, the NBL layer 13 and the N-type epitaxial layer 9 form reverse bias PN solid device isolation.
Example 4
As shown in fig. 4, a BCD semiconductor device of the present embodiment is different from embodiment 1 in that: the N-type epitaxial layer 9 is replaced by a P-type epitaxial layer 14, an isolation mode among all devices adopts an isolation ring, an N-type buried layer and an N-sink layer 11, each part is isolated by utilizing a reverse bias PN junction, an NBL layer 13 is arranged between a P-type substrate 10 and the P-type epitaxial layer 14, the isolation mode is realized by surface ion implantation before the P-type epitaxial layer 14 grows or high-energy ion implantation, the N-sink layer 11 is arranged among all the devices, the lower surface of the N-sink layer 11 extends into the NBL layer 13 or is tangent to the NBL layer, and the upper surface of the N-sink layer 11 penetrates through an STI oxide layer 23 and is led out of the surface through an isolation electrode 30; the positive high voltage applied by the isolation electrode 30 is transmitted to the NBL layer 13 through the N-sink layer 11, and the N-sink layer 11, the NBL layer 13 and the P-type epitaxial layer 14 form reverse bias PN solid device isolation.
Example 5
As shown in fig. 5, a BCD semiconductor device of the present embodiment is different from embodiment 1 in that: in this embodiment, an SOI (Silicon-On-Insulator) substrate is used, an oxide layer 24 is disposed between a P-type substrate 10 and an N-type epitaxial layer 9, deep trenches are etched between the devices and then filled with a medium to form deep dielectric trenches 20, the lower end surfaces of the deep dielectric trenches 20 are connected to the oxide layer 24, and the deep dielectric trenches 20 and the oxide layer 24 jointly realize isolation between the devices.
Example 6
As shown in fig. 6, a BCD semiconductor device of the present embodiment is different from embodiment 1 in that: an SOI substrate is adopted, the epitaxial layer is a P-type epitaxial layer 14, an oxide layer 24 is arranged between the P-type substrate 10 and the P-type epitaxial layer 14, deep grooves are adopted among devices, deep grooves are etched and filled with media to form deep dielectric grooves 20, the lower end faces of the deep dielectric grooves 20 are connected with the oxide layer 24, and the deep dielectric grooves 20 and the oxide layer 24 jointly realize isolation among the devices.
Example 7
As shown in fig. 7, a BCD semiconductor device of the present embodiment is different from embodiment 1 in that: the channel injection low-concentration P-type region 42 is arranged between the upper surface of the low-concentration P well 4 in the low-threshold nMOS tube 101 and the low-threshold nLDMOS tube 103 and the lower surface of the gate oxide layer 21, and the channel injection low-concentration N-type region 41 is arranged between the upper surface of the low-concentration N well 3 in the low-threshold pMOS tube 102 and the low-threshold pLDMOS tube 104 and the lower surface of the gate oxide layer 21.
It is worth noting that:
the core of the protection required by the invention is a low-threshold-voltage transverse high-voltage power device compatible with a BCD (bipolar-CMOS-Dp) process, a gate oxide layer forming process and a well region injection process related to the threshold voltage of a low-threshold-voltage NMOS (N-channel metal oxide semiconductor) tube compatible with the BCD process and the device are applied to the conventional LDMOS device manufacturing process, the problem of punch-through breakdown is solved, the low-threshold-voltage high-voltage LDMOS device capable of meeting the withstand voltage requirement is realized, the implementation process is completely compatible with the conventional BCD process, and a mask is not added.
The N-sink layer and the P-sink layer for isolation can be combined with multiple times of injection and other injection processes used by the platform to realize the improvement of the carrier concentration of the sink layer when the process is realized;
when the epitaxial layer is of an N type, the N type epitaxial layer 9 can be used as a drift region of the nLDMOS; similarly, when the epitaxial layer is P-type, the P-type epitaxial layer 14 can be used as a drift region of the pLDMOS;
the isolation of each part of the device surface included in the invention can also realize isolation by growing a field oxide layer through a LOCOS process, besides adopting STI in the embodiment.
The semiconductor material used in the invention is Si, and the semiconductor material is also suitable for other semiconductor materials.

Claims (10)

1. A BCD semiconductor integrated device is characterized by comprising 13 devices which are respectively as follows: the transistor comprises a low-threshold nMOS (101), a low-threshold pMOS (102), a low-threshold nLDMOS (103), a low-threshold pLDMOS (104), an NMOS (105), a PMOS (106), an nLDMOS (107), a pLDMOS (108), a first NPN (109), a first PNP (110), a second NPN (111), a second PNP (112) and a power diode (113); the 13 devices share a P-type substrate (10) and an N-type epitaxial layer (9), and each part is electrically isolated from the other parts through an isolation electrode (30) extending into a deep P-sink layer (12) of the P-type substrate (10) and above the deep P-sink layer (12):
the low-threshold nMOS transistor (101) includes: the transistor comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a low-concentration P well (4) formed on the surface of the N-type epitaxial layer (9) through ion implantation, two heavily doped N-type contacts (1) and a P-type contact (2) arranged on the inner surface of the low-concentration P well (4), and an STI (shallow trench isolation) oxide layer (23) with the surface having an isolation effect, wherein a gate oxide layer (21) is arranged on the surface of a semiconductor and connects the two N-type contacts (1), a gate electrode (31) is arranged on the gate oxide layer (21), a source electrode (32) and a drain electrode (33) are respectively arranged above the two N-type contacts (1), and a body contact electrode (39) is arranged on the P-type;
the low-threshold pMOS tube (102) includes: the field-effect transistor comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a low-concentration N well (3) formed on the surface of the N-type epitaxial layer (9) through ion implantation, two heavily doped P-type contacts (2) and an N-type contact (1) which are arranged on the inner surface of the low-concentration N well (3), an STI (shallow trench isolation) oxide layer (23) with the surface playing a role in isolation, a gate oxide layer (21) arranged on the surface of a semiconductor and connecting the two P-type contacts (2), a gate electrode (31) arranged on the gate oxide layer (21), a source electrode (32) and a drain electrode (33) respectively arranged above the two P-type contacts (2), and a body contact electrode (39) arranged on the N-type;
the low-threshold nLDMOS transistor (103) comprises: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second N well (7) formed on the surface of the N-type epitaxial layer (9) through diffusion, two low-concentration P wells (4) formed in the second N well (7) through ion implantation, the two low-concentration P wells (4) are separated by the second N well (7), the inner surfaces of the low-concentration P wells (4) respectively comprise a heavily doped N-type contact (1) and a P-type contact (2) adjacent to the heavily doped N-type contact (1), the two N-type contacts (1) arranged on the left side surface and the right side surface of the second N well (7) respectively, STI (shallow trench isolation) oxide layers (23) with surfaces playing an isolating role, a gate oxide layer (21) is arranged on the surface of a semiconductor and is connected with the heavily doped N-type contacts (1) on the inner surfaces of the two low-concentration P wells (4), a gate electrode (31) is arranged on the gate oxide layer (21), and a source electrode (32) is arranged above the N-type contact Short-circuiting the N-type contact, wherein the drain electrode (33) is positioned on the surface of the N-type contact (1) of the second N-well (7);
the low-threshold pLDMOS transistor (104) comprises: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, two low-concentration N wells (3) formed in the second P well (8) through ion implantation, the two low-concentration N wells (3) are separated by the second P well (8), the inner surfaces of the low-concentration N wells (3) respectively comprise a heavily doped N-type contact (1) and a P-type contact (2) adjacent to the heavily doped N-type contact (1), the two P-type contacts (2) respectively arranged on the left side surface and the right side surface of the second P well (8), STI (shallow trench isolation) oxide layers (23) with surfaces playing an isolating role, a gate oxide layer (21) is arranged on the surface of a semiconductor and is connected with the heavily doped P-type contacts (2) on the inner surfaces of the two low-concentration N wells (3), a gate electrode (31) is arranged on the gate oxide layer (21), and a source electrode (32) is arranged above the N-type contact ( Short-circuiting the drain electrode (33), and locating the drain electrode on the surface of the P-type contact (2) in the second P well (8);
the NMOS transistor (105) includes: the transistor comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a first P well (6) formed on the surface of the N-type epitaxial layer (9) through ion implantation, two heavily doped N-type contacts (1) and a P-type contact (2) arranged on the inner surface of the first P well (6), and an STI (shallow trench isolation) oxide layer (23) with the surface having an isolation effect, wherein a gate oxide layer (21) is arranged on the surface of a semiconductor and connects the two N-type contacts (1), a gate electrode (31) is arranged on the gate oxide layer (21), a source electrode (32) and a drain electrode (33) are respectively arranged above the two N-type contacts (1), and a body contact electrode (39) is arranged on the P-type contact (2);
the PMOS tube (106) comprises: the field-effect transistor comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a first N well (5) formed on the surface of the N-type epitaxial layer (9) through ion implantation, two heavily doped P-type contacts (2) and an N-type contact (1) which are arranged on the inner surface of the first N well (5), an STI (shallow trench isolation) oxide layer (23) with the surface playing a role in isolation, a gate oxide layer (21) arranged on the surface of a semiconductor and used for connecting the two P-type contacts (2), a gate electrode (31) arranged on the gate oxide layer (21), a source electrode (32) and a drain electrode (33) respectively arranged above the two P-type contacts (2), and a body contact electrode (39) arranged on the N-type contact (;
the nLDMOS tube (107) comprises: an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second N-well (7) formed on the surface of the N-type epitaxial layer (9) through diffusion, a first P-well (6) formed in the middle of the second N-well (7) through ion implantation, two heavily doped N-type contacts (1) arranged on the inner surface of the first P-well (6) and one P-type contact (2) between the two N-type contacts (1), two N-type contacts (1) respectively arranged on the left side surface and the right side surface of the second N-well (7), STI oxide layers (23) with isolation functions on the surfaces, two gate oxide layers (21) are arranged on the surface of a semiconductor, the gate oxide layers (21) respectively cover the surfaces on the left side and the right side of the first P-well (6) and cover the surfaces of the heavily doped part N-type contacts (1) and the surface of the second N-well (7) in the inner surface of the first P-well (6), a gate electrode (, the source electrode (32) is positioned above the two N-type contacts (1) on the surface of the first P well (6) and one P-type contact (2) between the two N-type contacts (1), the two N-type contacts (1) and the P-type contact (2) between the two N-type contacts are in short circuit, and the drain electrode (33) is positioned on the surface of the N-type contact (1) of the second N well (7);
the pLDMOS tube (108) includes: an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P-well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, a first N-well (5) formed in the middle of the second P-well (8) through ion implantation, two heavily doped P-type contacts (2) arranged on the inner surface of the first N-well (5) and one N-type contact (1) between the two P-type contacts (2), two P-type contacts (2) respectively arranged on the left side surface and the right side surface of the second P-well (8), STI oxide layers (23) with isolation functions on the surfaces, two gate oxide layers (21) are arranged on the surface of a semiconductor, the gate oxide layers (21) respectively cover the surfaces on the left side and the right side of the first N-well (5) and cover the surfaces of the heavily doped part P-type contacts (2) and the surface of the second P-well (8) on the inner surface of the first N-well (5), a gate electrode (, the source electrode (32) is positioned above the two P-type contacts (2) on the surface of the first N well (5) and one N-type contact (1) between the two P-type contacts (2), the two P-type contacts (2) and the N-type contact (1) between the two P-type contacts are in short circuit, and the drain electrode is positioned on the surface of the P-type contact (2) of the second P well (8);
the first type of NPN tube (109) includes: the manufacturing method comprises the steps of forming an N-type epitaxial layer (9) on a P-type substrate (10) in an epitaxial mode, forming a second N well (7) on the surface of the N-type epitaxial layer (9) through diffusion, forming a first P well (6) in the middle of the second N well (7) through ion implantation, placing an N-type contact (1) heavily doped on the inner surface of the first P well (6) and a P-type contact (2) isolated from the first P well in a medium mode, placing an N-type contact (1) heavily doped on the inner surface of the second N well (7), forming an STI (shallow trench isolation) oxide layer (23) with the surface playing an isolating role, placing an emitter (38) on the surface of the N-type contact (1) in the first P well (6), placing a base (36) on the surface of the P-type contact (2) in the first P well (6), and placing a collector (37) on the surface of the N-type contact;
the first type of PNP tube (110) includes: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, a first N well (5) formed in the middle of the second P well (8) through ion implantation, an N-type contact (1) heavily doped on the inner surface of the first N well (5) and a P-type contact (2) isolated from the N-type contact with a medium, a P-type contact (2) heavily doped on the inner surface of the second P well (8), an STI oxide layer (23) with the surface playing an isolating role, an emitter (38) arranged on the surface of the P-type contact (2) in the first N well (5), a base (36) arranged on the surface of the N-type contact (1) in the first N well (5), and a collector (37) arranged on the surface of the P-type contact (2) in the second P well (8);
the second NPN tube (111) comprises: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second N-well (7) formed on the surface of the N-type epitaxial layer (9) through diffusion, a low-concentration P-well (4) formed in the middle of the second N-well (7) through ion implantation, an N-type contact (1) arranged on the inner surface of the low-concentration P-well (4) in a heavily doped mode and a P-type contact (2) isolated from the N-type contact with a medium, an N-type contact (1) arranged on the inner surface of the second N-well (7) in a heavily doped mode, an STI oxide layer (23) with the surface playing an isolating role, an emitter (38) arranged on the surface of the N-type contact (1) in the low-concentration P-well (4), a base (36) arranged on the surface of the P-type contact (2) in the low-concentration P-well (4), and a collector;
a second type of PNP tube (112) includes: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, a low-concentration N well (3) formed in the middle of the second P well (8) through ion implantation, an N-type contact (1) arranged on the inner surface of the low-concentration N well (3) in a heavily doped mode and a P-type contact (2) isolated from the N-type contact in a medium mode, a P-type contact (2) arranged on the inner surface of the second P well (8) in a heavily doped mode, an STI oxide layer (23) with the surface playing an isolating role, an emitter (38) arranged on the surface of the P-type contact (2) in the low-concentration N well (3), a base (36) arranged on the surface of the N-type contact (1) in the low-concentration N well (3), and a collector (37) arranged on the;
the power diode (113) comprises: the structure comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, an N-type contact (1) arranged on the inner surface of the second P well (8) in heavy doping and a P-type contact (2) isolated from the N-type contact, an STI (shallow trench isolation) oxide layer (23) with the surface playing an isolation role, a cathode (35) arranged on the surface of the N-type contact (1) and an anode (34) arranged on the surface of the P-type contact (2).
2. The BCD semiconductor integrated device according to claim 1, wherein: the isolation mode among all devices is replaced by the mode of filling a medium after deep groove etching to realize isolation, the deep medium groove (20) is filled with an oxide layer and a silicon nitride medium, and the bottom of the deep medium groove (20) extends into the P-type substrate (10) or is tangent to the upper surface of the P-type substrate (10); the top of the deep dielectric groove (20) is connected with the STI oxide layer (23).
3. A BCD semiconductor integrated device according to claim 1, characterized in that: the isolation mode among each device is replaced by an isolation ring, an N-type buried layer and an N-sink layer (11), each part is isolated by utilizing a reverse bias PN junction, an NBL layer (13) is arranged between a P-type substrate (10) and an N-type epitaxial layer (9), the isolation mode is realized by surface ion implantation before the growth of the N-type epitaxial layer (9) or high-energy ion implantation, the N-sink layer (11) is arranged between each device, the lower surface of the N-sink layer (11) extends into the NBL layer (13) or is tangent to the NBL layer, and the upper surface penetrates through an STI oxide layer (23) and is led out of the surface through an isolation electrode (30); the isolation electrode (30) is applied with positive high voltage and is transmitted to the NBL layer (13) through the N-sink layer (11), and the N-sink layer (11), the NBL layer (13) and the N-type epitaxial layer (9) form reverse bias PN solid existing device isolation.
4. The BCD semiconductor integrated device according to claim 1, wherein: the isolation mode among each device is replaced by adopting an isolation ring, an N-type buried layer and an N-sink layer (11), each part is isolated by utilizing a reverse bias PN junction, an NBL layer (13) is arranged between a P-type substrate (10) and a P-type epitaxial layer (14), the isolation mode is realized by surface ion implantation before the growth of the P-type epitaxial layer (14) or high-energy ion implantation, the N-sink layer (11) is arranged between each device, the lower surface of the N-sink layer (11) extends into the NBL layer (13) or is tangent to the NBL layer, and the upper surface of the N-sink layer (11) penetrates through an STI oxide layer (23) and is led out of the surface through an isolation electrode (30); the isolation electrode (30) is applied with positive high voltage and is transmitted to the NBL layer (13) through the N-sink layer (11), and the N-sink layer (11), the NBL layer (13) and the P-type epitaxial layer (14) form reverse bias PN solid existing device isolation.
5. The BCD semiconductor integrated device according to claim 1, wherein: an SOI substrate is adopted, an oxide layer (24) is arranged between a P-type substrate (10) and an N-type epitaxial layer (9), the isolation mode between devices is replaced by a deep groove etching mode, a medium is filled into the deep groove etching mode to form a deep medium groove (20), the lower end face of the deep medium groove (20) is connected with the oxide layer (24), and the deep medium groove (20) and the oxide layer (24) jointly realize isolation between the devices.
6. The BCD semiconductor integrated device according to claim 1, wherein: an SOI substrate is adopted, the epitaxial layer is a P-type epitaxial layer (14), an oxide layer (24) is arranged between the P-type substrate (10) and the P-type epitaxial layer (14), the isolation mode between devices is replaced by adopting a deep groove to etch and then fill a medium to form a deep medium groove (20), the lower end face of the deep medium groove (20) is connected with the oxide layer (24), and the deep medium groove (20) and the oxide layer (24) realize isolation between the devices together.
7. A BCD semiconductor integrated device according to any of claims 1-6, characterized in that: and the STI oxide layer (23) with the surface playing the role of isolation is replaced by a LOCOS thermal growth oxide layer to realize the device isolation.
8. The BCD semiconductor integrated device according to claim 1, wherein: the P-sink for isolation is formed by multiple implants.
9. A BCD semiconductor integrated device according to any of claims 1-6, characterized in that: the low-threshold NMOS tube, the low-threshold PMOS tube, the low-threshold nLDMOS tube and the low-threshold pLDMOS tube use channel adjusting injection to realize low concentration of a channel.
10. A BCD semiconductor integrated device according to any of claims 1-6, characterized in that: the semiconductor material used is silicon or silicon carbide.
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CN101764100A (en) * 2008-12-25 2010-06-30 上海先进半导体制造股份有限公司 Vertical bipolar device manufacture process compatible to BCD integrated manufacture process
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