CN109216301B - Phase-change heat dissipation chip structure and preparation method thereof - Google Patents

Phase-change heat dissipation chip structure and preparation method thereof Download PDF

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CN109216301B
CN109216301B CN201811081424.XA CN201811081424A CN109216301B CN 109216301 B CN109216301 B CN 109216301B CN 201811081424 A CN201811081424 A CN 201811081424A CN 109216301 B CN109216301 B CN 109216301B
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wafer
phase
phase change
heat dissipation
cavity
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CN109216301A (en
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陈达
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China Core Integrated Circuit Ningbo Co Ltd
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China Core Integrated Circuit Ningbo Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes
    • H01L23/4275—Cooling by change of state, e.g. use of heat pipes by melting or evaporation of solids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A phase change heat dissipation chip structure and a preparation method thereof are provided, the phase change heat dissipation chip structure comprises: a cover plate and a wafer; the lower surface of the cover plate is bonded with the back surface of the wafer, the lower surface of the cover plate is provided with a cavity, the back surface of the wafer is provided with a hollow groove, the cavity is communicated with the hollow groove, and phase-change materials are stored in the cavity or the hollow groove; the phase-change material is filled in the cavity or the empty groove, the phase-change material absorbs heat to be changed into liquid or gas state, the volume of the phase-change material expands, the phase-change material with the expanded volume generates pressure on the chip and the cover plate, the reliability of the chip is further influenced, the cavity of the cover plate provides a space for storing the phase-change material with the expanded volume, the stress between the chip and the cover plate is reduced, and the reliability of the chip is improved.

Description

Phase-change heat dissipation chip structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a phase change heat dissipation chip structure, a single-chip wafer-level preparation method and a wafer-level system packaging preparation method thereof.
Background
The heat management mode of the chip is divided into active heat dissipation and passive heat dissipation, and the passive heat dissipation comprises the following steps: heat conduction (heat sink); the initiative heat dissipation includes: phase change heat dissipation, liquid metal heat dissipation, microchannel heat dissipation, thermoelectric heat dissipation and forced air cooling; in the power semiconductor, as the size of a single chip is reduced and the power is increased, the unit heat flux generated therewith is rapidly increased.
In the three-dimensional package, a large amount of heat is accumulated in a package body along with the integrated stacking of various chips. Conventionally, forced air cooling of a chip through a heat sink can discharge only 60% of generated waste heat at most, and the air cooling requires additional power consumption, and there is noise.
The phase change heat dissipation technology is a technology for releasing phase change latent heat by utilizing substance phase change. Experimental data show that the phase change mode has the capability of radiating heat by multiple times or even tens of times higher than that of simple temperature difference. The phase-change material can store or release a large amount of heat in the phase-change process, and the phase-change process is approximately isothermal, so that the chip can be effectively protected from overheating. Meanwhile, the device has the advantages of small volume, light weight, reliable performance, economy, no energy consumption and the like.
The chip generates heat in the working process, the phase-change material in the cavity at the back of the chip, which is close to the heating end of the chip, is changed from a solid state to a liquid state or from the liquid state to a vapor state to absorb the heat, and the phase-change material close to the cold end of the cover plate is changed from the liquid state to the solid state or from the vapor state to the liquid state to release the heat, so that a heat conduction cycle is formed. The active heat dissipation process of the chip is continuously completed in such a reciprocating way, and the high-heat-conductivity phase-change material plays a role of a heat transfer medium, so that the purpose of quickly dissipating heat of the integrated circuit chip is realized, the running speed and the efficiency are effectively improved, the running reliability is improved, and the service life is prolonged.
In the prior art, the back of a chip is filled with a phase-change material, the phase-change material undergoes phase change to cause volume expansion, so that the chip generates stress and the reliability of the chip is easily caused.
Disclosure of Invention
The invention aims to solve the problems that in the prior art, the phase change material filled in a chip generates phase change expansion, so that the chip is easy to generate stress, and the phase change expanded material releases heat quickly, and the like.
In order to achieve the above object, a phase change heat dissipation chip structure is provided, which includes a cover plate and a wafer:
the lower surface of the cover plate is bonded with the back of the wafer, a cavity is formed in the lower surface of the cover plate, an empty groove is formed in the back of the wafer, the cavity is communicated with the empty groove, and phase change materials are stored in the cavity or the empty groove.
Optionally, the cover plate further comprises a heat sink disposed on the upper surface of the cover plate.
Optionally, a heat transfer medium is disposed between the heat sink and the upper surface of the cover plate.
Optionally, the semiconductor device further comprises a conductive bump, wherein the conductive bump is attached to the front surface of the wafer.
Optionally, the width of the cavity is greater than or equal to the width of the empty slot.
Optionally, the cavity is comprised of a plurality of voids.
Optionally, the diameter of the void is greater than 1 um.
Optionally, the cover plate is made of a bonded wafer.
Optionally, a solder is provided at the bonding position of the cover plate and the wafer.
According to an aspect of the present invention, a method for manufacturing a phase change heat dissipation chip at a wafer level is provided, which includes:
providing a wafer, etching the back of the wafer to form a plurality of empty grooves, wherein the depth of each empty groove does not touch a deep well region close to the wafer;
providing a cover plate with the same size as the wafer, and etching the lower surface of the cover plate to form a plurality of cavities;
placing a phase change material in the empty groove or the cavity;
the cavity corresponds to the empty groove in position, and the lower surface of the cover plate is bonded with the back surface of the wafer.
Optionally, the method further comprises: and a heat transfer medium is arranged on the upper surface of the cover plate, and a heat sink is arranged on the heat transfer medium.
Optionally, before the heat transfer medium is disposed on the upper surface of the cover plate, the method further includes: and thinning the upper surface of the cover plate.
Optionally, before etching the back surface of the wafer and forming the plurality of empty slots, the method further includes: and thinning the back of the wafer.
Optionally, the method further comprises: and mounting a conductive bump on the front surface of the wafer.
Optionally, the bonded structure is cut to obtain a plurality of phase change heat dissipation chip structures.
Optionally, the cavity is comprised of a plurality of etched voids.
Optionally, the phase change material is disposed in the empty groove or the cavity by a low-speed spin coating method.
Optionally, the method further comprises: and exposing the hot spot area of the wafer.
Optionally, the empty slot covers the hot spot region.
Optionally, the etching is plasma reactive etching.
According to another aspect of the present invention, a method for manufacturing a phase change heat dissipation wafer level system package is provided, including:
providing a first wafer and a plurality of bare chips, arranging an interlayer medium on the back surface of the first wafer, and pasting the front surfaces of the plurality of bare chips which are spaced to the back surface of the first wafer;
etching the back surface of each bare chip to form a hollow groove;
the molding material is molded into a second wafer with a plurality of cavity structures on the lower surface, and the cavities correspond to the empty slots in position;
bonding a lower surface of the second wafer with a back side of the plurality of dies;
etching the front surface of the first wafer at a position corresponding to the bonding pad of the bare chip till the first wafer exposes the bonding pad of the bare chip to form a through hole;
and filling a conductive material in the through hole to form a conductive plug so as to realize the electrical connection with the bare chip.
Optionally, after the front side of the plurality of dies spaced apart is pasted to the back side of the first wafer, before etching the back side of each of the dies and forming the empty slot, the method further includes: and filling the gaps between the bare chips by injection molding to form a plastic packaging layer covering the side walls of the bare chips and the interlayer medium.
Optionally, before etching the front surface of the first wafer at a position corresponding to the pad of the die, the method further includes: and thinning or removing the front surface of the first wafer. Optionally, after filling a conductive material in the through hole and forming a conductive plug, the method further includes: a rewiring layer is disposed on the conductive plug.
Optionally, the method further comprises: attaching conductive bumps on the conductive plug or on the redistribution layer, the conductive bumps in electrical communication with the die.
Optionally, the method further comprises: and arranging a heat transfer medium on the upper surface of the second wafer, and arranging a heat sink on the heat transfer medium.
Optionally, before disposing the heat transfer medium on the upper surface of the second wafer, the method further includes: and thinning the upper surface of the second wafer.
Optionally, the cavity is comprised of a plurality of etched voids.
Optionally, the phase change material is disposed in the empty groove or the cavity by a low-speed spin coating method.
Optionally, after the phase change heat dissipation wafer level system is packaged, the phase change heat dissipation wafer level system is divided into a plurality of modules with a plurality of dies as a group, and each module forms a system capable of providing multiple functions.
The invention has the beneficial effects that:
1. the lower surface of the cover plate is provided with the cavity, the back surface of the wafer is provided with the empty groove, the phase-change material is filled in the cavity or the empty groove, when the phase-change material absorbs heat to generate phase change, the heat is released, and the volume is expanded, the cavity is communicated with the empty groove, so that the expandable space of the phase-change material is enlarged, the pressure on the chip and the cover plate after the phase-change material is expanded is reduced, and the reliability of the chip is improved.
2. The invention relates to a phase change heat dissipation wafer level system packaging preparation method, which combines a wafer level packaging method with a system packaging method, etches the backs of a plurality of bare chips adhered to an interlayer medium of a first wafer to form empty slots, molds a molding material into a second wafer with a plurality of cavity structures on the lower surface, the cavities correspond to the empty slots in position, arranges a phase change material in the cavities or the empty slots, bonds the lower surface of the second wafer with the backs of the bare chips, forms conductive plugs at the positions corresponding to welding pads of the bare chips to realize the electric communication of the bare chips, packages and integrates a plurality of groups of chips on the wafer, can reduce the area of a packaging structure, can improve the heat dissipation efficiency of the wafer level system packaging structure, optimizes the electrical property of the chips and reduces the manufacturing cost.
The apparatus of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts.
Fig. 1 is a phase change heat sink chip structure according to one embodiment of the present invention.
Fig. 2 is a phase change heat sink chip structure according to an embodiment of the invention.
Fig. 3 is another phase change heat sink chip structure according to an embodiment of the invention.
FIG. 4 is a flow chart of a phase change thermal wafer level fabrication method according to one embodiment of the present invention.
Fig. 5(a) -5 (F) are schematic structural diagrams of different stages in a phase change heat dissipation wafer level manufacturing process according to an embodiment of the invention.
FIG. 6 is a flow chart of a method for manufacturing a phase change heat dissipation wafer level system package according to an embodiment of the invention.
Fig. 7(a) -7 (L) are schematic structural diagrams of different stages in a phase change thermal wafer level SIP manufacturing process according to an embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
According to an embodiment of the present invention, a phase change heat dissipation chip structure is provided, which includes a cover plate and a wafer:
referring to fig. 1, the lower surface of a cover plate 5 is bonded to the back surface of a wafer 6, a cavity 7 is formed in the lower surface of the cover plate 5, a cavity 8 is formed in the back surface of the wafer 6, the cavity 7 is communicated with the cavity 8, and a phase change material is stored in the cavity 7 or the cavity 8.
The main improvement direction of phase change heat dissipation at the present stage is to improve the heat transfer capacity of the phase change material, a proper phase change material is selected according to a phase change temperature point, and the phase change material generates solid-to-liquid transition or liquid-to-gas transition after absorbing heat, so that the slow temperature rise of the chip is maintained.
The solid phase-change material fills the cavity 7 or the empty groove 8, and changes into liquid after absorbing heat, and expands in volume, and if the cover plate 5 has no cavity, the phase-change material forming the liquid phase will generate pressure on the wafer 6 and the cover plate 5, thereby affecting the reliability of the chip. If the phase change material becomes gaseous, there is also the problem of pressure being generated on the wafer 6 and the cover plate 5. The cavity 7 of the cover plate 5 provides a space for storing the phase-change material after volume expansion, reduces stress between the wafer 6 and the cover plate 5, and improves chip reliability.
Specifically, the phase change material includes inorganic hydrous salts, inorganic substances, organic substances, inorganic composite materials, and the like. Wherein the upper limit temperature of the n-eicosane is controlled at 50 ℃; the melting point of the paraffin is close to the working temperature of the electronic device; the paraffin composite material is formed by adding high heat conduction materials into paraffin.
As an alternative, a heat sink 9 is further included, the heat sink 9 is arranged on the upper surface of the cover plate 5, and a heat transfer medium is arranged between the heat sink 9 and the upper surface of the cover plate 5.
Optionally, the heat transfer medium is an epoxy glue with silver ions.
Specifically, the upper end of the cover plate 5 is a cold end, and the interface heat transfer medium and the heat sink 9 are sequentially prepared on the upper surface of the cover plate 5, so that heat exchange between the phase-change material and the outside is promoted, and efficient heat dissipation of the phase-change material is realized.
Alternatively, a conductive bump 11 is further included, and the conductive bump 11 is attached to the front surface of the chip 6.
Alternatively, the width of the cavity 7 may be greater than or equal to the width of the empty slot 8, see fig. 2.
Specifically, the width of the cavity 7 is greater than the width of the empty slot 8, so that the bonding precision requirement of the wafer and the cover plate 5 is reduced, the heat exchange area between the cavity 7 and the heat sink 9 is larger, and the heat exchange capacity between the phase-change material after state transition and the outside is improved.
Specifically, the edge of the cavity 7 is spaced from the edge of the empty groove 8 by 1um or more depending on the actual chip size.
Alternatively, the cavity 7 is composed of a plurality of hollows, see fig. 3.
Specifically, the plurality of cavities may be uniformly distributed, or may be distributed in a hot spot concentration area at a high density, or randomly distributed in other areas.
Specifically, the depths of the plurality of cavities may be the same or different, for example, the depth of the cavity in the hot spot concentration region may be deeper, and the diameter of the cavity may be determined according to the size of the chip and the requirement of the heat dissipation efficiency.
Alternatively, the diameter of the void is greater than 1 um.
Alternatively, the cover plate 5 may be made of silicon, germanium, ceramic, glass, metal, or an organic material, or the like.
According to an embodiment of the present invention, a method for manufacturing a phase change heat dissipation chip at a wafer level is provided according to a phase change heat dissipation chip structure, including the following steps:
step 1: providing a wafer 201, etching the back surface of the wafer 201 to form a plurality of empty grooves 203, wherein the depth of the empty grooves 203 does not reach the deep well region close to the wafer 201, and referring to fig. 5 (a);
alternatively, before etching the back surface of the wafer 201 and forming the plurality of empty slots 203, the method further includes: the back surface of the wafer 201 is thinned to a predetermined thickness.
Performing photoetching on the back surface of the wafer 201; with the patterned mask layer as a mask, the mask layer may include: a hard mask material and a photoresist mask material. And exposing a hot spot area of the wafer 201, engraving a pattern on the mask plate to the surface of the processed wafer 201, and etching the wafer 201 by a dry etching process or a wet etching process.
Specifically, the etching process may be a plasma dry etching process, and the chlorine-containing or fluorine-containing gas discharge generates a chemically active plasma etching gas, the etching gas contains a large amount of active radicals, and the active radicals combine with silicon atoms to form volatile silicon chloride or silicon fluoride molecules when deposited on the exposed wafer 201, so as to transfer the pattern of the photoresist to the wafer 201 therebelow.
For example using a material such as CF4、CF3、C4F6And etching with fluorine-containing gas as etching gas.
In one example, a reactive ion dry etch process is used: the etching gas comprises CF4、CF3One or two kinds of helium gas and helium gas, wherein the flow of the etching gas is 10-800 sccm, the etching gas pressure is 200-800 mtorr, and the radio frequency power is 300-1000 w.
Specifically, the size of the single empty groove 203 is not larger than that of the single chip, or the empty groove 203 covers a hot spot area, and the depth of the empty groove 203 does not reach a deep well area.
Step 2: providing a cover plate 202 with the same size as the wafer 201, and etching the lower surface of the cover plate 202 to form a plurality of cavities 204, referring to fig. 5 (B);
specifically, the cover plate 202 is the same size as the wafer 201, and in one example, the cover plate 202 is made of a silicon wafer.
Firstly, photoetching is carried out on the cover plate 202; in one example, a patterned photoresist layer is formed on the lower surface of the cover plate 202, the cover plate 202 is irradiated with ultraviolet rays for a certain time by using the photoresist layer as a mask layer, and the photolithography process of the cover plate 202 is completed by glue coating, exposure, development, drying, and the like.
Then etching the cover plate 202 after photoetching; the etching may be performed by wet, dry etching or laser, and a plurality of cavities 204 with a certain depth are formed on the lower surface of the cover plate.
Specifically, a plasma dry etching process is adopted, in one example, the etching pressure is 200-800 mtorr, the radio frequency power is 300-1000 w, and the etching gas is CF4、CF3Wherein the flow rate of the etching gas is 10-50 sccm.
The depth of the cavity 204 is preset, the width of the cavity 204 is equal to or larger than the width of the empty groove 203, and when the width of the cavity 204 of the cover plate 202 is larger than the width of the empty groove 203, the distance between the edge of the cavity 204 and the edge of the empty groove 203 is more than 1um, so that the precision requirement of the bonding of the wafer 201 and the cover plate 202 is reduced, the contact surface is increased, and the heat exchange capacity of the phase-change material and the outside is improved.
Optionally, the cavity 204 is comprised of a plurality of etched voids. A plurality of holes with certain depth are formed by etching the lower surface of the cover plate 202, the depth of the holes is consistent with that of the cavities, and the diameter of the holes is larger than 1 um. And the bonding surface of the lower surface of the cover plate 202 is subjected to plasma activation treatment to improve the surface adhesion.
Specifically, the plurality of cavities may be uniformly distributed, or may be distributed in a hot spot concentration area at a high density, or randomly distributed in other areas.
Specifically, the depth of the cavity 204 is determined by the thickness of the cover plate.
Optionally, the eight inch cover plate 202 has a thickness of 725um and the upper portion of the cavity 204 corresponds to a cover plate thickness of less than 50 um.
And step 3: placing a phase change material in the empty groove 203 or the cavity 204, see fig. 5 (C);
in this embodiment, the liquid phase-change material is uniformly disposed in the empty trench 202 or the cavity 204 by low-speed spin coating, and the solid phase-change material is liquefied by heating, then spin-coated at low speed, and cooled and solidified.
And 4, step 4: the cavity 204 corresponds to the position of the cavity 203, and bonds the lower surface of the lid plate 202 to the back surface of the wafer 201, see fig. 5 (D).
The bonding surface of the lower surface of the cover plate 202 is firstly subjected to plasma activation treatment to improve the surface adhesion.
And aligning the lower surface of the cover plate 202 with the back surface of the wafer 201, and uniformly corresponding each cavity 204 to the position of each empty groove 203 for carrying out vacuum low-temperature bonding.
Optionally, the bonding manner of the lower surface of the cover plate 202 and the back surface of the wafer 201 depends on the material of the cover plate 202.
Optionally, the cover plate 202 and the wafer 201 are welded by vacuum low temperature bonding or alloy eutectic bonding.
And 5: the upper surface of the lid plate 202 is thinned, a heat transfer medium is provided on the upper surface of the lid plate 202, and a heat sink 205 is provided on the heat transfer medium, see fig. 5 (E).
The upper surface of the cover plate 202 is thinned, so that the heat exchange capacity between the phase change material and the outside can be improved, the heat exchange between the phase change material and the outside can be further promoted by arranging the heat transfer medium and the heat sink 205 on the upper surface of the cover plate 202, and the efficient heat radiation performance of the phase change material is realized.
The thinning process may use any suitable mechanical grinding process, chemical mechanical grinding process, or etching process, etc. The thickness of the thinned wafer 201 or the thinned cover plate 202 can be set reasonably according to the actual process.
Step 6: conductive bumps 206 are mounted on the front surface of the wafer 201, as shown in fig. 5 (F).
Specifically, the formed conductive bump 206 may be classified into a solder ball bump, a gold bump, a polymer bump, or other suitable conductive bump 206 structures according to different materials.
The solder bump manufacturing technology can mount the bumps by electroplating, printing and metal injection on the wiring layer.
And 7: and cutting the bonded structure to obtain a plurality of phase-change heat-dissipation chip structures.
Specifically, the wafer-level structure of the prepared phase-change heat dissipation chip is cut to obtain the phase-change heat dissipation chip structure.
According to another embodiment of the present invention, a method for manufacturing a phase change heat dissipation wafer level system package is provided.
System In Package (SIP) is a combination of multiple active components with different functions, passive components, micro-electromechanical systems (MEMS), and optical components, among other components, into a unit to form a system or subsystem that can provide multiple functions, allowing heterogeneous IC (integrated circuit) integration, which is the best way to package integration. Compared to the system-on-chip SOC, SIP integration has the advantages of being relatively simple, shorter in design cycle and market cycle, and lower in cost, and SIP can implement more complex systems. Compared with the traditional SIP, the wafer level system packaging is a packaging and integrating process completed on the wafer, has the advantages of greatly reducing the area of a packaging structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment.
The method comprises the following steps:
step 1: providing a first wafer 102 and a plurality of dies 101, disposing an interlayer medium 112 on the back surface of the first wafer 102, and attaching the plurality of spaced dies 101 to the back surface of the first wafer 102, as shown in fig. 7 (a);
specifically, an interlayer dielectric 112 is disposed between the first wafer 102 and the die 101, and the interlayer dielectric is an insulating layer. The interlayer dielectric 112 may be silicon dioxide, borophosphosilicate glass, phosphosilicate glass, polymer material, silicon nitride, or the like.
Specifically, the dies 101 are attached to the first wafer 102 in a spaced array arrangement by the die attach adhesive 110.
Multiple dies 101 may have the same or different functions therebetween and multiple dies 101 may have the same or different dimensions therebetween. The actual number, function, and size of die 101 is determined by design requirements and is not limited.
Alternatively, after the front side of a plurality of dies 101 spaced apart from each other is pasted to the back side of the first wafer 102, before etching the back side of each die 101 and forming the empty slot 103, the method further includes: the gap between the die 101 and the die 101 is filled by injection molding to form a molding layer 113 covering the sidewall of the die 101 and the interlayer dielectric 112, and the surface after injection molding is trimmed.
Specifically, the first wafer 102 with the die 101 attached thereto is placed in an injection molding machine, and injection molding is performed with thermosetting plastic (epoxy resin), so that the gap between the die 101 and the die 101 on the first wafer 102 can be filled by injection molding, and the surface of the die 101 is trimmed after injection molding, as shown in fig. 7 (B).
The injection molding process uses a liquid molding compound (MoldCompound) or a solid molding compound, wherein the liquid molding compound is preferably used to fill the gap between the adjacent dies 101 before curing, thereby increasing the adhesion between the adjacent dies 101 and improving the stability of the package.
Step 2: etching the back surface of each die 101 to form a cavity 103, see fig. 7 (C);
specifically, a patterned mask layer covers each die 101, and the background of each die 101 is subjected to photolithography through operations such as exposure, development, drying and the like; and carrying out plasma reactive etching on the bare chip 101 after photoetching to form the empty groove 103, wherein the depth of the empty groove 103 does not touch the deep well region of the bare chip 101.
And step 3: molding a molding material into a second wafer 105 having a structure with a plurality of cavities 104 on a lower surface thereof, wherein the cavities 104 correspond to the empty slots 103, as shown in fig. 7 (D);
specifically, the diameter of the first wafer 102 is the same as the diameter of the second wafer 105.
Specifically, before the molding material is solidified, a plurality of cavity 104 structures are prepared by a mold, and a carrier wafer 109 is attached to the upper surface of the second wafer 105 for supporting and fixing the second wafer 105 and ensuring the flatness of the injection-molded second wafer 105.
In one example, the cavity 104 is comprised of a plurality of etched voids.
Specifically, a plurality of holes can be evenly distributed, also can be in the big density distribution of hot spot concentration district, or other regional random distribution, and the degree of depth of hole is unanimous with the degree of depth of cavity 104, and the diameter of hole is greater than 1 um.
Specifically, the depth of the cavity 104 is determined according to the thickness of the second wafer 105.
And 4, step 4: a phase change material is provided in the cavity 104 or the empty groove 103, see fig. 7 (E);
the liquid phase-change material is arranged in the empty groove 103 or the cavity 104 through modes such as low-speed spin coating, and the solid phase-change material is arranged in the empty groove 103 or the cavity 104 through modes such as heating, liquefying, then performing low-speed spin coating, cooling and solidifying.
And 5: bonding the lower surface of the second wafer 105 to the back surfaces of the plurality of dies 101, see fig. 7 (F);
the lower surface of the second wafer 105 is aligned with the back surface of the die 101, each cavity 103 corresponds to the position of the cavity 104, and vacuum low temperature bonding is performed.
Step 6: the front side of the first wafer 102 is thinned or the first wafer 102 is removed, see fig. 7 (G).
Specifically, the first wafer 102 is used to support a plurality of dies 101 fixedly spaced apart from each other and attached to the interlayer dielectric 112 on the wafer back side of the first wafer 102.
And 7: etching the front surface of the first wafer 102 at a position corresponding to the bonding pad of the die 101, until the bonding pad of the die 102 is exposed from the first wafer 102, to form a through hole 106, as shown in fig. 7 (H);
specifically, after the front side of the first wafer 102 is thinned, a groove is etched at a position of the first wafer 102 corresponding to each die 101, where the etching depth includes etching the interlayer dielectric 112 between the first wafer 102 and the die 101.
Specifically, the interlayer dielectric 112 is dry etched by using plasma, which specifically includes the following steps: the etching pressure is 100-1000 mtorr, the radio frequency power is 1000-3000W, and the etching gas is C4F6The carrier gas is argon. Wherein the flow rate of the etching gas is 10-500 sccm, and the flow rate of the argon gas is 200-1500 sccm.
Specifically, the etching gas further includes CF4，CF4The flow rate of the gas is 10-1000 sccm, which can reduce the polymer layer formed during the etching process of the interlayer dielectric 112 to a depth where the first wafer 102 exposes the bonding pad of the die 101, thereby ensuring the etching depth of the through hole 106.
In one example, the diameter of the via 106 is less than 500 um.
And 8: conductive material is filled in the via 106 to form a conductive plug 107 for electrical connection with the die 101.
Specifically, a metal oxide or passivation layer is deposited first, followed by a metal deposition within the via 106.
Specifically, the metal is deposited as a peptide or copper, and the via hole 106 is filled by an electroplating process to form the conductive plug 107.
Alternatively, the conductive plug is formed in a process consistent with a conventional Complementary Metal Oxide Semiconductor (CMOS) process.
Alternatively, after the conductive material is filled in the via hole 106 and the conductive plug 107 is formed, the method further includes: a redistribution layer is disposed on the conductive plug 107 to electrically connect the conductive material filled in the via hole 106.
And step 9: a conductive bump 108 is attached on the conductive plug 107 or on the redistribution layer, and the conductive bump 108 is electrically communicated with the die 101, refer to fig. 7 (I).
Specifically, through-silicon-via technology is used to fabricate an electrical connection channel vertically penetrating through the wafer, and an electrode is led out through the electrical connection channel, so that the die 101 is electrically connected with the conductive bump 108.
Step 10: the carrier wafer 109 on the upper surface of the second wafer 105 is removed, referring to fig. 7(J), and the upper surface of the second wafer 105 is thinned to a predetermined thickness, so as to maintain the heat transfer performance of the phase change material inside the cavity 104 or the cavity 103, referring to fig. 7 (K).
Step 11: a heat transfer medium is provided on the upper surface of the second wafer 105, a heat sink 114 is provided on the heat transfer medium, and the wafer level system package is diced, see fig. 7 (L).
Step 12: after the phase change heat dissipation wafer level system is packaged, the phase change heat dissipation wafer level system is divided into a plurality of modules with a plurality of bare chips as a group, and each module forms a system capable of providing multiple functions.
Specifically, after the phase change heat dissipation wafer level system packaging is completed, a dicing process may be performed on the first wafer 102 along dicing streets to separate the plurality of dies 101 integrated on the first wafer 102 into independent modules, for example, each module includes a structure of phase change heat dissipation and heat sink heat dissipation, and the modules form a system or subsystem that can provide multiple functions, which depend on the functions of the actually integrated chips.
Example 1
Fig. 1 is a phase change heat sink chip structure according to an embodiment of the present invention, fig. 2 is a phase change heat sink chip structure according to an embodiment of the present invention, and fig. 3 is another phase change heat sink chip structure according to an embodiment of the present invention.
As shown in fig. 1, the embodiment provides a phase change heat dissipation chip structure, which includes a cover plate 5 and a wafer 6:
the lower surface of the cover plate 5 is bonded with the back surface of the wafer 6, a cavity 7 is arranged on the lower surface of the cover plate 5, a hollow groove 8 is arranged on the back surface of the wafer 6, the cavity 7 is communicated with the hollow groove 8, and phase-change materials are stored in the cavity 7 or the hollow groove 8.
The structure also comprises a heat sink 9, wherein the heat sink 9 is arranged on the upper surface of the cover plate 5; and the chip also comprises a conductive bump 11, and the conductive bump 11 is attached to the front surface of the chip 6. The cover plate 5 is made of a silicon wafer, and the bonding part of the cover plate 5 and the wafer 6 is provided with solder 4.
As shown in fig. 2, the width of the cavity 7 is greater than the width of the empty groove 8.
As shown in fig. 3, the cavity 7 is composed of a plurality of hollows having a diameter larger than 1 um.
Through setting up cavity 7 at the lower surface of apron 5, set up dead slot 8 at the back of wafer 6, after phase change material filled cavity 7 or dead slot 8, phase change material heat absorption took place the phase transition, and volume expansion, the expandable space of phase change material increases, and the pressure to wafer 6 and apron 5 after the phase change material inflation that reduces to improve the reliability of chip.
Example 2
FIG. 4 is a flow chart of a phase change thermal wafer level fabrication method according to one embodiment of the present invention. Fig. 5(a) -5 (F) are schematic structural diagrams of different stages in a phase change heat dissipation wafer level manufacturing process according to an embodiment of the invention.
As shown in fig. 4, the present embodiment provides a phase change heat dissipation wafer level manufacturing method, which includes the following steps:
step 101: providing a wafer 201, etching the back surface of the wafer 101 to form a plurality of empty slots 103, wherein the depth of the empty slot 203 does not reach the deep well region close to the wafer 201, as shown in fig. 5 (a);
etching the back surface of the wafer 201, and before forming a plurality of empty grooves 203, thinning the back surface of the wafer 201;
step 102: providing a cover plate 202 with the same size as the wafer 201, and etching the lower surface of the cover plate 202 to form a plurality of cavities 204, as shown in fig. 5 (B);
the wafer 201 and the cover plate 202 are subjected to photoetching by performing operations such as exposure, development, drying and the like on hot spot areas of the wafer 201 and the cover plate 202, and then plasma reaction etching is performed.
Firstly, photoresist is coated on a wafer 201 and a cover plate 202, a mask plate is covered on the wafer 201 and the cover plate 102, then the wafer is irradiated for a certain time by ultraviolet rays through the mask plate, and the photoresist at specific parts of the wafer 201 and the cover plate 202 is subjected to chemical reaction by the ultraviolet rays, so that the surfaces of partial chips are exposed. Then, the wafer 201 and the cover plate 202 are subjected to a plasma reaction dry etching process by using a chlorine or fluorine-containing etching gas, and the pattern of the photoresist is transferred to the wafer therebelow.
Step 103: placing a phase change material in the empty groove 203, as shown in fig. 5 (C);
the liquid phase-change material is arranged in the empty groove 203 in a low-speed spin coating mode, and the solid phase-change material is arranged in the empty groove 203 in a cooling solidification mode after being liquefied by heating.
Step 104: the cavity 204 corresponds to the position of the empty groove 203, and bonds the lower surface of the cover plate 202 to the back surface of the wafer 201, as shown in fig. 5 (D).
The bonding surface of the lower surface of the cover plate 202 is firstly subjected to plasma activation treatment to improve the surface adhesion.
The lower surface of the cover plate 202 is aligned with the back surface of the wafer 201, and vacuum low-temperature bonding is performed.
Step 105: the upper surface of the lid plate 202 is thinned, and a heat transfer medium is provided on the upper surface of the lid plate 202, and a heat sink 205 is provided on the heat transfer medium, as shown in fig. 5 (E).
Step 106: the conductive bumps 206 are attached to the front surface of the wafer 201, as shown in fig. 5 (F).
When the conductive bumps 206 are solder balls (e.g., solder balls), the solder balls can be placed on the front surface of the wafer 201 by a ball-mounting process.
Step 107: and cutting the bonded structure to obtain a plurality of phase-change heat-dissipation chip structures.
And cutting the prepared wafer-level structure of the phase-change heat dissipation chip to obtain the phase-change heat dissipation chip structure.
Example 3
Fig. 6 is a flowchart of a method for manufacturing a phase change heat dissipation wafer level system package according to an embodiment of the present invention, and fig. 7(a) -7 (L) are schematic structural diagrams of different stages in a process for manufacturing a phase change heat dissipation wafer level system package according to an embodiment of the present invention.
As shown in fig. 6, the embodiment provides a method for manufacturing a phase change heat dissipation wafer level system package, including:
step 201: providing a first wafer 102 and a plurality of dies 101, arranging an interlayer medium 112 on the back surface of the first wafer 102, and pasting the front surfaces of the plurality of spaced dies 101 to the back surface of the first wafer 102;
as shown in fig. 7(a), an interlayer dielectric 112 is disposed between the first wafer 102 and the die 101, the die 101 is attached to the wafer 102 by a die attach adhesive 110, and the interlayer dielectric 112 is made of a silicon dioxide material.
The gap between the die 101 and the die 101 is filled by injection molding to form a molding layer 113 covering the sidewall of the die 101 and the interlayer dielectric 112, and the surface after injection molding is trimmed, as shown in fig. 7 (B).
The injection molding mode is as follows: the die-attached first wafer is placed in an injection molding machine, a molding layer 113 is injection molded by thermosetting plastic (epoxy resin), and the surface of the molding layer is trimmed after injection molding.
Step 202: the back side of each die 101 is etched to form empty slots 103.
As shown in fig. 7(C), each die 101 is subjected to plasma reactive etching to form empty trench 103, and the depth of empty trench 103 does not reach the deep well region of die 101.
Step 203: injection molding the molding material into a second wafer 105 with a structure that the lower surface of the second wafer is provided with a plurality of cavities 104, wherein the cavities 104 correspond to the positions of the empty grooves 103;
the molding material is cured to form a cavity 104 structure through a mold, and a carrier wafer 109 is disposed on the top surface of the second wafer 105, as shown in fig. 7 (D).
Step 204: a phase change material is provided within the empty trench 103.
As shown in fig. 7(E), the liquid phase change material is disposed in the empty tank 103 by a low-speed spin coating or the like, and the solid phase change material is disposed in the empty tank 103 by heating to liquefy the material, then performing low-speed spin coating, and cooling to solidify the material.
Step 205: the lower surface of the second wafer 105 is bonded to the backside of the plurality of dies 101.
As shown in fig. 7(F), the lower surface of the second wafer 105 is aligned with the back surface of the die 101, and vacuum low-temperature bonding is performed.
Step 206: after the front surface of the first wafer 102 is thinned, etching the front surface of the first wafer 102 at a position corresponding to the bonding pad of the bare chip 101, until the bonding pad of the bare chip 101 is exposed from the first wafer 102, and forming a through hole 106;
as shown in fig. 7(G) and fig. 7(H), the front surface of the first wafer 102 is thinned, and etching is performed on the front surface of the first wafer 102 at a position corresponding to the pad of the die 101, where the etching depth includes etching the interlayer dielectric 113 between the first wafer 102 and the die 101, and the diameter of the through hole 106 is less than 500 um.
Step 207: conductive material is filled in via 106 to form conductive plug 107 for electrical connection with die 101.
A redistribution layer is provided on conductive plugs 107, and conductive bumps 108 are attached on conductive plugs 107 or on the redistribution layer, the conductive bumps 108 being in electrical communication with the die 101, as shown in fig. 7 (I).
Step 208: the carrier wafer 109 on the top surface of the second wafer 105 is removed, as shown in fig. 7(J), and the top surface of the second wafer 105 is thinned to a predetermined thickness, as shown in fig. 7 (K).
Step 209: a heat transfer medium is provided on the upper surface of the second wafer 105, and a heat sink 114 is provided on the heat transfer medium, as shown in fig. 7 (L).
Step 210: after the phase change heat dissipation wafer level system is packaged, the system is divided into a plurality of modules with a plurality of dies 101 as a group, and each module forms a system capable of providing multiple functions.
According to the phase change heat dissipation wafer level system packaging preparation method, the wafer level packaging method and the system packaging method are combined, and a plurality of groups of chips are packaged and integrated on the wafer, so that the area of a packaging structure can be reduced, the heat dissipation efficiency of the wafer level system packaging structure can be improved, the electrical performance of the chips is optimized, and the manufacturing cost is reduced.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims (10)

1. A method for manufacturing a phase change heat dissipation wafer level system package comprises the following steps:
providing a first wafer and a plurality of bare chips, arranging an interlayer medium on the back surface of the first wafer, and pasting the front surfaces of the plurality of bare chips which are spaced to the back surface of the first wafer;
etching the back surface of each bare chip to form a hollow groove;
the molding material is molded into a second wafer with a plurality of cavity structures on the lower surface, and the cavities correspond to the empty slots in position;
arranging a phase change material in the cavity or the empty groove;
bonding a lower surface of the second wafer with a back side of the plurality of dies;
etching the front surface of the first wafer at a position corresponding to the bonding pad of the bare chip till the first wafer exposes the bonding pad of the bare chip to form a through hole;
and filling a conductive material in the through hole to form a conductive plug so as to realize the electrical connection with the bare chip.
2. The method as claimed in claim 1, wherein after the front side of the plurality of dies is pasted to the back side of the first wafer, the back side of each die is etched and before the empty slot is formed, further comprising: and filling the gaps between the bare chips by injection molding to form a plastic packaging layer covering the side walls of the bare chips and the interlayer medium.
3. The method as claimed in claim 1, further comprising, before etching the positions corresponding to the pads of the die on the front surface of the first wafer: and thinning or removing the front surface of the first wafer.
4. The method for manufacturing the phase-change heat dissipation wafer-level system package according to claim 1, wherein after the filling of the conductive material in the through hole and the formation of the conductive plug, the method further comprises: a rewiring layer is disposed on the conductive plug.
5. The method of manufacturing a phase change heat dissipation wafer level system package of claim 1, further comprising: attaching a conductive bump on the conductive plug, the conductive bump in electrical communication with the die.
6. The method of manufacturing a phase change heat dissipation wafer level system package of claim 4, wherein a conductive bump is attached to the redistribution layer, the conductive bump being in electrical communication with the die.
7. The method of manufacturing a phase change heat dissipation wafer level system package of claim 1, further comprising: and arranging a heat transfer medium on the upper surface of the second wafer, and arranging a heat sink on the heat transfer medium.
8. The method as claimed in claim 7, further comprising, before disposing the heat transfer medium on the top surface of the second wafer: and thinning the upper surface of the second wafer.
9. The method as claimed in claim 1, wherein the phase-change material is disposed in the empty trench or cavity by spin coating at a low speed.
10. The method of claim 4, further comprising: after the phase change heat dissipation wafer level system is packaged, the phase change heat dissipation wafer level system is divided into a plurality of modules with a plurality of bare chips as a group, and each module forms a system capable of providing multiple functions.
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