CN115050713A - Wafer-level cooling system, method for generating same, data processing method, and storage medium - Google Patents
Wafer-level cooling system, method for generating same, data processing method, and storage medium Download PDFInfo
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- 238000001816 cooling Methods 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000003860 storage Methods 0.000 title claims abstract description 26
- 238000003672 processing method Methods 0.000 title claims abstract description 14
- 238000012545 processing Methods 0.000 claims abstract description 183
- 230000017525 heat dissipation Effects 0.000 claims abstract description 29
- 238000004891 communication Methods 0.000 claims abstract description 22
- 239000007788 liquid Substances 0.000 claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 claims abstract description 14
- 235000012431 wafers Nutrition 0.000 claims description 230
- 238000004590 computer program Methods 0.000 claims description 12
- 239000011810 insulating material Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 14
- 230000006870 function Effects 0.000 description 10
- 230000003993 interaction Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000012530 fluid Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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- Power Engineering (AREA)
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- General Physics & Mathematics (AREA)
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Abstract
The present disclosure provides a wafer-level cooling system, a generation method thereof, a data processing method and a storage medium, wherein the system comprises: the chip packaging structure comprises a first wafer and a second wafer which are arranged in a stacked mode, wherein the first wafer comprises a plurality of uncut processing chips, and the second wafer comprises a plurality of uncut interconnection chips and a micro-diversion layer; the processing chip is used for executing processing tasks; the interconnection chip and the processing chip have a corresponding relation and are used for realizing communication connection between the processing chips; the micro flow guiding layer is positioned on the side face opposite to the interconnection chip layer, a micro pipeline is arranged in the micro flow guiding layer and used for containing heat dissipation liquid so as to dissipate heat of the wafer-level cooling system, and the interconnection chip layer is a layer where the interconnection chips are located. Embodiments in accordance with the present disclosure enable a high performance wafer level cooling system.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a wafer-level cooling system, a method for generating a wafer-level cooling system, a data processing method, and a computer-readable storage medium.
Background
In the related art, the chip is usually packaged by using a redistribution layer (RDL), which is an interposer made of a metal material or a polymer dielectric material and includes copper connecting lines or traces for realizing electrical connection between various parts of the package. The dies of the chip may be stacked in a package, communicating with each other through a redistribution layer, thereby reducing the I/O pitch of a large chipset.
Disclosure of Invention
The present disclosure provides a wafer-level cooling system, a method of generating a wafer-level cooling system, a data processing method, a computer-readable storage medium.
In a first aspect, the present disclosure provides a wafer level cooling system, comprising:
the chip packaging structure comprises a first wafer and a second wafer which are arranged in a stacked mode, wherein the first wafer comprises a plurality of uncut processing chips, and the second wafer comprises a plurality of uncut interconnection chips and a micro-diversion layer;
the processing chip is used for executing processing tasks;
the interconnection chip and the processing chip have a corresponding relation and are used for realizing communication connection between the processing chips;
the micro flow guiding layer is arranged on the side face opposite to the interconnection chip layer, micro pipelines are arranged in the micro flow guiding layer and used for containing heat dissipation liquid so as to dissipate heat of the wafer-level cooling system, and the interconnection chip layer is a layer where the plurality of interconnection chips are located.
In some embodiments, the second wafer further comprises an insulating layer between the interconnect chip layer and the micro-guiding layer for separating the interconnect chip layer and the micro-guiding layer.
In some embodiments, the plurality of processing chips and the plurality of interconnect chips are arranged in an array, each interconnect chip corresponding to an adjacent plurality of processing chips for enabling communication connections between the adjacent plurality of processing chips.
In some embodiments, the processing chip is provided with first bonding pads, the interconnect chip is provided with second bonding pads, the first bonding pads are joined with the second bonding pads, and the first bonding pads and the second bonding pads are made of conductive materials.
In some embodiments, the first and second wafers are joined at regions other than the first and second bonding bosses by a bonding layer made of an adhesive insulating material.
In a second aspect, the present disclosure provides a method of generating a wafer level cooling system, the method comprising:
obtaining a first wafer and a second wafer, wherein the first wafer is provided with a plurality of uncut processing chips, and the second wafer is provided with a plurality of uncut interconnection chips;
the processing chip is provided with a first bonding boss, the surface of the interconnected chip is provided with a second bonding boss, the positions of the first bonding boss and the second bonding boss have a corresponding relation, and the first bonding boss and the second bonding boss are made of conductive materials;
sequentially generating an insulating layer and a micro flow guide layer on the side face, opposite to the interconnection chip layer, of the second wafer, and generating a micro pipeline in the micro flow guide layer, wherein the interconnection chip layer is a layer where the plurality of interconnection chips are located;
coating a bonding layer on a surface area of the second wafer outside the second bonding bosses, the bonding layer being made of an adhesive insulating material;
bonding and connecting the first wafer and the second wafer in a face-to-face mode to obtain a wafer bonding structure, wherein corresponding first bonding bosses and corresponding second bonding bosses are jointed, and the first wafer and the second wafer are jointed in surface areas outside the first bonding bosses and the second bonding bosses through the bonding layer;
obtaining the wafer-level cooling system according to the chip bonding structure,
and the processing chips are in communication connection through the interconnection chip.
In some embodiments, the bonding layer and the second bonding boss have a fit gap therebetween, wherein the joining the first wafer and the second wafer by face-to-face bonding results in a wafer bonded structure comprising:
placing the first and second wafers in a face-to-face stack with the corresponding first bonding pads in contact with surfaces of the second bonding pads;
and applying pressure to the first wafer and the second wafer to enable the corresponding first bonding bosses to be jointed with the second bonding bosses to obtain the wafer bonding structure, wherein the corresponding first bonding bosses and the corresponding second bonding bosses generate space deformation to fill the fit clearance.
In some embodiments, the obtaining the wafer-level cooling system according to the die bonding structure includes:
and packaging the chip bonding structure to obtain the wafer-level cooling system.
In a third aspect, the present disclosure provides a data processing method, which is applied to processing chips in the wafer-level cooling system, where the wafer-level cooling system includes a first chip and a second chip that are stacked, the first chip includes a plurality of uncut processing chips, the second chip includes a plurality of uncut interconnect chips and a micro-current guiding layer, and the interconnect chips are used to implement communication connection between the processing chips; the micro flow guiding layer is positioned on the side surface opposite to the interconnection chip layer where the plurality of interconnection chips are positioned, and micro pipelines are arranged in the micro flow guiding layer and used for containing heat dissipation liquid so as to dissipate heat of the wafer-level cooling system, wherein the method comprises the following steps:
during the processing task executed by the processing chip, sending processing data to other processing chips through an interconnection chip connected with the processing chip; and/or receiving processing data sent by other processing chips through the interconnection chip connected with the processing chip.
In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processing chip, implements the data processing method described above.
According to the embodiment provided by the disclosure, a first chip comprising a processing chip and a second chip comprising an interconnection chip are stacked, the processing chip is in communication connection through the interconnection chip, and large-bandwidth interconnection between the chips is realized, so that a high-performance wafer-level cooling system is realized; and the wafer where the interconnection chip is arranged is provided with a micro flow guide layer, and micro pipelines in the micro flow guide layer are used for containing heat dissipation liquid, so that the heat dissipation effect of the whole system is improved.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a schematic view of a wafer level cooling system according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a second wafer according to an embodiment of the disclosure.
Fig. 3 is a flowchart of a method for generating a wafer-level cooling system according to an embodiment of the disclosure.
Fig. 4a and 4b are schematic views of a first wafer and a second wafer provided in an embodiment of the disclosure.
Fig. 5a and 5b are schematic views of a first wafer and a second wafer provided in an embodiment of the disclosure.
Fig. 6 is a schematic diagram illustrating bonding of a first wafer and a second wafer according to an embodiment of the disclosure.
Fig. 7 is a schematic diagram of a second wafer according to an embodiment of the disclosure.
Fig. 8 is a schematic view of a first wafer and a second wafer provided by an embodiment of the disclosure.
Fig. 9 is a flowchart of a data processing method according to an embodiment of the present disclosure.
Detailed Description
To enable those skilled in the art to better understand the technical aspects of the present disclosure, exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the present disclosure are included to assist understanding, and they should be considered as being merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the related art, chips are typically packaged by means of redistribution layers (RDLs), through which the dies of the chips can be stacked in the package to communicate with each other, thereby reducing the I/O pitch of large chipsets. However, in this packaging method, the redistribution layer is generated based on the substrate, which has a low process fineness and cannot generate a finer (e.g., 100nm) structure; in addition, the dielectric constant of the insulating layer in the substrate is difficult to be made low, so that the RC Delay (RC Delay) of the resulting structure is large, and the performance of the whole packaging system is affected. In addition, the packaging method still needs to cut the chips in the wafer, and the processing process is complex.
If the interconnection structure between the chips is generated by adopting a semiconductor process, a finer structure can be realized, a lower dielectric constant can be realized, and even a vacuum air gap (air gap) can be made to realize insulation, so that the flexibility of the whole system design is improved, and the performance of the system is improved.
According to the embodiment of the disclosure, a wafer-level packaging mode is adopted, and the wafer comprising the processing chip and the wafer comprising the interconnection chip are directly bonded and connected in a face-to-face mode, so that the processing chip is in communication connection through the interconnection chip, and the design flexibility and the performance are improved. In addition, the wafer where the interconnection chips are located is provided with the micro flow guide layer, and the micro pipeline in the micro flow guide layer is used for containing the heat dissipation liquid, so that the heat dissipation effect of the whole system is improved.
Fig. 1 is a schematic view of a wafer level cooling system according to an embodiment of the present disclosure.
According to an embodiment of the present disclosure, there is provided a wafer level cooling system, as shown in fig. 1, comprising:
a first wafer 11 and a second wafer 12 arranged in a stack, the first wafer including a plurality of processing chips 111 that are not diced, the second wafer including a plurality of interconnect chips 121 that are not diced and a micro-flow guiding layer 124;
the processing chip is used for executing processing tasks;
the interconnection chip and the processing chip have corresponding relation for realizing communication connection between the processing chips,
the micro flow guiding layer is located on a side surface opposite to the interconnection chip layer, and a micro pipeline 125 is arranged in the micro flow guiding layer and used for containing heat dissipation liquid so as to dissipate heat of the wafer-level cooling system, wherein the interconnection chip layer is a layer where the plurality of interconnection chips are located.
For example, the first wafer 11 and the second wafer 12 may be completely uncut wafers; or the wafer may be partially cut into rectangular chips, for example, according to the design size and shape of the wafer-level cooling system, the number of chips required by the wafer-level cooling system, and the like; but may also be a wafer processed through thinning, etc., as the present disclosure is not limited thereto.
In some embodiments, the first wafer 11 includes a plurality of processing chips 111 that are not diced, and the processing chips 111 are used to perform processing tasks, such as performing various operations in the processing tasks, data interaction, and the like. The processing task may be, for example, an image processing task, a voice processing task, a text processing task, a video processing task, etc., and the present disclosure does not limit the specific type of the processing task.
In some embodiments, processing chip 111 may be a many-core chip, including multiple processing cores. The processing cores, which may also be referred to as "cores" or "cores," are the smallest unit of a many-core chip that can be independently scheduled and that has full computational power, and each processing core has its own storage and computation resources. The present disclosure is not limited to a particular chip type or chip configuration of the processing chip.
In some embodiments, the second wafer 12 includes a plurality of interconnection chips 121 that are not diced, and the interconnection chips 121 may be interconnection structures generated based on a semiconductor process, including metal interconnection lines, an insulating layer, and the like. A small number of processing devices, memory devices, and the like may also be disposed in the interconnect chip 121, and the present disclosure does not limit the materials and processes used in the interconnect chip, nor the specific structure of the interconnect chip.
In some embodiments, the plurality of processing chips and the plurality of interconnect chips are arranged in an array, i.e., an array of processing chips and an array of interconnect chips are formed separately. The first wafer 11 and the second wafer 12 may be disposed in a face-to-face stacked manner so that the respective interconnection chips and the respective process chips can be connected to each other.
In some embodiments, the interconnection chip and the processing chip have a corresponding relationship therebetween, so as to implement communication connection between the processing chips. Each interconnection chip may correspond to a plurality of adjacent processing chips for implementing communication connections between the plurality of adjacent processing chips. For example, one interconnect chip corresponds to 4 adjacent processing chips, and the 4 adjacent processing chips are connected together, so that the chips can communicate with each other through the interconnect chip.
In this case, the number of processing chips is different from the number of interconnecting chips. For example, as shown in fig. 1, the number of process chips included in the cross section of the first wafer 11 is 5, indicating that the process chips have 5 rows or 5 columns; the number of interconnected chips included in the cross section of the second wafer 12 is 4, representing interconnected chips having 4 rows or 4 columns.
The interconnection chips and the processing chips are mutually corresponding and are arranged in a staggered mode, so that the interconnection chips can realize communication connection between a plurality of adjacent processing chips, and the connection efficiency between the processing chips is improved.
In some embodiments, as shown in fig. 1, the processing chip is provided with first bonding pads 112 and the interconnect chip is provided with second bonding pads 122. The first bonding pad 112 is engaged with the second bonding pad 122, so as to realize the electrical connection between the processing chip and the interconnection chip,
wherein the first and second bonding pads are made of a conductive material. The conductive material includes any one of copper, aluminum, and gold. The present disclosure is not limited to a particular type of conductive material.
In some embodiments, the first wafer and the second wafer are joined by a bonding layer 123 in a region outside the first bonding boss and the second bonding boss, and the bonding layer is used for packaging and fixing to realize bonding connection between the first wafer and the second wafer.
Wherein the bonding layer is made of an adhesive insulating material. The insulating material comprises any one of silicon carbide, epoxy resin, polyimide and tetraethyl silicate. The present disclosure is not limited to a particular type of insulating material.
In some embodiments, there are more devices in the processing chip 111 and there is limited space available for the substrate (e.g., silicon, Si) remaining in the first wafer 11. If the micro-fluidic layer for heat dissipation is provided in the first wafer 11, the performance of each processing chip 111 may be affected. However, the number of devices in the interconnection chip 121 is small, the available substrate space in the second wafer 12 is large, and the performance of the wafer-level cooling system is less affected by the micro flow guiding layer arranged in the second wafer 12, so that the heat dissipation capability of the whole wafer-level cooling system can be improved.
The material of the substrate of the first wafer 11 and the second wafer 12 may be silicon, silicon carbide SiC, or any other type of substrate material, which is not limited in this disclosure.
In some embodiments, as shown in fig. 1, a micro fluid guiding layer 124 is disposed on a side opposite to the interconnect die layer where the plurality of interconnect dies are located, and micro channels 125 are disposed in the micro fluid guiding layer for accommodating a heat dissipating liquid to dissipate heat for the wafer level cooling system. Wherein, the micro-channel 125 is respectively provided with an inlet and an outlet, so as to control the heat dissipation liquid to flow in the micro-channel 125 by the micro-fluidic technology, such that the heat dissipation liquid flows in from the inlet and flows out from the outlet. By the method, the heat dissipation effect of the wafer-level cooling system can be improved.
Fig. 2 is a schematic diagram of a second wafer according to an embodiment of the disclosure. As shown in fig. 2, in some embodiments, the second wafer further includes an insulating layer 127 in addition to the interconnect chip layer 126 and the micro fluid guiding layer 124, the insulating layer 127 is located between the interconnect chip layer 126 and the micro fluid guiding layer 124 for separating the interconnect chip layer 126 and the micro fluid guiding layer 124, and reducing the interaction between the interconnect chip layer and the micro fluid guiding layer, thereby reducing the effect of micro-channels on the performance of the interconnect chips in the interconnect chip layer.
The material of the insulating layer 127 may be silicon dioxide SiO 2 But may be other types of insulating materials. The present disclosure is not so limited.
As shown in fig. 2, in some embodiments, the microchannels 125 in the micro-fluidic layer 124 may have a serpentine shape and may include multiple inlets and outlets to improve the heat dissipation of the wafer level cooling system. The present disclosure does not limit the specific shape of the microchannels nor the number of inlets and outlets.
According to the wafer-level cooling system disclosed by the embodiment of the disclosure, a first chip comprising a processing chip and a second chip comprising an interconnection chip are stacked, and the processing chips are in communication connection through the interconnection chip, so that large-bandwidth interconnection among the chips is realized, and a high-performance wafer-level cooling system is realized; and the second wafer is provided with a micro flow guiding layer, and micro pipelines in the micro flow guiding layer are used for containing heat dissipation liquid, so that the heat dissipation effect of the whole wafer-level cooling system is improved.
The following describes the production process of the wafer level cooling system.
Fig. 3 is a flowchart of a method for generating a wafer-level cooling system according to an embodiment of the disclosure.
According to an embodiment of the present disclosure, there is provided a method for generating a wafer level cooling system, as shown in fig. 3, the method including:
step S31, obtaining a first wafer and a second wafer, wherein the first wafer is provided with a plurality of uncut processing chips, and the second wafer is provided with a plurality of uncut interconnection chips;
the surface of the processing chip is provided with a first bonding boss, the surface of the interconnection chip is provided with a second bonding boss, the positions of the first bonding boss and the second bonding boss are in corresponding relation, and the first bonding boss and the second bonding boss are made of conductive materials;
step S32, sequentially generating an insulating layer and a micro flow guiding layer on a side surface of the second wafer opposite to the interconnection chip layer, and generating a micro channel in the micro flow guiding layer, where the interconnection chip layer is a layer where the plurality of interconnection chips are located;
step S33, coating a bonding layer on the surface area of the second wafer except the second bonding bosses, wherein the bonding layer is made of adhesive insulating material;
step S34, bonding and connecting the first wafer and the second wafer in a face-to-face manner to obtain a wafer bonding structure, where corresponding first bonding bosses and second bonding bosses are bonded, and surface regions of the first wafer and the second wafer outside the first bonding bosses and the second bonding bosses are bonded through the bonding layer;
step S35, obtaining the wafer-level cooling system according to the chip bonding structure,
and the processing chips are in communication connection through the interconnection chip.
For example, a first wafer having a plurality of processing chips thereon that are not diced and a second wafer having a plurality of interconnecting chips thereon that are not diced may be respectively obtained in step S31. The wafer with a plurality of processing chips and the wafer with a plurality of interconnected chips can be respectively generated by adopting a preset semiconductor process, and the generated wafers can be directly used as a first chip and a second chip; the wafer may be further processed (e.g., cut into a predetermined rectangle) to obtain a first chip and a second chip, which is not limited by the present disclosure.
Fig. 4a and 4b are schematic views of a first wafer and a second wafer provided in an embodiment of the disclosure. FIG. 4a shows a first wafer 31 with a plurality of processing chips 311 thereon; fig. 4b shows a second wafer 32 on which a plurality of interconnected chips 321 are present.
In some embodiments, the processing chip may be, for example, an artificial intelligence AI many-core chip, which includes a plurality of processing cores for implementing corresponding AI processing tasks; other types of processing chips are possible and the present disclosure is not limited thereto.
In some embodiments, the plurality of processing chips of the first wafer are free of interconnects. Therefore, the space occupied by the interconnection structure can be saved, the size of a processing chip is reduced, or more devices are integrated under the same chip size, and the performance is improved.
In some embodiments, the interconnection structure in the interconnection chip, which may be custom designed and corresponds to the processing chip, includes metal interconnection lines, insulating layers, and the like. The interconnection chip can also be provided with a small number of processing devices, memory devices and the like, and the material and process adopted by the interconnection chip, the specific structure of the interconnection chip and the like are not limited in the disclosure.
In some embodiments, the interconnection chip and the processing chip have a corresponding relationship to realize communication connection between the processing chips. Each interconnection chip may correspond to a plurality of adjacent processing chips for implementing communication connections between the plurality of adjacent processing chips.
In some embodiments, at least one first bonding pad is disposed on the handle chip and at least one second bonding pad is disposed on the interconnect chip. The positions of the first bonding boss and the second bonding boss have a corresponding relationship, and the first bonding boss and the second bonding boss are both made of conductive materials, such as copper, aluminum, gold and the like.
Fig. 5a and 5b are schematic views of a first wafer and a second wafer provided in an embodiment of the disclosure. As shown in fig. 5a, the first wafer 41 has a plurality of processing chips each having a first bonding pad 411, and the number of the first bonding pads on the processing chip in the non-edge region is smaller, and the number of the first bonding pads on the processing chip in the edge region is larger. As shown in fig. 5b, a second bonding pad 421 is provided on each interconnection chip of the second wafer 42. There is a corresponding relationship between the positions of the first and second bonding bosses 411 and 421.
Fig. 6 is a schematic diagram of bonding a first wafer and a second wafer according to an embodiment of the disclosure. As shown in fig. 6, the first bonding pads of the first wafer and the second bonding pads of the second wafer have a corresponding relationship in position, and when the first wafer 51 and the second wafer 52 are bonded, the corresponding first bonding pads and the corresponding second bonding pads are bonded to realize the electrical connection between the processing chip and the interconnection chip.
In some embodiments, in step S32, after obtaining the second wafer, an insulating layer and a micro flow guiding layer may be sequentially formed on a side of the second wafer opposite to the interconnect chip layer, and micro channels may be formed in the micro flow guiding layer. For example, the insulating layer may be formed by oxidation, and the micro-fluidic layer and the micro-channels in the micro-fluidic layer may be formed by deposition and etching, and the present disclosure does not limit the process steps used to form the insulating layer and the micro-fluidic layer.
In some embodiments, the wafer on which the second wafer is located may also be directly processed to generate the insulating layer and the micro flow guiding layer; the wafer is further processed (e.g., cut into a predetermined rectangle) to obtain a second chip. The present disclosure does not limit the specific order of processing.
Fig. 7 is a schematic diagram of a second wafer according to an embodiment of the disclosure. As shown in fig. 7, one side of the second wafer 42 is an interconnection chip layer, which includes a plurality of interconnection chips, and each interconnection chip is provided with a second bonding pad 421; the other side is a micro-flow guiding layer comprising micro-channels 422. The micro-pipe 422 is serpentine and is positioned below the plurality of interconnected chips; and the heat dissipation liquid is provided with an inlet and an outlet so as to control the heat dissipation liquid to flow in the micro-pipeline through the microfluidic technology, so that the heat dissipation liquid flows in from the inlet and flows out from the outlet, and the heat dissipation of the whole system is realized.
In some embodiments, in step S33, a bonding layer may be applied to a surface area of the second wafer other than the second bonding pad, and the bonding layer is used for package fixing to realize bonding connection between the first wafer and the second wafer. Wherein the bonding layer is made of an adhesive insulating material. The insulating material includes silicon carbide, epoxy, polyimide, tetraethyl silicate, and the like, and the specific type of insulating material is not limited by the present disclosure.
Fig. 8 is a schematic view of a first wafer and a second wafer provided by an embodiment of the disclosure. As shown in fig. 8, the first wafer 11 includes a plurality of process chips 111, and the process chips 111 are provided with first bonding pads 112 thereon; the second wafer 12 includes a plurality of interconnection chips 121, and the interconnection chips 121 are provided with second bonding pads 122. The surface area of the second wafer 12 outside the second bonding pads is coated with a bonding layer 123. The second wafer 12 further comprises a micro-current guiding layer 124 provided with micro-channels 125.
In some embodiments, as shown in fig. 8, the bonding layer and the second bonding boss have a fit gap therebetween, which can leave room for the first bonding boss and the second bonding boss to deform. The present disclosure is not limited to specific dimensions of the fit-gap.
In some embodiments, in step S34, the first wafer and the second wafer may be bonded face to result in a wafer bonded structure. And the surface regions of the first wafer and the second wafer outside the first bonding boss and the second bonding boss are jointed through the bonding layer.
In some embodiments, step S34 may include:
placing the first and second wafers in a face-to-face stack with the corresponding first bonding pads in contact with surfaces of the second bonding pads;
and applying pressure to the first wafer and the second wafer to enable the corresponding first bonding bosses to be jointed with the second bonding bosses to obtain the wafer bonding structure, wherein the corresponding first bonding bosses and the corresponding second bonding bosses generate space deformation to fill the fit clearance.
That is, the first and second wafers may be stacked face-to-face with the corresponding first and second bonding pads aligned with their surfaces in contact; further, pressure is applied to the first and second wafers, for example, the first and second wafers are placed on a stage, and pressed down by a corresponding device, so that uniform pressure is applied to the first and second wafers, and the corresponding first and second bonding pads are spatially deformed to fill the fit gap in fig. 8, resulting in the structure shown in fig. 1. In this way, bonding of the first wafer and the second wafer is achieved, so that the processing chips can be communicatively connected with each other through the interconnection chip.
It should be understood that the bonding manner of the first wafer and the second wafer can be set by those skilled in the art according to practical situations, and the disclosure is not limited thereto.
In some embodiments, in step S35, a wafer level cooling system is obtained according to the die bonding configuration. The chip bonding structure can be directly used as a wafer-level cooling system; subsequent processing, such as thinning, packaging, etc., may also be performed on the die bond structure to obtain a wafer level cooling system.
In some embodiments, step S35 may include: and packaging the chip bonding structure to obtain the wafer-level cooling system.
That is, the die bond structure may be sealed by an encapsulation material, such as ceramic or the like; and corresponding pins are provided to enable the wafer bonding structure to be connected to external circuitry, such as to be soldered to a board. After packaging, the final wafer level cooling system is obtained. The present disclosure is not limited to a particular packaging process.
According to the generation method of the wafer-level cooling system, the wafer-level cooling system can be generated in a face-to-face bonding mode based on the first chip and the second chip, butt joint during connection is more accurate through direct connection of the chips, large-bandwidth interconnection among the chips can be achieved, and the high-performance wafer-level cooling system is obtained; and an insulating layer and a micro flow guiding layer are formed on the second wafer, and a micro pipeline is formed in the micro flow guiding layer, so that the heat dissipation effect of the whole wafer-level cooling system can be improved.
Fig. 9 is a flowchart of a data processing method according to an embodiment of the present disclosure.
According to an embodiment of the present disclosure, a data processing method is further provided, which is applied to the processing chip in the wafer-level cooling system. The wafer-level cooling system comprises a first wafer and a second wafer which are stacked, wherein the first wafer comprises a plurality of uncut processing chips, the second wafer comprises a plurality of uncut interconnection chips and a micro flow guiding layer, and the interconnection chips are used for realizing communication connection among the processing chips; the micro flow guiding layer is arranged on the side surface opposite to the interconnection chip layer where the plurality of interconnection chips are arranged, micro pipelines are arranged in the micro flow guiding layer and used for containing heat dissipation liquid so as to dissipate heat for the wafer level cooling system,
in some embodiments, as shown in fig. 9, the method comprises:
step S91, during the processing chip executing the processing task, sending the processing data to other processing chips through the interconnection chip connected with the processing chip; and/or receiving processing data sent by other processing chips through the interconnection chip connected with the processing chip.
For example, a processing chip may be used to perform processing tasks, such as performing various operations in a processing task, data interactions, and so forth. The processing tasks may be, for example, image processing tasks, voice processing tasks, text processing tasks, video processing tasks, etc., and the specific type of processing task is not limited by this disclosure.
In some embodiments, for any one processing chip in the wafer-level cooling system, during the processing chip performs a processing task, data interaction may be required with other processing chips in the wafer-level cooling system, for example, sending a processing result of the processing chip to the other processing chips, sending a processing instruction to the other processing chips, receiving a data processing result of the other processing chips, and the like. The present disclosure is not limited to the type or manner of data interaction.
In some embodiments, during the execution of a processing task by a processing chip, processing data, such as processing results, processing instructions, data acquisition requests, etc., may be sent to other processing chips via an interconnect chip connected to the processing chip; similarly, the processing chip may also receive processing data sent by other processing chips through the interconnection chip connected to the processing chip, such as processing results, processing instructions, data acquisition requests, and the like of other processing chips.
By the method, data interaction between the processing chips can be realized through the interconnection chip, and the bandwidth and the speed of the data interaction are improved, so that high-speed connection and interaction of large bandwidth are realized.
In some embodiments, during operation of the plurality of processing chips of the wafer-level cooling system, the heat dissipation liquid is controlled to flow in the micro-channels of the second chip by micro-fluidic technology (for example, micro-pumps corresponding to the micro-channels are provided), so that the heat dissipation liquid flows in from the inlet and flows out from the outlet, thereby achieving heat dissipation of the respective processing chips of the wafer-level cooling system.
According to the embodiment of the disclosure, the interconnection structure between the chips can be generated by adopting a semiconductor process, and the chips comprising the processing chips and the chips comprising the interconnection chips are directly bonded and connected face to face in a wafer-level packaging mode, so that the processing chips can realize high-speed connection with large bandwidth through the interconnection chips, and a high-performance wafer-level cooling system is realized. And the chip where the interconnected chips are located is provided with a micro flow guiding layer, and micro pipelines in the micro flow guiding layer are used for containing heat dissipation liquid, so that the heat dissipation effect of the whole wafer-level cooling system is improved.
The embodiment of the present disclosure also provides a computer readable storage medium, on which a computer program is stored, wherein the computer program realizes the above data processing method when being executed by a processing chip. The computer readable storage medium may be a volatile or non-volatile computer readable storage medium.
The disclosed embodiments also provide a computer program product, which includes a computer readable code or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code runs in a processor or a processing chip of an electronic device, the processor or the processing chip in the electronic device executes the above data processing method.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable storage media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM), Static Random Access Memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer. In addition, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.
The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).
The computer program product described herein may be embodied in hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK), or the like.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (10)
1. A wafer level cooling system, comprising:
the chip packaging structure comprises a first wafer and a second wafer which are arranged in a stacked mode, wherein the first wafer comprises a plurality of uncut processing chips, and the second wafer comprises a plurality of uncut interconnection chips and a micro-diversion layer;
the processing chip is used for executing processing tasks;
the interconnection chip and the processing chip have a corresponding relation and are used for realizing communication connection between the processing chips;
the micro flow guiding layer is positioned on the side face opposite to the interconnection chip layer, a micro pipeline is arranged in the micro flow guiding layer and used for containing heat dissipation liquid so as to dissipate heat of the wafer-level cooling system, and the interconnection chip layer is a layer where the interconnection chips are located.
2. The system of claim 1, wherein the second wafer further comprises an insulating layer between the interconnect chip layer and the micro fluidic layer for separating the interconnect chip layer from the micro fluidic layer.
3. The system of claim 1, wherein the plurality of processing chips and the plurality of interconnect chips are arranged in an array, each interconnect chip corresponding to an adjacent plurality of processing chips for enabling communication connections between the adjacent plurality of processing chips.
4. The system of claim 1, wherein the processing chip is provided with first bonding pads, the interconnect chip is provided with second bonding pads, the first bonding pads engage with the second bonding pads, and the first bonding pads and the second bonding pads are made of an electrically conductive material.
5. The system of claim 4, wherein the first and second wafers are joined at regions outside the first and second bonding bosses by a bonding layer made of an adhesive insulating material.
6. A method of generating a wafer level cooling system, comprising:
obtaining a first wafer and a second wafer, wherein the first wafer is provided with a plurality of uncut processing chips, and the second wafer is provided with a plurality of uncut interconnection chips;
the processing chip is provided with a first bonding boss, the surface of the interconnected chip is provided with a second bonding boss, the positions of the first bonding boss and the second bonding boss have a corresponding relation, and the first bonding boss and the second bonding boss are made of conductive materials;
sequentially generating an insulating layer and a micro flow guide layer on the side face, opposite to the interconnection chip layer, of the second wafer, and generating micro pipelines in the micro flow guide layer, wherein the interconnection chip layer is a layer where the plurality of interconnection chips are located;
coating a bonding layer on a surface area of the second wafer outside the second bonding bosses, the bonding layer being made of an adhesive insulating material;
bonding and connecting the first wafer and the second wafer in a face-to-face mode to obtain a wafer bonding structure, wherein corresponding first bonding bosses and second bonding bosses are jointed, and the surface regions of the first wafer and the second wafer, except the first bonding bosses and the second bonding bosses, are jointed through the bonding layer;
obtaining the wafer-level cooling system according to the chip bonding structure,
and the processing chips are in communication connection through the interconnection chip.
7. The method of claim 6, wherein the bonding layer and the second bonding pad have a fit gap therebetween, and wherein the connecting the first wafer and the second wafer by face-to-face bonding results in a wafer bonded structure comprising:
placing the first and second wafers in a face-to-face stack with the corresponding first bonding bosses in contact with surfaces of the second bonding bosses;
and applying pressure to the first wafer and the second wafer to enable the corresponding first bonding bosses to be jointed with the second bonding bosses to obtain the wafer bonding structure, wherein the corresponding first bonding bosses and the corresponding second bonding bosses generate space deformation to fill the fit clearance.
8. The method of claim 6, wherein said deriving said wafer level cooling system from said wafer bonding structure comprises:
and packaging the chip bonding structure to obtain the wafer-level cooling system.
9. A data processing method, which is applied to the processing chips in the wafer-level cooling system as claimed in any one of claims 1 to 5, wherein the wafer-level cooling system comprises a first wafer and a second wafer which are stacked, the first wafer comprises a plurality of uncut processing chips, the second wafer comprises a plurality of uncut interconnection chips and a micro-current conducting layer, and the interconnection chips are used for realizing communication connection among the processing chips; the micro flow guiding layer is positioned on the side surface opposite to the interconnection chip layer where the plurality of interconnection chips are positioned, micro pipelines are arranged in the micro flow guiding layer and used for containing heat dissipation liquid so as to dissipate heat for the wafer level cooling system,
wherein the method comprises the following steps:
during the processing task executed by the processing chip, sending processing data to other processing chips through an interconnection chip connected with the processing chip; and/or receiving processing data sent by other processing chips through the interconnection chip connected with the processing chip.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processing chip, carries out the data processing method of claim 9.
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| CN202210380552.4A CN115050713A (en) | 2022-04-08 | 2022-04-08 | Wafer-level cooling system, method for generating same, data processing method, and storage medium |
| PCT/CN2023/086435 WO2023193737A1 (en) | 2022-04-08 | 2023-04-06 | Wafer-level system and generation method therefor, data processing method, and storage medium |
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