CN109192782A - A kind of power device and preparation method thereof - Google Patents
A kind of power device and preparation method thereof Download PDFInfo
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- CN109192782A CN109192782A CN201811024201.XA CN201811024201A CN109192782A CN 109192782 A CN109192782 A CN 109192782A CN 201811024201 A CN201811024201 A CN 201811024201A CN 109192782 A CN109192782 A CN 109192782A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of power device and preparation method thereof, comprising: in the first epitaxial layer and the second epitaxial layer of one conduction type of upper surface of substrate growth regulation of the first conduction type；The first injection region of the second conduction type is formed in first epitaxial layer；The second injection region of the second conduction type is formed in second epitaxial layer；The third injection region of the first conduction type and the 4th injection region of the second conduction type are formed in second injection region；First medium layer is formed in the upper surface of second injection region；The first polysilicon layer is formed in first medium layer upper surface；Second dielectric layer is formed in second epitaxial layer upper surface；Form the second polysilicon layer for being separately connected first polysilicon layer and first injection region；Source electrode is formed in the second dielectric layer upper surface；The grid connecting with second polysilicon layer is formed in the second dielectric layer；Drain electrode is formed in the lower surface of the substrate, present invention reduces the power losses of device.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power device and preparation method thereof.
Background technique
Drain-source the two poles of the earth of vertical bilateral diffusion field-effect tranisistor in the two sides of device, keep electric current vertical in device inside respectively
Circulation, increases current density, improves rated current, the conducting resistance of unit area is also smaller, is that a kind of purposes is very wide
General power device.The most important performance parameter of vertical bilateral diffusion field-effect tranisistor is exactly working loss, and working loss can
To be divided into conduction loss, cut-off loss and switching loss three parts.Wherein conduction loss is determined by conducting resistance, cut-off loss by
Reverse leakage current size influences, and parasitic capacitance charge and discharge bring is lost during switching loss refers to devices switch.In order to full
Sufficient power device adapts to the requirement of frequency applications, reduces the switching loss of power device, improves the working efficiency of device, has weight
The meaning wanted.
The switching loss size of power device is determined that parasitic capacitance can be divided into gate-source capacitance, grid by parasitic capacitance size
Drain capacitance and source drain capacitance three parts.Wherein gate leakage capacitance influences the switching loss of device maximum, and gate leakage capacitance can be divided into
Layer capacitance and depletion-layer capacitance two parts are aoxidized, oxidation layer capacitance is influenced by gate oxide thickness, and depletion-layer capacitance is by technique and device
Structure is affected.Gate leakage capacitance directly influences input capacitance and the switch time of device, and input capacitance increases, to make device
Part switch time extends, and then increases switching loss.
Therefore, a kind of technical solution of switching loss that can reduce power device is needed.
Summary of the invention
The present invention is based on the above problems, proposes a kind of power device and preparation method thereof, can reduce power device
The parasitic capacitance of part, to reduce the switching loss of power device.
In view of this, on the one hand the embodiment of the present invention proposes a kind of power device, which includes:
The substrate of first conduction type；
First epitaxial layer of the first conduction type, is grown on the upper surface of substrate；
First injection region of the second conduction type is formed in first epitaxial layer；
Second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；
Second injection region of the second conduction type is formed in second epitaxial layer；
The 4th of the third injection region of first conduction type and the second conduction type being connect with the third injection region
Injection region is formed in second injection region, and the doping concentration of the 4th injection region is higher than mixing for second injection region
Miscellaneous concentration；
First medium layer, is formed in the upper surface of second injection region, and the first medium layer connects the third note
Enter the portion of upper surface in area；
First polysilicon layer is formed in first medium layer upper surface；
Second dielectric layer, is formed in second epitaxial layer upper surface, and the second dielectric layer covers the first medium
Layer and first polysilicon layer；
Second polysilicon layer is separately connected first polysilicon layer and first injection region；
Source electrode is formed in the upper surface of the second dielectric layer and through the second dielectric layer and the third injection region
It is connected with the 4th injection region；
Grid is formed in the second dielectric layer and connect with second polysilicon layer；
Drain electrode, is formed in the lower surface of the substrate and connect with the substrate.
Further, the doping concentration of the substrate is higher than the doping concentration of first epitaxial layer, first extension
The doping concentration of layer is higher than the doping concentration of second epitaxial layer, and the doping concentration of the substrate is higher than the third injection region
Doping concentration.
Further, the doping concentration of the 4th injection region is higher than the doping concentration of first injection region, and described the
The doping concentration of one injection region is higher than the doping concentration of second injection region.
Further, first injection region, the third injection region, the first medium layer, first polysilicon
Layer and second polysilicon layer are symmetrical arranged relative to the 4th injection region.
Further, second polysilicon layer includes being formed in the second dielectric layer and connecting first polycrystalline
The sub- polysilicon layer of the first of silicon layer connects first injection region through second epitaxial layer and extends to the second medium
The second sub- polysilicon layer in layer, and connect the first sub- polysilicon layer and the second sub- polysilicon layer third it is more
Crystal silicon layer.
On the other hand the embodiment of the present invention provides a kind of production method of power device, this method comprises:
The substrate of first conduction type is provided；
First epitaxial layer of one conduction type of surface growth regulation over the substrate；
The first injection region of the second conduction type is formed in first epitaxial layer；
The second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；
The second injection region of the second conduction type is formed in second epitaxial layer；
The third injection region of the first conduction type is formed in second injection region and is connected with the third injection region
4th injection region of the second conduction type connect, the doping concentration of the 4th injection region are higher than the doping of second injection region
Concentration；
First medium layer is formed in the upper surface of second injection region, the first medium layer is connected into the third and is infused
Enter the portion of upper surface in area；
The first polysilicon layer is formed in first medium layer upper surface；
Second dielectric layer is formed in second epitaxial layer upper surface, the second dielectric layer is covered into the first medium
Layer and first polysilicon layer；
Form the second polysilicon layer for being separately connected first polysilicon layer and first injection region；
Source electrode is formed in the second dielectric layer upper surface, and the source electrode also extends through second dielectric layer connection described the
Three injection regions and the 4th injection region；
The grid connecting with second polysilicon layer is formed in the second dielectric layer；
The drain electrode connecting with the substrate is formed in the lower surface of the substrate.
Further, the doping concentration of the substrate is higher than the doping concentration of first epitaxial layer, first extension
The doping concentration of layer is higher than the doping concentration of second epitaxial layer, and the doping concentration of the substrate is higher than the third injection region
Doping concentration.
Further, the doping concentration of the 4th injection region is higher than the doping concentration of first injection region, and described the
The doping concentration of one injection region is higher than the doping concentration of second injection region.
Further, by first injection region, the third injection region, the first medium layer, first polycrystalline
Silicon layer and second polysilicon layer are symmetrical arranged relative to the 4th injection region.
Further, second polysilicon layer includes being formed in the second dielectric layer and connecting first polycrystalline
The sub- polysilicon layer of the first of silicon layer connects first injection region through second epitaxial layer and extends to the second medium
The second sub- polysilicon layer in layer, and connect the first sub- polysilicon layer and the second sub- polysilicon layer third it is more
Crystal silicon layer.
The technical solution of the embodiment of the present invention is by providing the substrate of the first conduction type；Surface is grown over the substrate
First epitaxial layer of the first conduction type；The first injection region of the second conduction type is formed in first epitaxial layer；Institute
State the second epitaxial layer that the first epitaxial layer upper surface forms the first conduction type；It is conductive that second is formed in second epitaxial layer
Second injection region of type；Formed in second injection region the first conduction type third injection region and with the third
4th injection region of the second conduction type of injection region connection, the doping concentration of the 4th injection region are higher than second injection
The doping concentration in area；First medium layer is formed in the upper surface of second injection region, it will be described in first medium layer connection
The portion of upper surface of third injection region；The first polysilicon layer is formed in first medium layer upper surface；In second extension
Layer upper surface forms second dielectric layer, and the second dielectric layer is covered the first medium layer and first polysilicon layer；
Form the second polysilicon layer for being separately connected first polysilicon layer and first injection region；In the second dielectric layer
Surface forms source electrode, and the source electrode also extends through the second dielectric layer and connects the third injection region and the 4th injection region；
The grid connecting with second polysilicon layer is formed in the second dielectric layer；Formation and institute in the lower surface of the substrate
The drain electrode of substrate connection is stated, present invention decreases the parasitic capacitances of power device, to reduce the switching loss of power device, mention
The working efficiency of high-power component.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of the production method for the power device that one embodiment of the present of invention provides；
Fig. 2 is the structural schematic diagram for the power device that one embodiment of the present of invention provides；
Fig. 3 to Fig. 8 is the structural schematic diagram of the production method step for the power device that one embodiment of the present of invention provides；
Fig. 9 is the equivalent circuit diagram for the power unit structure that one embodiment of the present of invention provides；
In figure: 1, substrate；2, the first epitaxial layer；3, the first injection region；4, the second epitaxial layer；5, the second injection region；6,
Three injection regions；7, the 4th injection region；8, first medium layer；9, the first polysilicon layer；10, second dielectric layer；11, the second polysilicon
Layer；12, source electrode；13, grid；14, it drains；A, first diode.
Specific embodiment
It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
A kind of power device provided in an embodiment of the present invention and preparation method thereof is carried out below in conjunction with Fig. 1 to Fig. 9 detailed
Explanation.
Referring next to attached drawing, a kind of production method of power device of the embodiment of the present invention is elaborated.
The embodiment of the present invention provides a kind of production method of power device, as depicted in figs. 1 and 2, the system of the power device
Include: as method
Step S01: the substrate 1 of the first conduction type is provided；The of 1 upper surface growth regulation of substrate, one conduction type
One epitaxial layer 2；
Step S02: the first injection region 3 of the second conduction type is formed in first epitaxial layer 2；
Step S03: the second epitaxial layer 4 of the first conduction type is formed in 2 upper surface of the first epitaxial layer；
Step S04: the second injection region 5 of the second conduction type is formed in second epitaxial layer 4；In second note
Enter to be formed in area 5 the third injection region 6 of first conduction type and the second conduction type for connecting with the third injection region 6
4th injection region 7, the doping concentration of the 4th injection region 7 are higher than the doping concentration of second injection region 5；Described second
The upper surface of injection region 5 forms first medium layer 8, and the first medium layer 8 is connected table on the part of the third injection region 6
Face；The first polysilicon layer 9 is formed in 8 upper surface of first medium layer；Second is formed in 4 upper surface of the second epitaxial layer to be situated between
The second dielectric layer 10 is covered the first medium layer 8 and first polysilicon layer 9 by matter layer 10；
Step S05: the second polysilicon layer for being separately connected first polysilicon layer 9 and first injection region 3 is formed
11；
Step S06: source electrode 12 is formed in 10 upper surface of second dielectric layer, the source electrode 12 also extends through described second and is situated between
Matter layer 10 connects the third injection region 6 and the 4th injection region 7；It is formed and described second in the second dielectric layer 10
The grid 13 that polysilicon layer 11 connects；The drain electrode 14 connecting with the substrate 1 is formed in the lower surface of the substrate 1.
The present invention improves on the basis of conventional power devices proposes a kind of grid positive feedback power device chip,
The embodiment of the present invention in first epitaxial layer 2 by increasing by first injection region 3, so that the grid 13 and the leakage
By the first diode a connection between pole 14, thus the grid 13 is in parallel with the first diode a, reduce institute
The parasitic capacitance between grid 13 and drain electrode 14 is stated, the parasitic capacitance of the power device is also with reduction.In addition, the present invention is real
Applying the first diode a in parallel in the power device of example can also prevent surge current from damaging gate oxide, to improve
The protection feature and reliability of improved power device.Power device provided in an embodiment of the present invention simplifies technique, realizes
Cost is reduced, by reducing the parasitic capacitance of the power device, reduces the switching loss of the power device, to mention
The working efficiency of the high power device.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
In next embodiment, adulterated by p-type of first conduction type, second conduction type is that n-type doping is
Example is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
Attached drawing 3 is please referred to, step S01 is executed, specifically: the substrate 1 of the first conduction type is provided；On the substrate 1
First epitaxial layer 2 of one conduction type of surface growth regulation.In some embodiments of the invention, the substrate 1 is, for example, monocrystalline
Silicon substrate 1, and doping concentration is, for example, 1e15atoms/cm3.Wherein, it is grown in 1 upper surface of substrate of the first conduction type
The mode of first epitaxial layer 2 of the first conduction type is not limited to a kind of fixed mode, can use in 1 upper surface of substrate
It is epitaxially-formed, can also be formed outside described first by ion implanting and/or the method for diffusion in 1 upper surface of substrate
Prolong layer 2.It is possible to further be epitaxially-formed in the 1 upper surface use of substrate, can also by ion implanting and/or
The method for spreading any combination of P elements or arsenic element or both forms first epitaxial layer 2 in 1 upper surface of substrate.
Specifically, the extension or the method for diffusion include depositing operation.In some embodiments of the invention, deposition work can be used
Skill forms first epitaxial layer 2 in 1 upper surface of substrate, for example, depositing operation can be selected from electron beam evaporation, chemistry
One of vapor deposition, atomic layer deposition, sputtering.Preferably, first is formed using chemical vapor deposition on the substrate 1
Epitaxial layer 2, chemical vapor deposition include process for vapor phase epitaxy.In production, chemical vapor deposition uses vapour phase epitaxy work mostly
Skill forms the first epitaxial layer 2 using process for vapor phase epitaxy in 1 upper surface of substrate, and silicon material can be improved in process for vapor phase epitaxy
The perfection of material improves the integrated level of device, reaches raising minority carrier life time, reduces the leakage current of storage element.Preferably, described
First epitaxial layer 2 and the substrate 1 are all that silicon materials are made, so that the substrate 1 and first epitaxial layer 2 have the phase allomeric
The silicon face of structure, to keep the control to dopant type and concentration.Due to autodoping effect, in epitaxial process,
Dopant from the substrate 1 can enter in the first epitaxial layer 2, to change the electric conductivity of epitaxial semiconductor layer.
Attached drawing 4 is please referred to, step S02 is executed, specifically: the second conduction type is formed in first epitaxial layer 2
First injection region 3.In this step, it is prepared in the upper surface of first epitaxial layer 2 and covers one layer of photoresist layer, so
Photoresist layer is formed by mask using photoetching afterwards.The mask includes opening for all surfaces of exposure first injection region 3
Mouthful.Pass through in the opening of the exposure mask in method the second conductive-type of formation that 2 intermediate ion of the first epitaxial layer injects and/or spreads
First injection region 3 of type.Also, again by dissolving or being ashed removal light in a solvent after forming first injection region 3
Resist layer is caused, to ultimately form first injection region 3.Further, pass through ion implanting in the opening of the exposure mask
And/or spread the first note of method second conduction type of formation of boron element or phosphide element or aluminium element or any combination of three
Enter area 3, in forming process, any combination of ion implanting and/or diffusion boron element or phosphide element or aluminium element or three
Concentration is higher than the concentration of first epitaxial layer 2, so that guarantee forms the first injection region 3 of the second conduction type of heavy doping.
It should be noted that since first injection region 3 is by ion implanting and/or to diffuse to form, first note
The bottom sectional view for entering area 3 is to be similar to the shape of arc, and the bottom sectional view of first injection region 3 may be to be similar to
Rectangular shape, but not limited to this.
Attached drawing 5 is please referred to, step S03 is executed, specifically: the first conductive-type is formed in 2 upper surface of the first epitaxial layer
Second epitaxial layer 4 of type.In some embodiments of the invention, second epitaxial layer 4 can be on first epitaxial layer 2
Surface use is epitaxially-formed, and can also pass through any group of ion implanting and/or diffusion P elements or arsenic element or both
The method of conjunction is formed in 2 upper surface of the first epitaxial layer.Second epitaxial layer 4 is by the upper surface of first epitaxial layer 2
Covering, and it is equipped with certain thickness.It should be noted that the thickness of first epitaxial layer 2 and second epitaxial layer 4 is for example
It is 3~10 microns.The range of the intrinsic doping concentration of first epitaxial layer 2 and second epitaxial layer 4 be, for example, 1e11~
1e14atoms/cm.Second epitaxial layer 4 is with first epitaxial layer 2 and the substrate 1 for adjusting the power device
The breakdown reverse voltage of part, is not involved in form PN junction.Preferably, by adjust from the substrate 1 to first epitaxial layer 2 with
And the doping concentration of second epitaxial layer 4, it can control the breakdown voltage of the power device protection chip, such as positioned at 2-
In 48V or bigger range.
Attached drawing 6 is please referred to, step S04 is executed, specifically: the second conduction type is formed in second epitaxial layer 4
Second injection region 5；The third injection region 6 of the first conduction type is formed in second injection region 5 and is infused with the third
Enter the 4th injection region 7 of the second conduction type of the connection of area 6, the doping concentration of the 4th injection region 7 is higher than second note
Enter the doping concentration in area 5；First medium layer 8 is formed in the upper surface of second injection region 5, the first medium layer 8 is connected
Connect the portion of upper surface of the third injection region 6；The first polysilicon layer 9 is formed in 8 upper surface of first medium layer；Described
Second epitaxial layer, 4 upper surface forms second dielectric layer 10, and the second dielectric layer 10 is covered the first medium layer 8 and described
First polysilicon layer 9.In this step, it should be noted that the step specifically includes: second injection region 5 be by from
The method of any combination of son injection and/or diffusion boron element or phosphide element or aluminium element or three is in second epitaxial layer 4
Interior formation, it should be noted that second injection region 5 is the area the power device Zhong Ti.It should be understood that the third note
Entering area 6 can be by the method for any combination of ion implanting and/or diffusion P elements or arsenic element or both described second
It is formed in injection region 5, the 4th injection region 7 can pass through ion implanting and/or diffusion boron element or phosphide element or aluminium element
Or the method for any combination of three is formed in second injection region 5, the third injection region 6 and the 4th injection region
7 is adjacent, and the third injection region 6 is connect with the 4th injection region 7.Specifically, the third injection region 6 is the power
The source region of device.In some embodiments of the invention, in the power device, the doping concentration of the 4th injection region 7
Higher than the doping concentration of second injection region 5, so that the resistivity of second injection region 5 is higher than the 4th injection region 7
Resistivity, prevent from leaking electricity.
In some embodiments of the invention, the power device can be VDMOS (i.e. vertical double diffused metal-oxidation
Object semiconductor field effect transistor), it can also be LDMOS (i.e. transverse diffusion metal oxide semiconductor field effect pipe), it can also
To be JFET (i.e. junction field effect transistor) or BJT (i.e. bipolar junction transistor), but not limited to this, art technology
Personnel can select different power device and the embodiment of the present invention to be combined improvement according to the actual situation.
In some embodiments of the invention, the first medium layer 8 is by etching in 5 upper surface of the second injection region
It is formed, and the first medium layer 8 is also connected with the portion of upper surface of the third injection region 6.It should be noted that due to described
The method that second injection region 5, the third injection region 6 and the 4th injection region 7 are formed is ion implanting and/or expansion
It dissipates, therefore, the upper surface of second injection region 5, the third injection region 6 and the 4th injection region 7 is with described the
The upper surface of second medium layer 10 maintains an equal level.Firstly, by the upper surface of second epitaxial layer 4 prepare and cover one layer it is photic anti-
Oxidant layer is lost, photoresist layer is then formed by mask using photoetching.The mask includes the whole of exposure second injection region 5
The opening of the portion of upper surface of upper surface and the third injection region 6.The exposure mask opening by forming grid in etching
13 grooves.Also, again by dissolving or being ashed removal photoresist layer in a solvent after forming 13 groove of grid,
To ultimately form 13 groove of grid.Wherein, the method for etching includes dry etching and wet etching, it is preferred that is used
The method of etching be dry etching, dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching
Easily realize that automation, treatment process are not introduced into pollution, cleannes height.It is formed by 13 groove of grid in this step, for just
In being filled to form grid 13 using filler in the next steps.
It should be noted that forming the first medium layer 8 in 13 channel bottom of grid.It should be understood that described first
Dielectric layer 8 is the insulation gate oxide in the power device, and the insulation gate oxide constitutes the electricity of the power device
Medium.And the first polysilicon layer 9 is formed in 8 upper surface of first medium layer, first polysilicon layer 9 is by the grid 13
Groove fills up, so that the upper surface of first polysilicon layer 9 and the upper surface of 13 groove of grid maintain an equal level.Described first is situated between
Matter layer 8 and first polysilicon layer 9 are used to form the grid 13 of the power device.
In some embodiments of the invention, second dielectric layer 10 is formed also on 4 upper surface of the second epitaxial layer, and
The second dielectric layer 10 also covers side wall and the upper surface of 13 groove of grid, i.e., the described second dielectric layer 10 covers described
The side and upper surface of first medium layer 8 and first polysilicon layer 9.It should be understood that those skilled in the art can be according to reality
Border situation selects different processes to form the first medium layer 8 and the second dielectric layer 10 for meeting above-mentioned condition.
Specifically, the first medium layer 8 and the material of the second dielectric layer 10 are silicon oxide or silicon nitride or silicon oxynitride, specifically
The first medium layer 8 and the second medium can be formed by using sputtering or thermal oxidation method or chemical vapor deposition process
Layer 10.Preferably, the first medium layer 8 and the second dielectric layer 10 are the silicon oxide layer that thermal oxide is formed, subsequent
It adulterates in step, the silicon oxide layer is as protective layer, and by the interlayer insulating film as resulting devices.In addition, described
One dielectric layer 8 and the second dielectric layer 10 are equipped with certain thickness, so that the first medium layer 8 and the second dielectric layer
10 play the role of that electric current and insulation is isolated.More specifically, the second dielectric layer 10 is for being isolated the power device with after
Continuous conductive layer.
Further, the doping concentration of the substrate 1 is higher than the doping concentration of first epitaxial layer 2, outside described first
The doping concentration for prolonging layer 2 is higher than the doping concentration of second epitaxial layer 4, and the doping concentration of the substrate 1 is higher than the third
The doping concentration of injection region 6.In some embodiments of the invention, grown on the substrate 1 first epitaxial layer 2 and
During second epitaxial layer 4, since first epitaxial layer 2 is formed on the basis of substrate 1, outside described second
Prolong layer 4 to be formed on the basis of the first epitaxial layer 2, third epitaxial layer shape on the basis of the second epitaxial layer 4
At, therefore the doping concentration of the substrate 1 is higher than the doping concentration of first epitaxial layer 2.First epitaxial layer 2 at this time
Resistivity is higher than the resistivity of the substrate 1, so as to adjust the integral device resistivity of the power device, obtains more
Surge handling capability.It should be noted that the doping concentration of the substrate 1 is higher than the doping concentration of the third injection region 6, have
Conducive to the breakdown voltage that the power device is adjusted flexibly.
Further, second polysilicon layer 11 includes being formed in the second dielectric layer 10 and connecting described first
The sub- polysilicon layer of the first of polysilicon layer 9 connects first injection region 3 through second epitaxial layer 4 and extends to described
The second sub- polysilicon layer in second dielectric layer 10, and connect the first sub- polysilicon layer and the second sub- polysilicon layer
The sub- polysilicon layer of third.In some embodiments of the invention, the polysilicon layer formed in the first groove is described
First sub- polysilicon layer, the polysilicon layer formed in the second groove is the described second sub- polysilicon layer, in the connection
The polysilicon layer formed in groove is the sub- polysilicon layer of the third.It should be noted that the first sub- polysilicon layer, described
The type of the doping polycrystalline silicon layer formed in second sub- polysilicon layer and the sub- polysilicon layer of the third is all roughly the same, and institute
It is uniform to state the polysilicon layer formed in the first sub- polysilicon layer, the second sub- polysilicon layer and the sub- polysilicon layer of the third
Property is roughly the same, thus by the described first sub- polysilicon layer, the second sub- polysilicon layer and the sub- polysilicon layer of the third
Form the conductive channel of seamless interfacing.
It please refers to attached drawing 7, executes step S05, specifically: formation is separately connected first polysilicon layer 9 and described the
Second polysilicon layer 11 of one injection region 3.In some embodiments of the invention, it is separately connected 9 He of the first polysilicon layer
Second polysilicon layer 11 of first injection region 3 forms leading first polysilicon layer 9 and first injection region 3
Electric channel.Firstly, etching to form the first ditch for extending to first polysilicon layer 9 from 10 upper surface of second dielectric layer
Slot, and the second ditch for extending to first injection region 3 is formed through the second dielectric layer 10 and second epitaxial layer 4
Slot, and etching form from 10 upper surface of second dielectric layer and extend to the connection groove in the second dielectric layer 10, institute
Connection groove is stated to connect the first groove and the second groove.Secondly, in the first groove, second ditch
Polysilicon layer is filled in slot, and forms polysilicon layer in the connection channel bottom.It should be noted that in the connection groove
The polysilicon layer that bottom is formed does not fill up the connection groove.Finally, the polysilicon layer formed in the connection channel bottom
Upper surface forms dielectric layer and the dielectric layer and fills up the connection groove so that the upper surface of the dielectric layer with it is described
The upper surface of second dielectric layer 10 is filled up.According to above-mentioned steps, forms and be separately connected first polysilicon layer 9 and described
The polycrystalline silicon channel of one injection region 3, the section shape in the polycrystalline silicon channel are meander-shaped.
It should be noted that the first groove, the second groove and the connection groove pass through dry etching shape
At dry etching has specific descriptions in the aforementioned embodiment, and details are not described herein.It should be understood that the bottom of the first groove
First polysilicon layer 9 is extended to, the upper surface of the bottom and first polysilicon layer 9 that can be the first groove connects
It connects, the bottom for being also possible to the first groove extends in first polysilicon layer 9.The bottom of the second groove extends
To first injection region 3, the bottom that can be the second groove is connect with the upper surface of first injection region 3, can also
To be that the bottom of the second groove extends in first injection region 3.
In some embodiments of the invention, first polysilicon layer 9 and second polysilicon layer 11 all pass through
What intrinsic polysilicon doping phosphonium ion or boron ion were formed, those skilled in the art can be different according to the structure choice of device
Doped polycrystalline silicon-type, the polysilicon in first polysilicon layer 9 and second polysilicon layer 11 can be p-type polycrystalline
Silicon is also possible to N-type polycrystalline silicon.During forming doped polysilicon layer, the neutral atom in doped polysilicon layer is used for
Doped ions are prevented to agglomerate, Doped ions are used to have suction-operated to silicon atom.Specifically, the extension, diffusion and/or note
The method entered includes depositing operation.In some embodiments of the invention, depositing operation can be selected from electron beam evaporation, chemistry
One of vapor deposition, atomic layer deposition, sputtering.Preferably, low-pressure chemical vapor deposition is used on the substrate 1
(abbreviation LPCVD, i.e. Low Pressure Chemical Vapor Deposition) forms first polysilicon layer 9 and institute
State the second polysilicon layer 11, first polysilicon layer 9 of formation and the purity is high of second polysilicon layer 11, uniformity
It is good.
Attached drawing 8 is please referred to, step S06 is executed, specifically: forming source electrode 12, institute in 10 upper surface of second dielectric layer
It states source electrode 12 and also extends through the second dielectric layer 10 and connect the third injection region 6 and the 4th injection region 7；Described second
The grid 13 connecting with second polysilicon layer 11 is formed in dielectric layer 10；The substrate 1 lower surface formed with it is described
The drain electrode 14 that substrate 1 connects.It in some embodiments of the invention, can be in the second dielectric layer 10 by annealing process
Upper surface formed there is certain thickness the first metal layer, and the first metal layer covers the second dielectric layer 10.Institute
Stating the first metal layer includes the first part for covering 10 upper surface of second dielectric layer, and runs through the second dielectric layer 10
Extend to the second part of the 4th injection region 7 and the third injection region 6.It specifically, can be first in the 4th injection
Contact hole is etched in the portion of upper surface of whole upper surfaces in area 7 and the third injection region 6, and gold is filled in the contact hole
Belong to layer, forms the second part of the first metal layer.It should be understood that the first metal layer is the grid of the power device
13.Specifically, the second metal layer for being formed in the substrate 1 in the lower surface of the substrate 1 and being connect with the substrate 1, institute
Stating second metal layer also has certain thickness, and the second metal layer is the drain electrode 14 of the power device at this time.It needs to illustrate
, the first medium layer 8 and first polysilicon layer 9 form the grid 13 of the power device, the grid 13
It is connect with second polysilicon layer 11.
In some embodiments of the invention, the first metal layer is used for the source electrode 12 and grid of the power device
13 connect, so that metal lead wire draws the source electrode 12 and the grid 13 when encapsulation.
In some embodiments of the invention, it could be covered with above the first metal layer and the second metal layer
Passivation layer, the passivation layer is for protecting the first metal layer and the second metal layer, so that protecting the entire function
Rate device.
Further, the doping concentration of the 4th injection region 7 is higher than the doping concentration of first injection region 3, described
The doping concentration of first injection region 3 is higher than the doping concentration of second injection region 5.In some embodiments of the invention, by
In in ion implanting and/or during diffuse to form the first injection region 3, the ion concentration of injection and/or diffusion wants high
Doped ions concentration in finally formed first injection region 3, to guarantee to form the of the lower heavy doping of resistivity
First injection region 3 of two conduction types.Since second injection region 5 is the area the power device Zhong Ti, when the described 4th
When the doping concentration of injection region 7 is higher than the doping concentration of second injection region 5, the third injection region 6 and the 4th note
Enter area 7 and forms reverse-biased PN junction.Preferably, the doping concentration of first injection region 3 is higher than the doping of second injection region 5
Concentration, since first injection region 3 is used to be formed positive PN junction with first epitaxial layer 2, and second injection region 5
For forming Ohmic contact with first epitaxial layer 2, the generation of device punchthrough effect is prevented, to prevent parasitic N-channel
Field-effect tube is opened.Therefore, when voltage is reverse-biased, the positive PN junction of first injection region 3 and first epitaxial layer 2 formation
Breakdown voltage need it is larger, thus need first injection region 3 doping concentration be higher than second injection region 5 doping
Concentration to reduce the dead resistance of second injection region 5, and reduces between the grid 13 and the drain electrode 14
Parasitic capacitance.
Further, by first injection region 3, the third injection region 6, the first medium layer 8, described more than first
Crystal silicon layer 9 and second polysilicon layer 11 are symmetrical arranged relative to the 4th injection region 7.In some implementations of the invention
In example, the primitive unit cell of the power device is a symmetrical structure, and the power device with symmetrical structure can specifically have
One primitive unit cell, can also be there are two primitive unit cell.In addition, in other embodiments of the invention, to form institute on the substrate 1
For two layers of epitaxial structure for stating the first epitaxial layer 2 and second epitaxial layer 4, but it is not limited only to this.It should be understood that in technique
On, it is only necessary to carry out epitaxy technique is with regard to achievable twice, moreover, by first injection region 3, the third injection region 6,
The first medium layer 8, first polysilicon layer 9 and second polysilicon layer 11 are relative to the 4th injection region 7
It is symmetrical arranged, so that the technology difficulty of symmetrical structure is lower than the technology difficulty of asymmetric structure in technique, from
And improve production efficiency；In structure, symmetrical structure can reduce the defect of the power device, it is easier to realize its property
Energy.
The embodiment of the present invention is by drawing polycrystalline silicon channel from first polysilicon layer 9, and by the polysilicon
Conductive channel is connected to first injection region 3, so that in parallel one between the grid 13 and drain electrode 14 of the power device
The PN junction of a positively biased reduces the power device to reduce the parasitic capacitance between the grid 13 and the drain electrode 14
The switching loss of part, while 13 Surge handling capability of grid is greatly improved, improve the power device
Performance.
As shown in Fig. 2, the embodiment of the present invention provides a kind of power device, shown power device includes:
The substrate 1 of first conduction type；
First epitaxial layer 2 of the first conduction type is grown on 1 upper surface of substrate；
First injection region 3 of the second conduction type, is formed in first epitaxial layer 2；
Second epitaxial layer 4 of the first conduction type is formed in 2 upper surface of the first epitaxial layer；
Second injection region 5 of the second conduction type, is formed in second epitaxial layer 4；
The of the third injection region 6 of first conduction type and the second conduction type being connect with the third injection region 6
Four injection regions 7 are formed in second injection region 5, and the doping concentration of the 4th injection region 7 is higher than second injection region
5 doping concentration；
First medium layer 8, is formed in the upper surface of second injection region 5, and the first medium layer 8 connects the third
The portion of upper surface of injection region 6；
First polysilicon layer 9 is formed in 8 upper surface of first medium layer；
Second dielectric layer 10, is formed in 4 upper surface of the second epitaxial layer, and the second dielectric layer 10 covers described first
Dielectric layer 8 and first polysilicon layer 9；
Second polysilicon layer 11 is separately connected first polysilicon layer 9 and first injection region 3；
Source electrode 12 is formed in the upper surface of the second dielectric layer 10 and through the second dielectric layer 10 and the third
Injection region 6 and the 4th injection region 7 connection；
Grid 13 is formed in the second dielectric layer 10 and connect with second polysilicon layer 11；
Drain electrode 14, is formed in the lower surface of the substrate 1 and connect with the substrate 1.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
In next embodiment, adulterated by p-type of first conduction type, second conduction type is that n-type doping is
Example is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
In some embodiments of the invention, as shown in Fig. 2, the power device includes the substrate 1 of the first conduction type
With the first epitaxial layer 2 of the first conduction type, first epitaxial layer 2 is grown on 1 upper surface of substrate.Specifically, described
Substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, and the substrate 1 also assists in the integrated circuit
Work.The substrate 1 can be silicon substrate, or Sapphire Substrate can also be silicon Chu substrate, it is preferred that the lining
Bottom 1 is silicon substrate, this is because silicon substrate material has the characteristics that low cost, large scale, conductive, avoids edge effect,
Yield can be increased substantially.
Current Transient Voltage Suppressor is largely only adapted to form the suppression of single channel transient voltage in a chip
Device processed.In order to form multichannel Transient Voltage Suppressor, then need to form a channel unit in respective chip respectively, so
By by bonding wire, each chip is electrically connected to each other to form array.Bonding wire between chip leads to packaging cost
Increase, and introduce lead resistance and parasitic capacitance, so that the reliability of semiconductor devices reduces.
In conclusion the power device overall structure is symmetrical and is the first primitive unit cell.
Please refer to the equivalent circuit diagram of power unit structure shown in Fig. 9.When logical to the source electrode 12 and the drain electrode 14
When electric, the electric current flows to the drain electrode 14 from the source electrode 12.It should be noted that PN junction formed below is positive and anti-
To N-type is set as with the first conduction type, it is one embodiment of the present of invention to be sentenced that second conduction type, which is set as p-type,
It is disconnected, but not to this restriction.When electric current is flowed into from the source electrode 12 and the grid 13, while forming channel, electric current is also
It is flowed in the parallel branch of the power device by the conductive channel that second polysilicon layer 11 is formed.First injection
Area 3 and first epitaxial layer 2 form the PN junction of positively biased, so as to form positive diode a.Due to being formed in the first primitive unit cell
Symmetrical structure, therefore first injection region 3, the third injection region 6, the first medium layer 8, first polycrystalline
The quantity of silicon layer 9 and second polysilicon layer 11 is for two and symmetrical, so that two symmetrical positively biased PN junctions are formed, so that
There are two symmetrical forward diode a for tool in the equivalent circuit that the power device is formed.
It should be noted that since the power device overall structure is symmetrical and is the first primitive unit cell, but first primitive unit cell
Be not the smallest primitive cell structure in the power device, minimum primitive unit cell be first injection region 3, the third injection region 6,
The quantity of the first medium layer 8, first polysilicon layer 9 and second polysilicon layer 11 only has one.For convenience
Illustrating, the embodiment of the present invention specifically describes the structure of the power device by taking first primitive unit cell as an example, but is not limited only to this,
Those skilled in the art can the primitive unit cell of the power device determines according to actual conditions specific structure.
The technical solution of the embodiment of the present invention is had been described in detail above with reference to the accompanying drawings, the embodiment of the present invention is in conventional power device
It is improved on the basis of part and proposes a kind of a kind of grid positive feedback power device formed by process modification, by two
It is formed in the substrate 1 of secondary extension, first epitaxial layer 2, second epitaxial layer 4 and second epitaxial layer 4
First injection region 3, and second polysilicon layer 11 connecting with grid 13, i.e. conductive channel are formed, so as to form
Parallel branch with diodes in parallel.This not only lowers parasitic capacitances, and due to the diode in parallel of the grid 13,
Parallel diode can prevent surge current Damage to insulation gate oxide, enhance the Anti-surging ability of the power device.It improves
Power device afterwards is by reducing the parasitic capacitance between the grid 13 and the drain electrode 14, to reduce the power device
The switching loss of part, so that the protection feature and reliability of the power device are all improved.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (10)
1. a kind of power device characterized by comprising
The substrate of first conduction type；
First epitaxial layer of the first conduction type, is grown on the upper surface of substrate；
First injection region of the second conduction type is formed in first epitaxial layer；
Second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；
Second injection region of the second conduction type is formed in second epitaxial layer；
4th injection of the third injection region of the first conduction type and the second conduction type being connect with the third injection region
Area is formed in second injection region, and the doping that the doping concentration of the 4th injection region is higher than second injection region is dense
Degree；
First medium layer, is formed in the upper surface of second injection region, and the first medium layer connects the third injection region
Portion of upper surface；
First polysilicon layer is formed in first medium layer upper surface；
Second dielectric layer, is formed in second epitaxial layer upper surface, the second dielectric layer cover the first medium layer and
First polysilicon layer；
Second polysilicon layer is separately connected first polysilicon layer and first injection region；
Source electrode is formed in the upper surface of the second dielectric layer and through the second dielectric layer and the third injection region and institute
State the connection of the 4th injection region；
Grid is formed in the second dielectric layer and connect with second polysilicon layer；
Drain electrode, is formed in the lower surface of the substrate and connect with the substrate.
2. power device according to claim 1, which is characterized in that the doping concentration of the substrate is higher than outside described first
Prolong the doping concentration of layer, the doping concentration of first epitaxial layer is higher than the doping concentration of second epitaxial layer, the substrate
Doping concentration be higher than the third injection region doping concentration.
3. power device according to claim 1, which is characterized in that the doping concentration of the 4th injection region is higher than described
The doping concentration of first injection region, the doping concentration of first injection region are higher than the doping concentration of second injection region.
4. power device according to claim 1, which is characterized in that first injection region, the third injection region, institute
First medium layer, first polysilicon layer and second polysilicon layer is stated symmetrically to set relative to the 4th injection region
It sets.
5. power device according to claim 1, which is characterized in that second polysilicon layer includes being formed in described the
In second medium layer and the first sub- polysilicon layer of first polysilicon layer is connected, through second epitaxial layer connection described the
One injection region simultaneously extends to the second sub- polysilicon layer in the second dielectric layer, and the connection first sub- polysilicon layer and
The sub- polysilicon layer of third of the second sub- polysilicon layer.
6. a kind of production method of power device comprising:
The substrate of first conduction type is provided；
First epitaxial layer of one conduction type of surface growth regulation over the substrate；
The first injection region of the second conduction type is formed in first epitaxial layer；
The second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；
The second injection region of the second conduction type is formed in second epitaxial layer；
It forms the third injection region of the first conduction type in second injection region and is connect with the third injection region
4th injection region of the second conduction type, the doping that the doping concentration of the 4th injection region is higher than second injection region are dense
Degree；
First medium layer is formed in the upper surface of second injection region, the first medium layer is connected into the third injection region
Portion of upper surface；
The first polysilicon layer is formed in first medium layer upper surface；
Form second dielectric layer in second epitaxial layer upper surface, by the second dielectric layer cover the first medium layer and
First polysilicon layer；
Form the second polysilicon layer for being separately connected first polysilicon layer and first injection region；
Source electrode is formed in the second dielectric layer upper surface, the source electrode also extends through the second dielectric layer and connects the third note
Enter area and the 4th injection region；
The grid connecting with second polysilicon layer is formed in the second dielectric layer；
The drain electrode connecting with the substrate is formed in the lower surface of the substrate.
7. a kind of production method of power device according to claim 6, which is characterized in that the doping concentration of the substrate
Higher than the doping concentration of first epitaxial layer, the doping concentration of first epitaxial layer is higher than the doping of second epitaxial layer
Concentration, the doping concentration of the substrate are higher than the doping concentration of the third injection region.
8. a kind of production method of power device according to claim 6, which is characterized in that mix the 4th injection region
Miscellaneous concentration is higher than the doping concentration of first injection region, and the doping concentration of first injection region is higher than second injection region
Doping concentration.
9. a kind of production method of power device according to claim 6, which is characterized in that by first injection region,
The third injection region, the first medium layer, first polysilicon layer and second polysilicon layer are relative to described
4th injection region is symmetrical arranged.
10. a kind of production method of power device according to claim 6, which is characterized in that second polysilicon layer
The first sub- polysilicon layer including being formed in the second dielectric layer and connecting first polysilicon layer runs through described second
Epitaxial layer connects first injection region and extends to the second sub- polysilicon layer in the second dielectric layer, and described in connection
The sub- polysilicon layer of third of first sub- polysilicon layer and the second sub- polysilicon layer.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010012671A1 (en) * | 1999-09-21 | 2001-08-09 | Yutaka Hoshino | Semiconductor device and a method of manufacturing the same |
| CN103035720A (en) * | 2012-09-05 | 2013-04-10 | 上海华虹Nec电子有限公司 | Super junction device and manufacturing method thereof |
| CN104867972A (en) * | 2014-02-20 | 2015-08-26 | 北大方正集团有限公司 | Double diffusion metal-oxide-semiconductor (DMOS) device of integrated driving resistor and method for manufacturing same |
| CN107170738A (en) * | 2017-05-22 | 2017-09-15 | 安徽富芯微电子有限公司 | A kind of unidirectional TVS device of low electric capacity and its manufacture method |
| CN108054164A (en) * | 2017-12-12 | 2018-05-18 | 深圳迈辽技术转移中心有限公司 | Transient Voltage Suppressor and preparation method thereof |
-
2018
- 2018-09-04 CN CN201811024201.XA patent/CN109192782A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010012671A1 (en) * | 1999-09-21 | 2001-08-09 | Yutaka Hoshino | Semiconductor device and a method of manufacturing the same |
| CN103035720A (en) * | 2012-09-05 | 2013-04-10 | 上海华虹Nec电子有限公司 | Super junction device and manufacturing method thereof |
| CN104867972A (en) * | 2014-02-20 | 2015-08-26 | 北大方正集团有限公司 | Double diffusion metal-oxide-semiconductor (DMOS) device of integrated driving resistor and method for manufacturing same |
| CN107170738A (en) * | 2017-05-22 | 2017-09-15 | 安徽富芯微电子有限公司 | A kind of unidirectional TVS device of low electric capacity and its manufacture method |
| CN108054164A (en) * | 2017-12-12 | 2018-05-18 | 深圳迈辽技术转移中心有限公司 | Transient Voltage Suppressor and preparation method thereof |
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Application publication date: 20190111 |