CN109192664A - A kind of low-temperature polysilicon film transistor, preparation method and array substrate - Google Patents
A kind of low-temperature polysilicon film transistor, preparation method and array substrate Download PDFInfo
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- CN109192664A CN109192664A CN201811067545.9A CN201811067545A CN109192664A CN 109192664 A CN109192664 A CN 109192664A CN 201811067545 A CN201811067545 A CN 201811067545A CN 109192664 A CN109192664 A CN 109192664A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 title claims abstract description 30
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000010936 titanium Substances 0.000 claims abstract description 43
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000001312 dry etching Methods 0.000 claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 16
- 239000004411 aluminium Substances 0.000 claims abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000012545 processing Methods 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 239000002245 particle Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000006073 displacement reaction Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 125
- 239000010408 film Substances 0.000 description 55
- 239000000460 chlorine Substances 0.000 description 24
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium chloride Substances Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 14
- 239000007789 gas Substances 0.000 description 10
- KLZUFWVZNOTSEM-UHFFFAOYSA-K Aluminium flouride Chemical compound F[Al](F)F KLZUFWVZNOTSEM-UHFFFAOYSA-K 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000012805 post-processing Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910021502 aluminium hydroxide Inorganic materials 0.000 description 3
- 239000004568 cement Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910001679 gibbsite Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010494 dissociation reaction Methods 0.000 description 2
- 230000005593 dissociations Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910003074 TiCl4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- WNROFYMDJYEPJX-UHFFFAOYSA-K aluminium hydroxide Chemical compound [OH-].[OH-].[OH-].[Al+3] WNROFYMDJYEPJX-UHFFFAOYSA-K 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
The embodiment of the invention discloses a kind of low-temperature polysilicon film transistor, preparation method and array substrates, the described method includes: providing substrate, buffer layer, low-temperature polycrystalline silicon layer, source contact area, drain contact region, gate insulating layer, grid layer and dielectric layer are sequentially formed on the substrate；It is respectively formed the first contact hole and the second contact hole through the dielectric layer and the gate insulating layer by dry etching, respectively by the source contact area and drain contact region exposure；Titanium/aluminium/titanium three-decker film layer is deposited on the dielectric layer；Using C2HF5Gas carries out plasma cleaning processing to the source electrode and drain electrode surface.Implement the present invention, the effect of preparation source electrode and drain electrode last handling process can be improved and reduces cost.
Description
Technical field
The present invention relates to low-temperature polysilicon film transistor (LTPS-TFF) technical field, in particular to a kind of low-temperature polysilicons
Silicon thin film transistor, preparation method and array substrate.
Background technique
Currently, in traditional low-temperature polysilicon film transistor (LTPS-TFT) preparation process, to titanium/aluminium/titanium (Ti/AL/
Ti) film layer forms source/drain (Source/Drain) driver circuit after stemness (Dry Etch) etching；And Ti/AL/Ti
Film layer generally uses chlorine (CL in stemness etching process2) perform etching, in CL2After the completion of etching, CL and AL are with AlCL3's
Form is attached to the surface of AL film layer, and in particular to chemical reaction it is as follows:
Cl2 Cl?+ Cl++ Cl*+Cl2*
Ti+Cl*+Cl? TiClx↑ (wherein TiClxWith TiCl4Based on, while having excessive state compound)
Al+ Cl*+Cl? ALClx↑ (wherein AlClxWith AlCl3Based on, while having excessive state compound)
AlCl3+H2O+O2 Al(OH)3↓+HCl(prevents)
And in low-temperature polysilicon film transistor (LTPS) and active matrix organic light-emitting diode (AMOLED) array substrate
(Array) in processing procedure, Ti/AL/Ti film layer generally uses CF after over etching4Add O2In power (Source
Power F* and O* ionizing particle is formed under ionization) and is post-processed (After treatment, AT), i.e., using ionization grain
Son cleans Ti/AL/Ti film layer, to prevent AlCl3+H2O+O2 Al(OH)3The generation of this reaction of ↓+HCl, it is main
Principle is to replace ALCl by displacement reaction with F*3In Cl, detailed process is as follows:
CF4 F?+ F++ F*+CFx*
F?+ F*+AlCl3 AlF3+ Cl?+ Cl*
Due to AlCl3Belong to molecular crystal, very soluble in water (45.8g/100mL), AlF3Belong to ionic crystals, is insoluble in
Water；The generation of AL corrosion effect is prevented by the effect that occurs with of above-mentioned reaction.
But for CF4This compound, C-F belong to covalent bond, and C, F binding force are especially strong, if it is total to interrupt C-F
Valence link, it is desirable to provide very high additional energy, therefore for dry etching equipment, higher power is needed, this is for work
For factory, higher electric power just will use, i.e. electricity consumption is more；While in order to guarantee the F*, CF that have sufficient4It must be passed through higher
The CF of flow4, will increase plant investment cost in this way；The place therefore treatment effect of existing this mode comes with some shortcomings,
As shown in Figure 1, showing in the prior art using CF4On to Ti-AL-Ti film layer perform etching post-processing formed structure part
Structural schematic diagram；There it can be seen that using CF4The product film layer of post-processing acquisition is carried out as a result, its film layer side wall invaginates, is same
When film surface can have concave-convex corrosion.
Summary of the invention
Technical problem to be solved by the present invention lies in, provide a kind of low-temperature polysilicon film transistor preparation method,
The effect and drop of preparation source electrode and drain electrode last handling process can be improved in low-temperature polysilicon film transistor and array substrate
Low cost.
In order to solve the above-mentioned technical problem, the one side of the embodiment of the present invention provides a kind of low-temperature polysilicon film crystal
The preparation method of pipe comprising:
Substrate is provided, sequentially forms buffer layer, low-temperature polycrystalline silicon layer, source contact area, drain contact region, grid on the substrate
Pole insulating layer, grid layer and dielectric layer, the source contact area and the drain contact region are set with the low temperature polycrystalline silicon same layer
It sets, and is separately positioned on the opposite both ends of the low-temperature polycrystalline silicon layer；
The first contact hole and the second contact through the dielectric layer and the gate insulating layer are respectively formed by dry etching
Hole, respectively by the source contact area and drain contact region exposure；
Titanium/aluminium/titanium three-decker film layer is deposited on the dielectric layer, and source electrode and leakage are respectively formed by dry etching
Pole, the source electrode are connected by first contact hole with the source contact area, and the drain electrode is contacted by described second
Hole is connected with the drain contact region；
Using C2HF5Gas carries out plasma cleaning processing to the source electrode and drain electrode surface.
Wherein, titanium/aluminium/titanium three-decker film layer is deposited on the dielectric layer, and is respectively formed by dry etching
In the step of source electrode and drain electrode, comprising:
Using CL2Gas performs etching the film layer of the titanium/aluminium/titanium three-decker, is respectively formed source electrode and drain electrode, is etching
After the completion, free AlCL is attached in the aluminium film layer surface of titanium/aluminium/titanium three-decker film layer3。
Wherein, using C2HF5Gas to the source electrode and drain electrode surface carry out plasma cleaning processing the step of include:
In dry etching equipment, to C2HF5Gas is ionized, F* and H* particle is formed；
When carrying out plasma cleaning processing, the F* particle AlCl free with source electrode and drain electrode surface3It is reacted, is replaced
AlCl out3In CL* particle；The H* particle reacts the Cl to be formed with above-mentioned displacement?Particle and Cl* particle combine, and make institute
Displacement reaction is stated to continue to carry out to positive direction.
Wherein, the material of the gate insulating layer includes at least one of silicon nitride and silica；The dielectric layer
Material includes at least one of silicon nitride and silica.
Another aspect of the present invention also provides a kind of low-temperature polysilicon film transistor, uses low-temperature polysilicon above-mentioned
The preparation method of silicon thin film transistor is prepared.
Wherein, table of the source electrode in the source contact area with the separate buffer layer of the low-temperature polycrystalline silicon layer
Face contact, the drain electrode contact in the drain contact region with the surface far from the buffer layer of low-temperature polycrystalline silicon layer.
Another aspect of the invention also provides a kind of array substrate comprising low-temperature polysilicon film transistor above-mentioned.
It wherein, further include flatness layer, anode and the pixel defining layer being located on the low-temperature polysilicon film transistor,
In, via hole is equipped in the flatness layer, the anode passes through the leakage in the via hole and the low-temperature polysilicon film transistor
Pole is electrically connected；On the flat laye, the pixel defining layer is equipped with opening for exposing for the pixel defining layer setting
The part anode, the opening is for being arranged the OLED device being connected with the anode.
The implementation of the embodiments of the present invention has the following beneficial effects:
In an embodiment of the present invention, during preparing low-temperature polysilicon film transistor, Ti/AL/Ti film layer is used
CL2After carrying out dry etching, using C2HF5It is post-processed, due to C2HF5Ionization is low with required energy is dissociated, i.e., dry etching is set
For standby, lower power ensures that C2HF5There are higher degree of ionization and degree of dissociation, can not only provide enough
F*, and enough H* can be provided, plant investment cost can be saved；
Due to the introducing of H*, attachment and the Cl* of film surface can be made thoroughly to cement out, improve displacement efficiency；Effectively
The corrosion for preventing Al film layer；For using C2HF5The film layer side wall obtained as post-processing step be smooth, no concave-convex, nothing
Phenomena such as indent, improves product yield.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is in the prior art using CF4On to Ti-AL-Ti film layer perform etching post-processing formed structure part
Structural schematic diagram；
Fig. 2 is that a kind of main flow of one embodiment of the preparation method of low-temperature polysilicon film transistor provided by the invention shows
It is intended to；
Fig. 3 is the base that buffer layer, low-temperature polycrystalline silicon layer, gate insulating layer, grid layer and dielectric layer are formed in the step S10 of Fig. 2
Plate schematic diagram；
Fig. 4 be Fig. 2 step S12 in be formed with the schematic diagram of substrate structure of the first contact hole and the second contact hole；
Fig. 5 be Fig. 2 step S14 in be formed with the schematic diagram of substrate structure of source electrode and drain electrode；
Fig. 6 is the partial structural diagram of source electrode and drain electrode film layer that is formed in the step S16 of Fig. 2；
Fig. 7 is a kind of structural schematic diagram of one embodiment of low-temperature polysilicon film transistor provided by the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear and complete
Ground description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without making creative work it is obtained it is all its
Its embodiment, shall fall within the protection scope of the present invention.
Here, it should also be noted that, in order to avoid having obscured the present invention because of unnecessary details, in the accompanying drawings only
Show with closely related structure and/or processing step according to the solution of the present invention, and be omitted little with relationship of the present invention
Other details.
As shown in Fig. 2, being a kind of main flow chart of the preparation method of low-temperature polysilicon film transistor provided by the invention；
It combines together shown in Fig. 2-7, in the present embodiment, which comprises
Step S10, provides substrate, sequentially forms buffer layer, low-temperature polycrystalline silicon layer, source contact area, drain electrode on the substrate
Contact zone, gate insulating layer, grid layer and dielectric layer, the source contact area and the drain contact region and the low-temperature polysilicon
The setting of silicon same layer, and it is separately positioned on the opposite both ends of the low-temperature polycrystalline silicon layer；
There is provided substrate 1, sequentially formed on the substrate 1 buffer layer 2, low-temperature polycrystalline silicon layer 3, source contact area 31, drain electrode connect
Touch area 32, gate insulating layer 4, grid layer 5 and dielectric layer 6, the source contact area 31 and the drain contact region 32 with it is described
The setting of 3 same layer of low-temperature polycrystalline silicon layer, and it is separately positioned on the opposite both ends of the low-temperature polycrystalline silicon layer 3.
In the present embodiment, when the cleanliness of substrate 1 is unsatisfactory for requiring, prerinse is carried out to substrate 1 first.It is optional
The material on ground, substrate 1 is unlimited, can be glass substrate or flexible base board etc..
In the present embodiment, by the vapour deposition process (PECVD) of coating process such as plasma enhanced chemical in substrate 1
The upper buffer layer (Buffer) 2 for forming one layer of entire substrate of covering.Optionally, the material of buffer layer 2 includes silicon nitride (SiNx)
With silica (SiOxAt least one of).Still optionally further, the material of buffer layer 2 can for single layer membranous layer of silicon oxide or
Silicon nitride film layer, or the lamination for silica and silicon nitride.
In the present embodiment, by coating process (such as PECVD) on the buffer layer 2 deposition of amorphous silicon layers.Amorphous silicon
Layer covering part buffer layer, makes annealing treatment the amorphous silicon layer, the amorphous silicon layer is made to be changed into low-temperature polycrystalline silicon layer
(poly-silicon) 3.Specifically, recrystallized amorphous silicon is made to be changed into polysilicon by radium-shine crystallization (ELA) technique of quasi-molecule, so
Afterwards to the polysilicon graphics, forming low-temperature polycrystalline silicon layer 3 can be specifically patterned by photoetching process.It is optional
Ground, the source contact area 31 and the drain contact region 32 and 3 same layer of low-temperature polycrystalline silicon layer are arranged, and are separately positioned on
The opposite both ends of the low-temperature polycrystalline silicon layer 3.
In the present embodiment, gate insulating layer 4 (GI), institute are deposited on the low-temperature polycrystalline silicon layer 3 by coating process
It states gate insulating layer 4 and the area that the low-temperature polycrystalline silicon layer 3 and buffer layer 2 are not covered by the low-temperature polycrystalline silicon layer 3 is completely covered
Domain.Optionally, the material of gate insulating layer 4 includes at least one of silicon nitride and silica.Still optionally further, grid is exhausted
The material of edge layer 4 can be the silicon nitride perhaps silica of single layer or the lamination formed for silica and silicon nitride of single layer.
In the present embodiment, by physical vapor deposition (PVD) on the gate insulating layer 4 depositing layers 5, it is described
5 covering part gate insulating layer 4 of grid layer.Optionally, the material of the grid layer 5 can be metal or alloy, such as one
In a example, the material of the grid layer 5 is metal molybdenum (Mo).
It in the present embodiment, is exposure mask to the low-temperature polycrystalline silicon layer 3 progress ion doping with the grid layer 5, thus
The ohmic contact regions that being formed in the low-temperature polycrystalline silicon layer can contact with source-drain electrode form source contact area 31 and leakage
Pole contact zone 32, the ion of the doping can be but be not limited only to for boron (B) ion.
In the present embodiment, by coating process (such as PECVD) on the grid layer 5 and the gate insulating layer 4
Dielectric layer 6 is covered on the region covered by grid layer 5, then by rapid thermal annealing (RTA) technique short annealing to live
Change.Optionally, the material of the dielectric layer 6 includes at least one of silicon nitride and silica.Still optionally further, it is given an account of
The material of electric layer 6 can be the silicon nitride perhaps silica of single layer or the lamination formed for silica and silicon nitride of single layer.
Step S12 is respectively formed the first contact through the dielectric layer and the gate insulating layer by dry etching
Hole 71 and the second contact hole 72, respectively by the source contact area 31 and the exposure of the drain contact region 32；Specifically, exist
In one example, the etching gas that the dry etching uses includes fluoro-gas and hydrogen.
Step S14 deposits titanium/aluminium/titanium three-decker film layer on the dielectric layer, and distinguishes shape by dry etching
At source electrode 8 and drain electrode 9.Wherein, the source electrode 8 is connected by first contact hole 71 with the source contact area 31, institute
Drain electrode 9 is stated to be connected by second contact hole 72 with the drain contact region 32；
In the present embodiment, physical vapor deposition (PVD) process deposits source electrode 8 and drain electrode 9 are utilized.In the present embodiment, source electrode 8
Material with drain electrode 9 is Ti/Al/Ti(titanium/aluminium/titanium) laminated composite materials., after the completion of etching, in titanium/aluminium/titanium three-layered node
The aluminium film layer surface of the film layer of structure is attached with free AlCL3。
Step S16, using C2HF5Gas carries out plasma cleaning processing to the source electrode and drain electrode surface.
In dry etching equipment, to C2HF5Gas is ionized, F* and H* particle is formed；Specifically, in one example, may be used
It is 30-50mtorr in air pressure, gas source power is 400-800W, bias voltage 100-200V to use plasma generator
Under conditions of prepare each C2HF5The plasma of gas.
When carrying out plasma cleaning processing, the F* particle AlCl free with source electrode and drain electrode surface3It is reacted,
Displace AlCl3In CL* particle；The H* particle reacted with above-mentioned displacement in the Cl that is formed?Particle is mutually tied with Cl* particle
It closes, the displacement reaction is made to continue to carry out to positive direction.
In embodiments of the present invention, using C2HF5For F* and H* particle source, to chemically react F?+ F*+AlCl3 AlF3+
Cl?+ Cl* provides F*；Enough H* can also be provided simultaneously, to combine Cl?And Cl*, make to chemically react F?+ F*+AlCl3
AlF3+ Cl?+ Cl* continues to carry out to positive direction；To reduce AlCl3Content, prevent AlCl in the prior art3+H2O+O2 Al(OH)3The generation of ↓+HCl reaction；
Meanwhile in an embodiment of the present invention, using C2HF5To substitute CF in the prior art4And O2, an other advantage
It is exactly C2HF5In the binding force of C-F key will be well below CF4The binding force of middle C-F, therefore interrupt C2HF5In C-F key needed for
The energy wanted will be well below interrupting CF4The energy of middle C-F.
As shown in fig. 6, using C2HF5As AT(After treatment) expected results that are post-processed of step, with
It cements out attachment and the Cl* of film surface thoroughly, improves displacement efficiency；Effectively prevent the corrosion of Al film layer；Its
Film layer side wall is smooth, no concave-convex corrodes.
In some instances, after the low-temperature polysilicon film transistor is made, in the drain electrode 8 and the drain electrode 9
It is upper that flatness layer 10 is formed by deposition and patterning process, via hole is opened up on the flatness layer 10 for exposing the drain electrode 9；
Then anode 11 is formed by deposition and patterning process at the via hole so that the anode 11 drains 9 electrically with described
Connect；Pixel defining layer 12 is formed on the flatness layer 10 and the anode 11, is formed and is opened in the pixel defining layer 12
Mouth is finally used in opening vapor deposition Organic Light Emitting Diode (OLED) luminous organic material with exposing the part anode 11
It is connected with the anode 11, completes the production of OLED device.
Second aspect of the embodiment of the present invention provides a kind of low-temperature polysilicon film transistor, the low-temperature polysilicon film
Transistor is prepared using the preparation method of low-temperature polysilicon film transistor described in above-mentioned first aspect.The low temperature is more
The structure of polycrystal silicon film transistor sees the structure of low-temperature polysilicon film transistor shown in fig. 5.
The third aspect of the embodiment of the present invention provides a kind of array substrate, and the array substrate includes low temperature described above
Polycrystalline SiTFT.
Refering to Fig. 7, in the present embodiment, the array substrate further includes being located on the low-temperature polysilicon film transistor
10, anode 11(Anode flatness layer (PLN)) and pixel defining layer 12, wherein via hole, the anode are equipped in the flatness layer
11 are electrically connected by the via hole and the drain electrode 9 in the low-temperature polysilicon film transistor；The pixel defining layer 12 is set
It sets on the flatness layer 10, the pixel defining layer 12 is equipped with opening for exposing the part anode 11, the opening
Place is for being arranged the OLED device 13 to connect with the anode 11.
In one example, 10 material of flatness layer is organic insulating material.Further, 10 material of flatness layer is
Polyimides.The anode 11 can be the materials such as tin indium oxide (IT0), indium zinc oxide (IZO) or aluminum zinc oxide.Pixel defining layer
12 material can be polyimide material.
The implementation of the embodiments of the present invention has the following beneficial effects:
In an embodiment of the present invention, during preparing low-temperature polysilicon film transistor, Ti/AL/Ti film layer is used
CL2After carrying out dry etching, using C2HF5It is post-processed, due to C2HF5Ionization is low with required energy is dissociated, i.e., dry etching is set
For standby, lower power ensures that C2HF5There are higher degree of ionization and degree of dissociation, can not only provide enough
F*, and enough H* can be provided, plant investment cost can be saved；
Due to the introducing of H*, attachment and the Cl* of film surface can be made thoroughly to cement out, improve displacement efficiency；Effectively
The corrosion for preventing Al film layer；For using C2HF5The film layer side wall obtained as post-processing step be smooth, no concave-convex, nothing
Phenomena such as indent, improves product yield.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The above is only the specific embodiment of the application, it is noted that for the ordinary skill people of the art
For member, under the premise of not departing from the application principle, several improvements and modifications can also be made, these improvements and modifications are also answered
It is considered as the protection scope of the application.
Claims (8)
1. a kind of preparation method of low-temperature polysilicon film transistor characterized by comprising
Substrate is provided, sequentially forms buffer layer, low-temperature polycrystalline silicon layer, source contact area, drain contact region, grid on the substrate
Pole insulating layer, grid layer and dielectric layer, the source contact area and the drain contact region are set with the low temperature polycrystalline silicon same layer
It sets, and is separately positioned on the opposite both ends of the low-temperature polycrystalline silicon layer；
The first contact hole and the second contact through the dielectric layer and the gate insulating layer are respectively formed by dry etching
Hole, respectively by the source contact area and drain contact region exposure；
Titanium/aluminium/titanium three-decker film layer is deposited on the dielectric layer, and source electrode and leakage are respectively formed by dry etching
Pole, the source electrode are connected by first contact hole with the source contact area, and the drain electrode is contacted by described second
Hole is connected with the drain contact region；
Using C2HF5Gas carries out plasma cleaning processing to the source electrode and drain electrode surface.
2. the method as described in claim 1, which is characterized in that deposit titanium/aluminium/titanium three-decker film on the dielectric layer
Layer, and in the step of being respectively formed source electrode and drain electrode by dry etching, comprising:
Using CL2Gas performs etching the film layer of the titanium/aluminium/titanium three-decker, is respectively formed source electrode and drain electrode, is etching
After the completion, free AlCL is attached in the aluminium film layer surface of titanium/aluminium/titanium three-decker film layer3。
3. method according to claim 2, which is characterized in that use C2HF5Gas carries out the source electrode and drain electrode surface etc.
Ion Cleaning processing the step of include:
In dry etching equipment, to C2HF5Gas is ionized, F* and H* particle is formed；
When carrying out plasma cleaning processing, the F* particle AlCl free with source electrode and drain electrode surface3It is reacted, is replaced
AlCl out3In CL* particle；The H* particle reacts the Cl to be formed with above-mentioned displacement?Particle and Cl* particle combine, and make institute
Displacement reaction is stated to continue to carry out to positive direction.
4. method as claimed in claim 3, which is characterized in that the material of the gate insulating layer includes silicon nitride and silica
At least one of；The material of the dielectric layer includes at least one of silicon nitride and silica.
5. a kind of low-temperature polysilicon film transistor, which is characterized in that more using low temperature according to any one of claims 1-4
The preparation method of polycrystal silicon film transistor is prepared.
6. low-temperature polysilicon film transistor as claimed in claim 5, which is characterized in that the source electrode is in the source contact
Low-temperature polycrystalline silicon layer described in Qu Zhongyu far from the buffer layer surface contact, it is described drain electrode in the drain contact region with
The surface far from the buffer layer of low-temperature polycrystalline silicon layer contacts.
7. a kind of array substrate, which is characterized in that including low-temperature polysilicon film transistor such as described in claim 5 or 6.
8. array substrate as claimed in claim 7, which is characterized in that further include being located at the low-temperature polysilicon film transistor
On flatness layer, anode and pixel defining layer, wherein in the flatness layer be equipped with via hole, the anode by the via hole with
Drain electrode in the low-temperature polysilicon film transistor is electrically connected；The pixel defining layer is arranged on the flat laye, institute
It states pixel defining layer and is equipped with opening for exposing the part anode, the opening is used to be arranged to be connected with the anode
OLED device.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN88100380A (en) * | 1987-01-23 | 1988-10-19 | 德索托公司 | Form the monolayer carbon fluorine cpd protective cover of anodized aluminum table |
| US6069087A (en) * | 1998-08-25 | 2000-05-30 | Micron Technology, Inc. | Highly selective dry etching process |
| US6209483B1 (en) * | 1996-10-17 | 2001-04-03 | Accord S. E. G. | Apparatus and method for removing silicon dioxide residues from CVD reactors |
| US6235640B1 (en) * | 1998-09-01 | 2001-05-22 | Lam Research Corporation | Techniques for forming contact holes through to a silicon layer of a substrate |
| US20030003755A1 (en) * | 2001-06-28 | 2003-01-02 | Micron Technology, Inc. | Etching of high aspect ratio structures |
| CN104701255A (en) * | 2015-03-18 | 2015-06-10 | 信利（惠州）智能显示有限公司 | Preparation method for lower substrate of liquid crystal display |
| CN107507869A (en) * | 2017-09-20 | 2017-12-22 | 武汉华星光电半导体显示技术有限公司 | Low-temperature polysilicon film transistor and preparation method thereof and array base palte |
| CN108198745A (en) * | 2017-12-28 | 2018-06-22 | 信利（惠州）智能显示有限公司 | Source-drain electrode film forming pre-treating method |
| CN108346561A (en) * | 2018-02-09 | 2018-07-31 | 信利（惠州）智能显示有限公司 | Polysilicon layer processing method and processing system before gate insulating layer film forming |
| CN108346572A (en) * | 2018-02-09 | 2018-07-31 | 信利（惠州）智能显示有限公司 | The surface treatment method of silicon oxide film and silicon nitride film |
| CN108400090A (en) * | 2017-12-22 | 2018-08-14 | 信利（惠州）智能显示有限公司 | Prevent the processing method of Al corruption |
-
2018
- 2018-09-13 CN CN201811067545.9A patent/CN109192664A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN88100380A (en) * | 1987-01-23 | 1988-10-19 | 德索托公司 | Form the monolayer carbon fluorine cpd protective cover of anodized aluminum table |
| US6209483B1 (en) * | 1996-10-17 | 2001-04-03 | Accord S. E. G. | Apparatus and method for removing silicon dioxide residues from CVD reactors |
| US6069087A (en) * | 1998-08-25 | 2000-05-30 | Micron Technology, Inc. | Highly selective dry etching process |
| US6235640B1 (en) * | 1998-09-01 | 2001-05-22 | Lam Research Corporation | Techniques for forming contact holes through to a silicon layer of a substrate |
| US20030003755A1 (en) * | 2001-06-28 | 2003-01-02 | Micron Technology, Inc. | Etching of high aspect ratio structures |
| CN104701255A (en) * | 2015-03-18 | 2015-06-10 | 信利（惠州）智能显示有限公司 | Preparation method for lower substrate of liquid crystal display |
| CN107507869A (en) * | 2017-09-20 | 2017-12-22 | 武汉华星光电半导体显示技术有限公司 | Low-temperature polysilicon film transistor and preparation method thereof and array base palte |
| CN108400090A (en) * | 2017-12-22 | 2018-08-14 | 信利（惠州）智能显示有限公司 | Prevent the processing method of Al corruption |
| CN108198745A (en) * | 2017-12-28 | 2018-06-22 | 信利（惠州）智能显示有限公司 | Source-drain electrode film forming pre-treating method |
| CN108346561A (en) * | 2018-02-09 | 2018-07-31 | 信利（惠州）智能显示有限公司 | Polysilicon layer processing method and processing system before gate insulating layer film forming |
| CN108346572A (en) * | 2018-02-09 | 2018-07-31 | 信利（惠州）智能显示有限公司 | The surface treatment method of silicon oxide film and silicon nitride film |
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