CN109166919A - Shield gate power MOSFET device and preparation method thereof - Google Patents
Shield gate power MOSFET device and preparation method thereof Download PDFInfo
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- CN109166919A CN109166919A CN201810757764.3A CN201810757764A CN109166919A CN 109166919 A CN109166919 A CN 109166919A CN 201810757764 A CN201810757764 A CN 201810757764A CN 109166919 A CN109166919 A CN 109166919A
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- 238000002360 preparation method Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000000605 extraction Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 238000001459 lithography Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of shielding gate power MOSFET devices.The invention also discloses a kind of shielding gate power MOSFET device production methods, prepare an epitaxial substrate, carry out trench lithography etching to the epitaxial substrate, form groove；Sidewall dielectric layers are formed in the trench；It carries out shield grid filling in the sidewall dielectric layers formed and returns to carve to epitaxial substrate surface；Shield grid is continued back to carve, shield grid is returned and carves to epitaxial substrate surface；It carries out the second dielectric layer filling in the trench and returns to carve to epitaxial substrate surface；In the trench with the surface deposition control gate of epitaxial substrate, the control gate deposited at shield grid extraction is filled to groove two sides；Control gate carve, control gate is returned and carves to epitaxial substrate surface, form control gate.The present invention can save lithography step, reduce cost of manufacture.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of shield grid power MOSFET (metal-oxide
Object semiconductor field effect transistor) device.The invention further relates to a kind of shielding gate power MOSFET device production methods.
Background technique
Existing shielding gate power MOSFET device structure is as shown in Figure 1, wherein and 1 is epitaxial substrate, and 2 be dielectric layer, 3
It is control gate for shield grid, 4,5 be trap, and 6 be source region, and 7 be ILD (separation layer) medium, and 8 be front conductive film, and 9 contact for trap
Layer, 10 be back side conductive film.
Existing shielding gate power MOSFET device process for making is as follows:
Step 1, as shown in connection with fig. 3 carries out trench lithography etching (the 1st exposure), forms groove on epitaxial substrate.
Step 2, referring to fig. 4, forms sidewall dielectric layers in the trench.
Step 3, as shown in connection with fig. 5 carries out shield grid filling and returns to carve in the sidewall dielectric layers formed.
Step 4, as shown in connection with fig. 6 carries out shield grid chemical wet etching (second expose).
Step 5, referring to Fig. 7, carry out second dielectric layer filling in the shield grid upper end for having completed etching and polish.
Step 6, referring to Fig. 8, chemical wet etching (third time exposes) is carried out to the second dielectric layer.
Step 7, as shown in connection with fig. 9 carries out control gate filling and returns to carve in the second dielectric layer upper end for having completed etching,
Form control gate.
Step 8, as shown in connection with fig. 1, forms trap in the upper end of the epitaxial substrate, carries out source photoetching in the upper end of the trap
Injection (the 4th exposure), forms source region, deposits ILD dielectric layer in the upper end of the control gate and source region.In the ILD medium
Contact hole chemical wet etching (five times exposure) is carried out in layer, forms contact hole, trap contact layer is formed in the contact hole, in institute
It states and deposits front side conductive metal (the 6th exposure) in ILD dielectric layer upper end and contact hole, and carry out chemical wet etching, described outer
The back side (i.e. lower end) of epitaxial substrate forms back side conductive metal and is thinned, and finally formed device is as shown in Figure 1.
It at least needs to carry out 6 photoetching in above-mentioned existing shielding gate power MOSFET device process for making.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of shielding gate power MOSFET devices, can save photoetching step
Suddenly, cost of manufacture is reduced；For this purpose, the present invention also provides a kind of shielding gate power MOSFET device production method.
In order to solve the above technical problems, shielding gate power MOSFET device of the invention, comprising:
One epitaxial substrate, the shield grid formed in the upper end of the epitaxial substrate, the shield grid are coated on by dielectric layer
In groove；It is located at the control gate that shield grid upper end is formed in the groove；Expose second in groove at shield grid extraction to be situated between
Electric layer surface, the groove opening at shield grid extraction form U-shaped structure；The trap formed in the upper end of the epitaxial substrate,
The source region that the upper end of the trap is formed in the upper end of the epitaxial substrate is situated between in the control gate and source region and second
The ILD dielectric layer of the upper end deposit of electric layer, the shield grid being respectively formed in the ILD dielectric layer draw contact hole, trap contact
Hole and control gate contact hole；The trap contact layer in contact hole, trap contact hole and control gate contact hole is drawn positioned at shield grid, in institute
The front side conductive metal deposited in ILD dielectric layer upper end and contact hole is stated, is led at the back side that the back side of the epitaxial substrate is formed
Electric metal.
Shielding gate power MOSFET device production method of the invention, includes the following steps:
Step 1 prepares an epitaxial substrate, and the upper end of the epitaxial substrate deposits one layer of first dielectric layer, to the epitaxial base
Piece carries out trench lithography etching, forms groove, and keep the groove width at shield grid extraction sufficiently large；
Step 2 forms sidewall dielectric layers in the trench；
Step 3 carries out shield grid filling and returns to carve to epitaxial substrate surface in the sidewall dielectric layers formed；
Step 4 continues back to carve to the shield grid, returns shield grid and carves to epitaxial substrate surface；
Step 5 carries out the second dielectric layer filling in the groove, and return carve to epitaxial substrate surface hereinafter,
Step 6, in the groove with the surface deposition control gate of epitaxial substrate, the control gate deposited at shield grid extraction
It is filled to groove two sides, forms U-shaped structure；
Step 7 carve to control gate, returns control gate and carves to epitaxial substrate surface, forms control gate；
Step 8 forms trap in the upper end of the epitaxial substrate, carries out source photoetching injection in the upper end of the trap, forms source
Area；ILD dielectric layer is deposited in the upper end of the control gate and source region and the second dielectric layer, is carried out in the ILD dielectric layer
Contact hole chemical wet etching forms shield grid and draws contact hole, trap contact hole and control gate contact hole, connects in shield grid extraction
Trap contact layer is formed in contact hole, trap contact hole and control gate contact hole, is deposited just in ILD dielectric layer upper end and contact hole
Face conductive metal, and carry out chemical wet etching, form back side conductive metal at the back side of the epitaxial substrate and be thinned, it is formed final
Device.
Groove width at shield grid extraction is sufficiently large, refers to that the groove width arrives greatly and fills out discontented ditch after control gate filling
Slot, control gate material has been removed completely above epitaxial substrate surface and shield grid after control gate is returned and carved, and shield grid is enable to exist
It is picked out during contact hole etching by lead.
The present invention is using once without the control gate etching substitution shield grid of photoetching process, the total light twice of second dielectric layer
It carves, saves 2 layers of lithography step, it is only necessary to which minimum four mask effectively reduces cost of manufacture.
Using method of the invention, control gate lead-out area window is done greatly, is filled using large scale window control grid discontented
The characteristics of, it is removed control grid material above shield grid, without additional photoetching process.
In the device that the present invention is formed, above shield grid there is control grid material residual in two sides, since discord current potential connects
Touching, does not influence device performance.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is existing shielding gate power MOSFET device structure chart；
Fig. 2 is improved one embodiment schematic diagram of shielding gate power MOSFET device structure；
Fig. 3~Fig. 9 is existing shielding gate power MOSFET device process for making schematic diagram；
Figure 10~Figure 15 is improved one embodiment schematic diagram of shielding gate power MOSFET device process for making.
Specific embodiment
As shown in connection with fig. 2, improved shielding gate power MOSFET device process for making, in the following embodiments
Include the following steps:
Step 1: as shown in connection with fig. 10, preparing an epitaxial substrate 1, the upper end of the epitaxial substrate 1 deposits one layer of first dielectric
Layer 12 carries out trench lithography etching (the 1st exposure) to the epitaxial substrate 1, forms groove, and make at shield grid extraction
Groove width is sufficiently large, and the size at shield grid extraction can in this way done greatly, prevents control gate from filling up.
Step 2: forming sidewall dielectric layers 2 in the trench referring to Figure 10.
Step 3: being carried out in the sidewall dielectric layers formed outside shield grid filling and Hui Kezhi in conjunction with shown in Figure 11
1 surface of epitaxial substrate.
Step 4: continuing back to carve to the shield grid in conjunction with shown in Figure 12, returns shield grid and carve to epitaxial substrate 1
Surface makes shield grid 3 protrude from sidewall dielectric layers 2 hereinafter, even if sidewall dielectric layers 2 and shield grid 3 are located in groove 11.?
There is no exposure technology step in the step.
Step 5: carrying out the second dielectric layer filling in the groove, and return and carve to epitaxial substrate 1 in conjunction with shown in Figure 13
Surface hereinafter, i.e. be located in the groove, make the second dielectric layer that sidewall dielectric layers 12 and shield grid 3 be completely covered.Do not have in this step
There is exposure technology step.
Step 6: referring to Figure 14, in the groove with the surface deposition control gate of epitaxial substrate.Since shield grid is drawn
The groove width size at place is sufficiently large, i.e., the size at shield grid extraction is wide, and control gate is caused to be filled to both sides, is formed U-shaped
Structure.
Step 7: it is shown in Figure 15, control gate carve, control gate is returned and carves to 1 surface of epitaxial substrate, formed
Control gate 4.Since the size at shield grid extraction is wide, so that the polysilicon above groove inner shield grid at shield grid extraction
(control gate deposited) is removed, until the second dielectric layer surface, only in the side wall of groove, there are slight control gate etching residues
But current potential is not connect, on device performance without influence, the control gate above remaining groove inner shield grid is unaffected.Do not have in this step
There is exposure technology step.
Step 8: as shown in connection with fig. 2, forming trap 5 in the upper end of the epitaxial substrate 1, source is carried out in the upper end of the trap 5
Photoetching injection (second of exposure), forms source region 6.It is deposited in the upper end of the control gate 4 and source region 6 and the second dielectric layer
ILD (it is noted that its Chinese please be provide) dielectric layer 7.Contact hole chemical wet etching (third is carried out in the ILD dielectric layer 7
Secondary exposure), it forms shield grid and draws contact hole, trap contact hole and control gate contact hole, draw contact hole, trap in the shield grid
Trap contact layer 9 is formed in contact hole and control gate contact hole, and front is deposited in 7 upper end of ILD dielectric layer and contact hole and is led
Electric metal 8 (the 4th exposure), and chemical wet etching is carried out, it is conductive to form the back side at the back side (i.e. lower end) of the epitaxial substrate 1
Metal 10 is simultaneously thinned, and finally formed device is as shown in Figure 2.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of shielding gate power MOSFET device characterized by comprising an epitaxial substrate, in the upper end of the epitaxial substrate
The shield grid formed in portion, the shield grid are coated in the trench by dielectric layer；It is located at shield grid upper end in the groove to be formed
Control gate；Expose the second dielectric layer surface in groove at shield grid extraction, the groove opening at shield grid extraction forms U-shaped
Structure；The trap formed in the upper end of the epitaxial substrate, the upper end of the trap in the upper end of the epitaxial substrate
The source region of formation is situated between in the ILD dielectric layer of the upper end of the control gate and source region and the second dielectric layer deposit in the ILD
The shield grid being respectively formed in matter layer draws contact hole, trap contact hole and control gate contact hole；Positioned at shield grid draw contact hole,
Trap contact layer in trap contact hole and control gate contact hole, the front deposited in ILD dielectric layer upper end and contact hole are led
Electric metal, in the back side conductive metal that the back side of the epitaxial substrate is formed.
2. device as described in claim 1, it is characterised in that: the groove width at shield grid extraction is sufficiently large, i.e. the groove
Width, which arrives greatly, fills out discontented groove after control gate filling, the control gate above epitaxial substrate surface and shield grid after control gate is returned and carved
Material has been removed completely, and shield grid is enable to be picked out during contact hole etching by lead.
3. a kind of shielding gate power MOSFET device production method, which comprises the steps of:
Step 1 prepares an epitaxial substrate, and the upper end of the epitaxial substrate deposits one layer of first dielectric layer, to the epitaxial substrate into
Row trench lithography etching, forms groove, and keep the groove width at shield grid extraction sufficiently large；
Step 2 forms sidewall dielectric layers in the trench；
Step 3 carries out shield grid filling and returns to carve to epitaxial substrate surface in the sidewall dielectric layers formed；
Step 4 continues back to carve to the shield grid, returns shield grid and carves to epitaxial substrate surface；
Step 5 carries out the second dielectric layer filling in the groove, and return carve to epitaxial substrate surface hereinafter,
Step 6, in the groove with the surface deposition control gate of epitaxial substrate, the control gate deposited at shield grid extraction is to ditch
The filling of slot two sides, forms U-shaped structure；
Step 7 carve to control gate, returns control gate and carves to epitaxial substrate surface, forms control gate；
Step 8 forms trap in the upper end of the epitaxial substrate, carries out source photoetching injection in the upper end of the trap, forms source region；?
The upper end of the control gate and source region and the second dielectric layer deposits ILD dielectric layer, carries out contact hole in the ILD dielectric layer
Chemical wet etching forms shield grid and draws contact hole, trap contact hole and control gate contact hole, the shield grid draw contact hole,
Trap contact layer is formed in trap contact hole and control gate contact hole, and front is deposited in ILD dielectric layer upper end and contact hole and is led
Electric metal, and carry out chemical wet etching, form back side conductive metal at the back side of the epitaxial substrate and be thinned, form final device
Part.
4. method as claimed in claim 3, it is characterised in that: return and carved to epitaxial substrate surface hereinafter, being side wall described in step 4
Dielectric layer and shield grid are located in the groove, and shield grid is made to protrude from sidewall dielectric layers.
5. method as claimed in claim 3, it is characterised in that: return and carved to referring to the below epitaxial substrate surface described in step 5
Two dielectric layers are located in the groove, and make the second dielectric layer that sidewall dielectric layers and shield grid be completely covered.
6. method as claimed in claim 3, it is characterised in that: control gate described in step 7, which returns, to be carved, so that at shield grid extraction
The control gate of deposit above groove inner shield grid is removed, until the second dielectric layer surface.
7. method as claimed in claim 3, it is characterised in that: the groove width at shield grid extraction described in step 1 is sufficiently large,
Refer to that the groove width arrives greatly and fills out discontented groove after control gate filling, epitaxial substrate surface and shield grid after control gate is returned and carved
Top control gate material has been removed completely, and shield grid is enable to be picked out during contact hole etching by lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810757764.3A CN109166919A (en) | 2018-07-11 | 2018-07-11 | Shield gate power MOSFET device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810757764.3A CN109166919A (en) | 2018-07-11 | 2018-07-11 | Shield gate power MOSFET device and preparation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN109166919A true CN109166919A (en) | 2019-01-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810757764.3A Pending CN109166919A (en) | 2018-07-11 | 2018-07-11 | Shield gate power MOSFET device and preparation method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034712A (en) * | 2009-09-23 | 2011-04-27 | 万国半导体股份有限公司 | Direct contact in trench with three-mask shield gate process |
| US20130168731A1 (en) * | 2011-12-30 | 2013-07-04 | Force Mos Technology Co., Ltd. | Semiconductor power device having wide termination trench and self-aligned source regions for mask saving |
-
2018
- 2018-07-11 CN CN201810757764.3A patent/CN109166919A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034712A (en) * | 2009-09-23 | 2011-04-27 | 万国半导体股份有限公司 | Direct contact in trench with three-mask shield gate process |
| US20130168731A1 (en) * | 2011-12-30 | 2013-07-04 | Force Mos Technology Co., Ltd. | Semiconductor power device having wide termination trench and self-aligned source regions for mask saving |
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Application publication date: 20190108 |