CN109166882A - Display panel and forming method thereof, display device - Google Patents
Display panel and forming method thereof, display device Download PDFInfo
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- CN109166882A CN109166882A CN201810866804.8A CN201810866804A CN109166882A CN 109166882 A CN109166882 A CN 109166882A CN 201810866804 A CN201810866804 A CN 201810866804A CN 109166882 A CN109166882 A CN 109166882A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/82—Cathodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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Abstract
The present invention relates to a kind of display panel and forming method thereof, display device, display panel includes: array substrate；Pixel defining layer is formed in array substrate, and pixel defining layer defines multiple pixel definition openings；Luminescent layer is formed in pixel definition opening；Cathode layer covers pixel defining layer and luminescent layer；Display panel further includes the recessed portion for being formed in pixel defining layer and deviating from array substrate side, is electrically connected to form cathode return circuit between the cathode layer being covered in recessed portion and the cathode layer for being covered in each luminescent layer.Above-mentioned display panel, when external force is in pixel defining layer, pixel defining layer takes the lead in far from the surface of the not formed recessed portion in array substrate side by external force, and since the cathode layer of covering recessed portion can form complete cathode return circuit with the cathode layer for being covered in each luminescent layer, therefore in the case where part cathode layer is damaged, cathode return circuit is still connected, and display panel still can normally be shown.
Description
Technical field
The present invention relates to field of display devices, more particularly to a kind of display panel and forming method thereof, display device.
Background technique
In recent years, with the development of society and the progress of science and technology, the technology development of intelligent terminal and wearable device
Make rapid progress, the requirement for FPD is also gradually increased, and demand is also more and more diversified.OLED(Organic Light-
Emitting Diode, Organic Light Emitting Diode) display device due to compared with liquid crystal display have more low-power consumption, have simultaneously
Have higher brightness and a response speed, and it is flexible, there is good flexibility, therefore be applied to hand more and more widely
In the smart terminal products such as machine, tablet computer even TV, become the main flow display of display field.
But since material and structure limit, the shock resistance of OLED display device is weaker, aobvious when there is weight to hit OLED
When showing device, the region hit, which is easy to appear, shows bad situation, to seriously affect the use of OLED display device
Service life and stability in use.
Summary of the invention
Based on this, it is necessary to aiming at the problem that can not normally showing when OLED display device is by external impacts, provide one
Kind improves display panel of the above problem and forming method thereof, display device.
A kind of display panel, comprising:
Array substrate；
Pixel defining layer is formed in the array substrate, and the pixel defining layer defines multiple pixel definition openings；
Luminescent layer is formed in the pixel definition opening；And
Cathode layer is covered in the pixel defining layer and the luminescent layer；
The display panel further includes the recessed portion for being formed in the pixel defining layer and deviating from the array substrate side, is covered
Yin is electrically connected to form between the cathode layer being placed in the recessed portion and the cathode layer for being covered in each luminescent layer
Pole circuit.
Above-mentioned display panel, when being not affected by external force or external force is smaller, cathode layer cover pixel defining layer with
Luminescent layer and form an entire cathode return circuit, be covered in the cathode layer of each luminescent layer and pass through the yin that is covered in pixel defining layer
Pole layer mutual conduction.When certain external force is in pixel defining layer, pixel defining layer is not formed far from array substrate side
Surface (i.e. region of the distance of pixel defining layer facing arrays substrate greater than the distance of recessed portion facing arrays substrate of recessed portion
Surface) it is likely to damage due to taking the lead in by external force and the larger external force that is subject to.And at this point, due to there are difference in height, because
This cathode layer for being covered in recessed portion can't directly bear external force, be covered in the cathode layer of recessed portion be covered in it is luminous
The cathode layer of layer still forms complete cathode return circuit, to cover each shine in the case where part cathode layer is damaged
Still mutual conduction, display panel still can normally be shown the cathode layer of layer.
Optionally, the recessed portion is formed in the interval region between each pixel definition opening.
Optionally, the cathode layer whole face be covered in the pixel defining layer away from the array substrate side surface,
Luminescent layer and the recessed portion.
Optionally, the cathode layer being covered in the recessed portion and the cathode layer for being covered in each luminescent layer
Series connection forms the cathode return circuit.
Optionally, the recessed portion includes a plurality of interlaced link slot, and each pixel definition open communication is extremely
A few link slot, any one link slot intersect at least one link slot in addition to itself.
Optionally, a plurality of interlaced link slot forms the connection master around each pixel definition opening
Connection branch between road, and each pixel definition opening of connection and the corresponding connection main road.
Optionally, the link slot includes bottom wall and the side wall positioned at the bottom wall opposite sides；
Angle between the side wall and bottom wall of the link slot is 100 ° -160 °.
Optionally, in the direction perpendicular to the array substrate, the size in the section of the link slot is from close to described
Array substrate one is laterally away from the array substrate side and is gradually increased.
Optionally, the depth of the link slot is the 20%-80% of the pixel defining layer thicknesses of layers.
A kind of display device, including display panel described in above-described embodiment.
A kind of display panel forming method, comprising the following steps:
Array basal plate is provided；
Pixel defining layer is formed in the array substrate；The pixel defining layer defines multiple pixel definition openings；
Recessed portion is formed away from the array substrate side in the pixel defining layer；
Luminescent layer is formed in the pixel definition is open；
The cathode layer for being covered in the pixel defining layer and the luminescent layer is formed, is covered in described in the recessed portion
Cathode return circuit is electrically connected to form between cathode layer and the cathode layer for being covered in each luminescent layer.
Above-mentioned display panel forming method, due to foring the recessed portion of recess in pixel defining layer, to work as pixel
When the cathode layer that definition layer is not provided with the region of recessed portion damages under external force, be covered in the cathode layer of recessed portion still with
The cathode layer connection webbed cathode return circuit of shape being covered on luminescent layer, to guarantee the cathode layer phase mutual conductance of covering luminescent layer
It is logical.Due to, without increasing additional buffer structure, avoiding the thickness for increasing display panel by the way of subtracting material processing
Degree brings other problems without adaptive change is carried out to other structures while avoiding cathode layer from damaging.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the display panel of one embodiment of the invention；
Fig. 2 is the top view of display panel shown in FIG. 1；
Fig. 3 is that the receiving of display panel shown in FIG. 1 hits the structural schematic diagram after being damaged；
Fig. 4 is that display panel shown in Fig. 2 bears to hit the structural schematic diagram after being damaged；
Fig. 5 is the structural schematic diagram of the display panel of another embodiment of the present invention；
Fig. 6 is the flow chart of the forming method of the display panel of one embodiment of the invention.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing
Give presently preferred embodiments of the present invention.But the invention can be realized in many different forms, however it is not limited to this paper institute
The embodiment of description.On the contrary, purpose of providing these embodiments is keeps the understanding to the disclosure more thorough
Comprehensively.
It should be noted that it can directly on the other element when element is referred to as " being fixed on " another element
Or there may also be elements placed in the middle.When an element is considered as " connection " another element, it, which can be, is directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " left side ",
" right side " and similar statement are for illustrative purposes only.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the listed item of pass.
When describing positional relationship, unless otherwise defined, when an element such as layer, film or substrate are regarded as another
When element "upper", intermediary element can may be present directly in other elements or also.Furtherly, when layer is regarded as in another layer
When "lower", one or more middle layers can also may be present directly in lower section.It can also understand, when layer is regarded as at two layers
" between " when, it can be the sole layer between two layers, or one or more middle layers also may be present.
Using " comprising " described herein, " having " and "comprising", unless having used specific restriction
Term, such as " only ", " by ... form " etc., it otherwise can also add another component.Unless refer on the contrary, otherwise singular shape
The term of formula may include plural form, and can not be interpreted as its quantity is one.
It will be appreciated that though term " first ", " second " etc. can be used herein to describe various elements, but these yuan
Part should not be limited by these terms.These terms are only used to distinguish an element and another element.For example, not taking off
In the case where the scope of the present invention, first element can be referred to as second element, and similarly, and second element can be claimed
For first element.
It is to be further understood that, although not being expressly recited, element is construed to include error model when explaining element
It encloses.For example, pixel defining layer defines multiple pixel definition openings, and the spacer region between each pixel definition opening
Domain, interval region can be using the sides that pixel definition is open as boundary, and the side that opening can also be defined with range pixel is certain
The position of distance is boundary, is not limited thereto.
Fig. 1 shows the structural schematic diagram of the display panel in one embodiment of the invention；Fig. 2 shows shown in FIG. 1 aobvious
Show the top view of panel.For ease of description, attached drawing illustrates only structure relevant to the embodiment of the present invention.
Refering to attached drawing, a kind of display panel 100 provided in an embodiment of the present invention, including array substrate 20, pixel defining layer
40, luminescent layer 60 and cathode layer 80.Pixel defining layer 40, luminescent layer 60 and cathode layer 80 are sequentially formed in array substrate 20
On.
Array substrate 20 includes underlay substrate 21 (for example, PI material is formed), the thin film transistor (TFT) for being set to underlay substrate
Layer 23 and anode layer 25.Certainly, which can also include the film layers such as planarization layer, passivation layer, be not limited thereto.
Underlay substrate 21 has multiple pixel regions, and each pixel region includes the first sub-pixel area domain, the second sub-pixel
Region and third subpixel area.In one embodiment, the first sub-pixel area domain be emit feux rouges subpixel area, second
Subpixel area is to emit the subpixel area of green light, and third subpixel area is to emit the subpixel area of blue light.One group
The first sub-pixel area domain, the second subpixel area and third subpixel area may make up a pixel region.
It is appreciated that each pixel region also may include other subpixel areas, herein not in some other embodiment
It limits, for example, may also include the 4th subpixel area of transmitting white light.
The stacking of tft layer 23 is set to 21 1 side surface of underlay substrate, shines for controlling pixel region.Specifically,
Tft layer 23 includes multiple thin film transistor (TFT)s.Each thin film transistor (TFT) includes the grid electricity being formed on underlay substrate 21
Pole, cover on gate electrode gate insulating layer, the active layer that is formed on gate insulating layer and be formed on active layer
Source electrode and drain electrode.It is appreciated that above-mentioned thin film transistor (TFT) is illustrated by taking bottom gate type as an example, the present invention does not limit herein
Fixed, in some other embodiment, thin film transistor (TFT) can be top gate type.
In some embodiments, since tft layer 23 has the layer structure of above-mentioned complexity, top surface may
Unevenness, thus planarization layer covers tft layer 23 far from 21 side of underlay substrate to form sufficiently flat surface.
After forming planarization layer, through-hole can be offered in planarization layer with the source electrode or drain electrode of exposed film transistor.
Anode layer 25 is formed on planarization layer, for example, anode layer 25 includes multiple first sub-pixels in some embodiments
Electrode, the second pixel electrode and third pixel electrode.First pixel electrode is formed in the first sub-pixel area domain, and second
Pixel electrode is formed in the second subpixel area, and third pixel electrode is formed in third subpixel area, the first sub-pixel
Electrode, the second pixel electrode or third pixel electrode can be electrically connected to tft layer by the through-hole of planarization layer
23。
Pixel defining layer 40 is formed in array substrate 20, and at least part of the pixel electrode of exposure anode layer 25.
For example, pixel defining layer 40 can cover at least part at the edge of each pixel electrode, thus extremely by each pixel electrode
Few a part is exposed.In this way, pixel defining layer 40 has defined multiple pixel definition openings 41 and has been located at each pixel definition
Interval region between opening 41, each pixel definition opening 41 respectively with the first pixel electrode, the second pixel electrode or
Third pixel electrode is corresponding to expose the central part of pixel electrode, to form the output optical zone domain of multiple exposed sub-pixels
With the non-outgoing area of multiple covering sub-pixels.
In this way, pixel defining layer 40 can increase the end of each pixel electrode and be formed on each pixel electrode
The distance between opposite electrode (cathode layer 80), and the antireflection that can prevent the end of pixel electrode from occurring.
The luminescent layer 60 to form covering array substrate 20 is deposited in luminous organic material, and luminous organic material is in pixel definition
Layer 40 restriction under at be deposited on pixel definition opening 41 in, therefore be located at each pixel definition opening 41 in luminescent layer 60 by
Pixel defining layer 40 is mutually isolated and avoids interfering with each other.
Cathode layer 80 covers surface and pixel defining layer 40 of the luminescent layer 60 far from 20 side of array substrate far from array base
The surface of 20 side of plate and form an entire cathode circuit.In some embodiments, cathode layer 80 can be used silver, lithium, magnesium,
Calcium, strontium, aluminium, the lower metal of indium constant power function, or be made of metallic compound or alloy material.
In this way, under the driving of tft layer 23, electronics and hole are respectively from cathode layer 80 and anode layer 25 to hair
Photosphere 60 injects, and injected electrons and hole are in luminescent layer 60 in conjunction with being reduced into central element.By above-mentioned in conjunction with mistake
Journey, organic molecule energy are activated, and electronic state turns to the state (excitation state) of high-energy from stable state (ground state), into
And because of excitation state and its unstable and original ground state can be returned to, energy is released and shows as the form of " light " at this time.
Although it is desirable to without being bound by theory, inventor has found under study for action, in array substrate 20, due to pixel defining layer
40 are convexly equipped in the surface of array substrate 20 and have certain altitude, therefore when weight hits display panel 100, pixel defining layer
40 top surface (i.e. pixel defining layer 40 is far from 20 side of array substrate and with array substrate 20 apart from maximum surface) more first connects
Be hit and the impact force being subject to be larger, thus the cathode layer 80 for being covered on the top surface of pixel defining layer 40 be easily damaged and
Open circuit is caused, and then causes multiple cathode layers 80 in pixel definition opening 41 that can not be connected and can not normally show.
Therefore, how to avoid the cathode layer 80 in pixel defining layer 40 from damaging under external force percussion is the current field
One of allowed important technical challenges faced.
Fig. 1 and Fig. 2 is please referred to, in an embodiment of the present invention, display panel 100 further includes being formed in pixel defining layer 40
Recessed portion away from 20 side of array substrate, the cathode layer 80 being covered in recessed portion and the cathode layer for being covered in each luminescent layer 60
Cathode return circuit is electrically connected to form between 80.
Fig. 1 and Fig. 2 is please referred to, 80 whole face of cathode layer is covered in the table that pixel defining layer 40 deviates from 20 side of array substrate
Face, luminescent layer 60 and recessed portion.It further says, the top surface in pixel defining layer 40, recess is deposited in 80 whole face of cathode layer
On luminescent layer 60 in portion and in pixel definition opening 41.Therefore when being not affected by external force or external force is smaller, cathode
The top surface of pixel defining layer 40 is completely covered in layer 80, in recessed portion and luminescent layer 60 and form an entire cathode and return
Road is covered in the cathode layer 80 of each luminescent layer 60 and passes through the 80 phase mutual conductance of cathode layer that is covered on pixel defining layer 40 and recessed portion
It is logical.
It should be understood that the OLED device of top emitting can be obviously improved the aperture opening ratio of OLED device, can be improved simultaneously
Pixel PPI density, but cathode layer 80 generallys use silver, the lower transparent electrode of magnesium constant power function, and there are RSResistance value is higher
The problem of, influence the uniformity of the characteristics such as 100 display brightness of display panel.And by the way that recessed portion, and whole face evaporation cathode is arranged
Layer 80 can effectively reduce the resistance of cathode layer 80, improve the electric conductivity of cathode layer 80, reduce the power consumption of display panel 100, and
The IR pressure drop for reducing cathode layer 80 improves the uniformity of the characteristics such as 100 brightness of display panel, improves display panel 100
Quality.
Fig. 3 shows the display panel in one embodiment of the invention and bears to hit the structural schematic diagram after being damaged；Fig. 4 is shown
Display panel shown in Fig. 2 bear to hit it is impaired after top view.Implement for ease of description, attached drawing is illustrated only with the present invention
The relevant structure of example.
Refering to attached drawing 3 and attached drawing 4, when certain external force (for example, the impact force for falling shock) acts on pixel defining layer 40
When upper, surface (the i.e. top table of pixel defining layer 40 of the pixel defining layer 40 far from the not formed recessed portion in 20 side of array substrate
Face) because take the lead in by external force and the external force that is subject to it is larger due to damage, for example, fracture, with pixel defining layer 40 and luminescent layer
60 separation.And at this point, due to there are difference in height, the cathode layer 80 for being covered in recessed portion can't directly bear outer masterpiece
With, the cathode layer 80 for being covered in recessed portion still forms complete cathode return circuit with the cathode layer 80 for being covered in luminescent layer 60, from
And in the case where part cathode layer 80 is damaged, the cathode layer 80 of each luminescent layer 60 still mutual conduction, display surface are covered
Plate 100 still can normally be shown.
Please continue to refer to Fig. 1 and Fig. 2, in some embodiments, between recessed portion is formed between each pixel definition opening 41
Septal area domain.In this way, convenient for being formed using patterning processes, and the aperture opening ratio of display panel 100 is not influenced.For example, specific to some
In embodiment, recessed portion includes a plurality of interlaced link slot 43, each 41 connection of pixel definition opening, at least one connection
Slot 43, any one link slot 43 intersect at least one link slot 43 in addition to itself.In this way, being covered in each luminescent layer 60
Interior cathode layer 80 can be electrically connected to each other by being covered in the cathode layer 80 of link slot 43.
It is appreciated that the quantity of link slot 43 is without being limited thereto, and in processing technology precision allowed band, each pixel definition
Opening 41 can connect a plurality of link slot 43, every link slot 43 can a plurality of link slot 43 in addition to except itself intersect, to make
Criss-cross mesh cathode is collectively formed in the cathode layer 80 for being covered in link slot 43 and the cathode layer 80 for being covered in luminescent layer 60
Circuit.When cathode layer 80 in part link slot 43 is damaged (as shown in Figures 3 and 4), the cathode layer 80 of each luminescent layer 60 according to
It can be so interconnected by covering the cathode layer 80 of other link slots 43, so that the service life of display panel 100 is improved,
It still can normally be shown in the case where by multiple external force.
In some embodiments, a plurality of interlaced link slot 43 forms the connection around each pixel definition opening 41
Connection branch between main road, and each pixel definition opening 41 of connection and corresponding connection main road.For example, specific to implementation
In example, a plurality of link slot 43 includes lateral connection slot 432 and longitudinally connected slot 434, and lateral connection slot 432 includes main lateral connection
Slot 4321 and branch lateral connection slot 4323, longitudinally connected slot 434 include main longitudinally connected slot 4341 and the longitudinally connected slot 4343 of branch.
Wherein, main lateral connection slot 4321 is interlaced with main longitudinally connected slot 4341 and is surrounded on the outer of each pixel definition opening 41
Week is to form connection main road；Branch lateral connection slot 4323 and prop up longitudinally connected slot 4343 be connected to each pixel definition opening 41 with
It connects and connects branch between main road to be formed.
It is interconnected in this way, each pixel definition opening 41 is connected to connection main road by connection branch.
It is understood that two adjacent pixels define a portion that connection main road can be shared between opening 41,
It also can be respectively around there are two connect main road.Branch between two adjacent pixel definition openings 41 can be communicated as one,
It also can be two mutually independent branches to be connected to connection main road.
In some embodiments, pixel definition opening 41 is in rectangle, and multiple pixel definitions opening 41 is arranged in arrays, laterally
Link slot 432 is perpendicular to vertical link slot 434.For example, in embodiment shown in Fig. 2, the pixel defining layer 40 on the figure includes
Four pixel definition openings 41, four pixel definition openings 41 are arranged in two rows, two column matrix.Three main lateral connection slots 4321
Horizontal direction along Fig. 2 extends, and three longitudinally connected slots 4341 of master extend along the vertical direction of Fig. 2, three main lateral connection slots
4321 and three longitudinally connected slots 4341 of master are interlaced that sphere of movements for the elephants type around four pixel definitions opening 41 is collectively formed
Connect main road.Each pixel definition opening 41 is by two branch lateral connection slots 4323 and the longitudinally connected slot 4343 of two branch and even
Main road connection is connect, and the branch lateral connection slot 4323 of two neighboring pixel definition opening 41 or the longitudinally connected connection of slot 4343 of branch are
One.
It is appreciated that when offering more pixel definition opening 41 in pixel defining layer 40, the setting of link slot 43
Rule is upper similar to figure.In some embodiments, may also set up more link slots 43 makes each pixel definition opening more than 41
A connection main road is surround, and pixel definition opening 41 can also be connected to connection main road by more link slot 43, thus into
Cathode layer 80 in one step guarantee section link slot 43 can also normally in the case where being damaged.
As shown in figure 5, in further embodiments, the cathode layer 80 that is covered in recessed portion and it is covered in each luminescent layer 60
Cathode layer 80 series connection form cathode return circuit.Specifically, each pixel definition opening 41 only passes through a link slot 43 and one
Adjacent 41 connection of pixel definition opening, each link slot 43 is mutually indepedent and is not connected directly.In this way, each pixel definition is opened
Mouth 41 is sequentially communicated, and is covered in the cathode layer 80 of a link slot 43 and the cathode layer 80 for being covered in a luminescent layer 60 replaces connection shape
At cathode return circuit.
Please continue to refer to Fig. 1, link slot 43 includes that bottom wall and the side wall positioned at bottom wall opposite sides, cathode layer 80 cover completely
The bottom wall and side wall of lid link slot 43 are with biggish area coverage.Specifically in some embodiments, the side wall of link slot 43
Angle between bottom wall is 100 ° -160 °, to can prevent external force while guaranteeing that cathode layer 80 has enough thickness
The cathode layer 80 that link slot 43 is covered in impact process is damaged.Since cathode layer 80 is side of the cathode material using vapor deposition
Method is deposited on the bottom wall and side wall of link slot 43, therefore when the angle between the side wall of link slot 43 and bottom wall is less than 100 °,
Cathode material is difficult to be deposited on side wall and keeps the thickness of cathode layer 80 excessively thin and be easy to be damaged, and works as the side of link slot 43
When angle between wall and bottom wall is greater than 160 °, the bottom wall of link slot 43 is easy the impact by external force, to make to be covered on it
On cathode layer 80 be damaged.
It is appreciated that link slot 43 is not limited to above-mentioned shape, as long as in the direction perpendicular to array substrate 20, link slot
The size in 43 section is laterally away from 20 side of array substrate from close array substrate 20 and is gradually increased.In this way, logical
Cross vapor deposition the methods of formed be covered in link slot 43 bottom wall and side wall cathode layer 80 when, can avoid side wall to evaporation material shape
Cover the bottom wall of link slot 43 by cathode layer 80 completely with side wall.
In some embodiments, depth of the link slot 43 in the direction perpendicular to array substrate 20 is pixel defining layer 40
The 20%-80% of thicknesses of layers in the direction perpendicular to array substrate 20, to be covered on the bottom wall for avoiding link slot 43
While the cathode layer 80 of lid is damaged, avoids the hypotelorism of cathode layer 80 and anode layer 25 and overlap and cause short circuit.And
When 20% or less the thickness that the depth of link slot 43 is pixel defining layer 40, the depth of link slot 43 is too small, causes to connect
The hypotelorism of the top surface of the bottom wall and pixel defining layer 40 of slot 43, thus be difficult to the cathode layer 80 reached avoid on bottom wall by
The purpose of impact.And when 80% or more of the thickness that the depth of link slot 43 is pixel defining layer 40, the depth of link slot 43
It is excessive, lead to the hypotelorism of the cathode layer covered on the bottom wall of link slot 43 80 and anode layer 25 and mutually overlap cause it is short
Road.
For convenient for further understanding technical solution of the present invention, the embodiment of the present invention also provides a kind of system of display panel
Make method.
Fig. 6 shows the flow diagram of the forming method of the display panel in one embodiment of the invention；
Refering to attached drawing, a kind of 100 forming method of display panel of one embodiment of the invention, comprising the following steps:
S110: array basal plate 20 is provided.
Specifically in one embodiment, the array substrate 20 include be stacked underlay substrate 21, tft layer 23,
Planarization layer and anode layer 25.
S120: forming pixel defining layer 40 in array substrate 20, which defines multiple pixel definitions
Opening 41.
Specifically in one embodiment, the pixel defining layer of covering anode layer 25 is formed on the anode layer 25 of array substrate 20
40, the pixel electrode of anode 25 is exposed to pixel definition opening 41 to form light emitting region.
S130: recessed portion is formed away from 20 side of array substrate in pixel defining layer 40.
Specifically in one embodiment, the mode of exposure development photoetching can be used in pixel defining layer 40 far from array substrate 20
The surface of side forms a plurality of link slot 43, and recessed portion is collectively formed in a plurality of link slot 43.Certainly, in some other embodiment
In, other patterning processes also can be used and formed, for example, dry etch process can be used.It should be noted that recessed portion can be
After forming pixel definition film layer, formed while forming pixel definition layer pattern；It is also possible to be initially formed pixel defining layer figure
Then case is formed in pixel defining layer 40 away from the side of array substrate 20.
S140: luminescent layer 60 is formed in pixel definition opening 41.
Specifically in one embodiment, it adopts vapor deposition method and is deposited in the array substrate 20 in pixel definition opening 41
Machine luminescent material is to form luminescent layer 60.
S150: the cathode layer 80 for being covered in pixel defining layer 40 and luminescent layer 60, the cathode being covered in recessed portion are formed
Cathode return circuit is electrically connected to form between layer 80 and the cathode layer 80 for being covered in each luminescent layer 60.
In this way, being covered in the cathode layer 80 of recessed portion after the cathode layer 80 of the top surface of pixel defining layer 40 is impaired
Complete netted cathode return circuit is still formed with the cathode layer 80 for being covered in luminescent layer 60, to make to be covered in each luminescent layer 60
80 mutual conduction of cathode layer.
The forming method of above-mentioned display panel 100 is recessed due to being formd in pixel defining layer 40 by way of photoetching
Sunken recessed portion, thus when the cathode layer 80 that pixel defining layer 40 is not provided with the region of recessed portion damages under external force,
The cathode layer 80 for being covered in recessed portion still connect the webbed cathode return circuit of shape with the cathode layer 80 being covered on luminescent layer 60,
To guarantee to cover 80 mutual conduction of cathode layer of luminescent layer 60.Due to additional without increasing by the way of subtracting material processing
Buffer structure, therefore avoid increase display panel 100 thickness, without to other structures carry out adaptive change and keeping away
Exempt to bring other problems while cathode layer 80 damages.
Based on above-mentioned display panel 100, the embodiment of the present invention also provides a kind of display device, in some embodiments,
The display device can be display terminal, such as tablet computer, and in further embodiments, which also can be mobile communication
Terminal, such as mobile phone terminal.
In some embodiments, which includes display panel 100 and control unit, which is used for aobvious
Show 100 transmitting display signal therefor of panel.
In conclusion the formation of the display panel 100 provided in the embodiment of the present invention, display device and display panel 100
Method is formed with recessed portion in the pixel defining layer 40 of display panel 100 and divides cathode layer 80 with protection portion, to fall in weight
In the case where 100 surface of display panel causes cathode layer 80 to damage, there is complete connection to be covered in luminescent layer 60 always
The netted cathode return circuit of cathode layer 80 makes to improve the display reliability of the display device equipped with the display panel 100
Display device still can normally be shown by multiple external force.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (11)
1. a kind of display panel, comprising:
Array substrate；
Pixel defining layer is formed in the array substrate, and the pixel defining layer defines multiple pixel definition openings；
Luminescent layer is formed in the pixel definition opening；And
Cathode layer is covered in the pixel defining layer and the luminescent layer；
It is characterized in that, the display panel further includes being formed in the pixel defining layer away from the recessed of the array substrate side
Concave portion is electrically connected between the cathode layer being covered in the recessed portion and the cathode layer for being covered in each luminescent layer
Form cathode return circuit.
2. display panel according to claim 1, which is characterized in that the recessed portion is formed in each pixel definition and opens
Interval region between mouthful.
3. display panel according to claim 1, which is characterized in that the cathode layer whole face is covered in the pixel definition
Layer deviates from surface, luminescent layer and the recessed portion of the array substrate side.
4. described in any item display panels according to claim 1~3, which is characterized in that the institute being covered in the recessed portion
It states cathode layer and connects to form the cathode return circuit with the cathode layer for being covered in each luminescent layer.
5. described in any item display panels according to claim 1~3, which is characterized in that the recessed portion includes a plurality of mutual
Staggered link slot, link slot described in each pixel definition open communication at least one, any one link slot with
At least one link slot intersection in addition to itself.
6. display panel according to claim 5, which is characterized in that a plurality of interlaced link slot formation surrounds
It is open and the corresponding connection in the connection main road of each pixel definition opening, and each pixel definition of connection
Connection branch between main road.
7. display panel according to claim 5, which is characterized in that the link slot include bottom wall and be located at the bottom wall
The side wall of opposite sides；
Angle between the side wall and bottom wall of the link slot is 100 ° -160 °.
8. display panel according to claim 5, which is characterized in that in the direction perpendicular to the array substrate, institute
The size for stating the section of link slot is laterally away from the array substrate side from the close array substrate one and is gradually increased.
9. display panel according to claim 5, which is characterized in that the depth of the link slot is the pixel defining layer
The 20%-80% of thicknesses of layers.
10. a kind of display device, including display panel as described in any one of claims 1-9.
11. a kind of display panel forming method, which comprises the following steps:
Array basal plate is provided；
Pixel defining layer is formed in the array substrate；The pixel defining layer defines multiple pixel definition openings；
Recessed portion is formed away from the array substrate side in the pixel defining layer；
Luminescent layer is formed in the pixel definition is open；
Form the cathode layer for being covered in the pixel defining layer and the luminescent layer, the cathode being covered in the recessed portion
It layer and is covered between the cathode layer of each luminescent layer and is electrically connected to form cathode return circuit.
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